2 * This file is part of the coreboot project.
4 * Copyright (C) 2007 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 * This file initializes the CPU cores for voltage and frequency settings
21 * in the different power states.
25 checklist (functions are in this file if no source file named)
26 Fam10 Bios and Kernel Development Guide #31116, rev 3.48, April 22, 2010
28 2.4.2.6 Requirements for p-states
30 1.- F3x[84:80] According to table 100 : prep_fid_change
33 2.4.2.9.1 Steps 1,3-6 and warning for 2,7 if they apply
34 fixPsNbVidBeforeWR(...)
35 2.4.2.9.1 Step 8 enable_fid_change
36 We do this for all nodes, I don't understand BKDG 100% on
37 whether this is or isn't meant by "on the local
38 processor". Must be OK.
39 2.4.2.9.1 Steps 9-10 (repeat 1-7 and reset) romstage.c/init_cpus ?
40 2.4.2.9.1 Steps 11-12 init_fidvid_stage2
41 2.4.2.9.2 DualPlane PVI : Not supported, don't know how to detect,
42 needs specific circuitry.
44 3.- 2.4.2.7 dualPlaneOnly(dev)
46 4.- 2.4.2.8 applyBoostFIDOffset(dev)
48 5.- enableNbPState1(dev)
51 a) UpdateSinglePlaneNbVid()
52 b) setVSRamp(), called from prep_fid_change
54 d) improperly, for lack of voltage regulator details?,
55 F3xA0[PsiVidEn] in defaults.h
56 F3xA0[PsiVid] in init_cpus.c AMD_SetupPSIVID_d (before prep_fid_change)
58 7.- TODO (Core Performance Boost is only available in revision E cpus, and we
59 don't seem to support those yet, at least they don't have any
60 constant in amddefs.h )
62 8.- FIXME ? Transition to min Pstate according to 2.4.2.15.3 is required
63 by 2.4.2.6 after warm reset. But 2.4.2.15 states that it is not required
64 if the warm reset is issued by coreboot to update NbFid. So it is required
65 or not ? How can I tell who issued warm reset ?
66 Coreboot transitions to P0 instead, which is not recommended, and does
67 not follow 2.4.2.15.2 to do so.
69 9.- TODO Requires information on current delivery capability
70 (depends on mainboard and maybe power supply ?). One might use a config
71 option with the maximum number of Ampers that the board can deliver to CPU.
73 10.- [Multiprocessor] TODO 2.4.2.12
74 [Uniprocessor] FIXME ? We call setPStateMaxVal() in init_fidvid_stage2,
75 but not sure this is what is meant by "Determine the valid set of
76 P-states based on enabled P-states indicated
77 in MSRC001_00[68:64][PstateEn]" in 2.4.2.6-10
79 11.- finalPstateChange() from init_fidvid_Stage2 (BKDG says just "may", anyway)
81 12.- generate ACPI for p-states. FIXME
82 Needs more assesment. There's some kind of fixed support that
83 does not seem to depend on CPU revision or actual MSRC001_00[68:64]
84 as BKDG apparently requires.
85 http://www.coreboot.org/ACPI#CPU_Power_Management
86 At least for Tilapia board:
87 src/mainboard/<vendor>/<model>/acpi_tables.c write_acpi_tables(...) calls
88 acpi_add_ssdt_pstates(...)
89 in /src/northbridge/amd/amdfam10/amdfam10_acpi.c
90 which apparently copies them from static info in
91 src/mainboard/<vendor>/<model>/acpi/cpstate.asl
93 "must also be completed"
95 a.- PllLockTime set in ruleset in defaults.h
96 BKDG says set it "If MSRC001_00[68:64][CpuFid] is different between
97 any two enabled P-states", but since it does not say "only if"
98 I guess it is safe to do it always.
100 b.- prep_fid_change(...)
104 #if CONFIG_SET_FIDVID
106 #include <northbridge/amd/amdht/AsPsDefs.h>
108 static inline void print_debug_fv(const char *str, u32 val)
110 #if CONFIG_SET_FIDVID_DEBUG
111 printk(BIOS_DEBUG, "%s%x\n", str, val);
115 static inline void print_debug_fv_8(const char *str, u8 val)
117 #if CONFIG_SET_FIDVID_DEBUG
118 printk(BIOS_DEBUG, "%s%02x\n", str, val);
122 static inline void print_debug_fv_64(const char *str, u32 val, u32 val2)
124 #if CONFIG_SET_FIDVID_DEBUG
125 printk(BIOS_DEBUG, "%s%x%x\n", str, val, val2);
133 static void enable_fid_change(u8 fid)
142 for (i = 0; i < nodes; i++) {
143 dev = NODE_PCI(i, 3);
144 dword = pci_read_config32(dev, 0xd4);
146 dword |= (u32) fid & 0x1F;
147 dword |= 1 << 5; // enable
148 pci_write_config32(dev, 0xd4, dword);
149 printk(BIOS_DEBUG, "FID Change Node:%02x, F3xD4: %08x \n", i,
154 static void applyBoostFIDOffset( device_t dev ) {
156 // revision E only, but E is apparently not supported yet, therefore untested
157 if ((cpuid_edx(0x80000007) & CPB_MASK)
158 && ((cpuid_ecx(0x80000008) & NC_MASK) ==5) ) {
159 u32 core = get_node_core_id_x().coreid;
160 u32 asymetricBoostThisCore = ((pci_read_config32(dev, 0x10C) >> (core*2))) & 3;
161 msr_t msr = rdmsr(PS_REG_BASE);
162 u32 cpuFid = msr.lo & PS_CPU_FID_MASK;
163 cpuFid = cpuFid + asymetricBoostThisCore;
164 msr.lo &= ~PS_CPU_FID_MASK;
166 wrmsr(PS_REG_BASE , msr);
171 static void enableNbPState1( device_t dev ) {
172 u32 cpuRev = mctGetLogicalCPUID(0xFF);
173 if (cpuRev & AMD_FAM10_C3) {
174 u32 nbPState = (pci_read_config32(dev, 0x1F0) & NB_PSTATE_MASK);
176 u32 nbVid1 = (pci_read_config32(dev, 0x1F4) & NB_VID1_MASK) >> NB_VID1_SHIFT;
178 for (i = nbPState; i < NM_PS_REG; i++) {
179 msr_t msr = rdmsr(PS_REG_BASE + i);
180 if (msr.hi & PS_EN_MASK ) {
181 msr.hi |= NB_DID_M_ON;
182 msr.lo &= NB_VID_MASK_OFF;
183 msr.lo |= ( nbVid1 << NB_VID_POS);
184 wrmsr(PS_REG_BASE + i, msr);
191 static u8 setPStateMaxVal( device_t dev ) {
193 for (i = 0; i < NM_PS_REG; i++) {
194 msr_t msr = rdmsr(PS_REG_BASE + i);
195 if (msr.hi & PS_IDD_VALUE_MASK) {
196 msr.hi |= PS_EN_MASK ;
197 wrmsr(PS_REG_BASE + i, msr);
199 if (msr.hi | PS_EN_MASK) {
203 //FIXME: CPTC2 and HTC_REG should get max per node, not per core ?
204 u32 reg = pci_read_config32(dev, CPTC2);
205 reg &= PS_MAX_VAL_MASK;
206 reg |= (maxpstate << PS_MAX_VAL_POS);
207 pci_write_config32(dev, CPTC2,reg);
211 static void dualPlaneOnly( device_t dev ) {
214 u32 cpuRev = mctGetLogicalCPUID(0xFF);
215 if ((mctGetProcessorPackageType() == AMD_PKGTYPE_AM3_2r2)
216 && (cpuRev & AMD_DR_Cx)) { // should be rev C or rev E but there's no constant for E
217 if ( (pci_read_config32(dev, 0x1FC) & DUAL_PLANE_ONLY_MASK)
218 && (pci_read_config32(dev, 0xA0) & PVI_MODE) ){
219 if (cpuid_edx(0x80000007) & CPB_MASK) {
220 // revision E only, but E is apparently not supported yet, therefore untested
221 msr_t minPstate = rdmsr(0xC0010065);
222 wrmsr(0xC0010065, rdmsr(0xC0010068) );
223 wrmsr(0xC0010068,minPstate);
227 wrmsr(0xC0010064, rdmsr(0xC0010068) );
228 wrmsr(0xC0010068, msr );
231 //FIXME: CPTC2 and HTC_REG should get max per node, not per core ?
232 u8 maxpstate = setPStateMaxVal(dev);
234 u32 reg = pci_read_config32(dev, HTC_REG);
235 reg &= HTC_PS_LMT_MASK;
236 reg |= (maxpstate << PS_LIMIT_POS);
237 pci_write_config32(dev, HTC_REG,reg);
243 static int vidTo100uV(u8 vid)
244 {// returns voltage corresponding to vid in tenths of mV, i.e. hundreds of uV
245 // BKDG #31116 rev 3.48 2.4.1.6
250 voltage = (15500 - (125*vid));
255 static void setVSRamp(device_t dev) {
256 /* BKDG r31116 2010-04-22 2.4.1.7 step b F3xD8[VSRampTime]
257 * If this field accepts 8 values between 10 and 500 us why
258 * does page 324 say "BIOS should set this field to 001b."
260 * Shouldn't it depend on the voltage regulators, mainboard
264 dword = pci_read_config32(dev, 0xd8);
265 dword &= VSRAMP_MASK;
266 dword |= VSRAMP_VALUE;
267 pci_write_config32(dev, 0xd8, dword);
270 static void recalculateVsSlamTimeSettingOnCorePre(device_t dev)
273 u8 highVoltageVid, lowVoltageVid, bValue;
275 u16 vSlamTimes[7] = { 1000, 2000, 3000, 4000, 6000, 10000, 20000 }; /* Reg settings scaled by 100 */
279 /* This function calculates the VsSlamTime using the range of possible
280 * voltages instead of a hardcoded 200us.
281 * Note: his function is called only from prep_fid_change,
282 * and that from init_cpus.c finalize_node_setup()
283 * (after set AMD MSRs and init ht )
286 /* BKDG r31116 2010-04-22 2.4.1.7 step b F3xD8[VSSlamTime] */
287 /* Calculate Slam Time
288 * Vslam = (mobileCPU?0.2:0.4)us/mV * (Vp0 - (lowest out of Vpmin or Valt)) mV
289 * In our case, we will scale the values by 100 to avoid
293 /* Determine if this is a PVI or SVI system */
294 dtemp = pci_read_config32(dev, 0xA0);
296 if (dtemp & PVI_MODE)
301 /* Get P0's voltage */
302 /* MSRC001_00[68:64] are not programmed yet when called from
303 prep_fid_change, one might use F4x1[F0:E0] instead, but
304 theoretically MSRC001_00[68:64] are equal to them after
306 msr = rdmsr(0xC0010064);
307 highVoltageVid = (u8) ((msr.lo >> PS_CPU_VID_SHFT) & 0x7F);
308 if (!(msr.hi & 0x80000000)) {
309 printk(BIOS_ERR,"P-state info in MSRC001_0064 is invalid !!!\n");
310 highVoltageVid = (u8) ((pci_read_config32(dev, 0x1E0)
311 >> PS_CPU_VID_SHFT) & 0x7F);
314 /* If SVI, we only care about CPU VID.
315 * If PVI, determine the higher voltage b/t NB and CPU
318 bValue = (u8) ((msr.lo >> PS_NB_VID_SHFT) & 0x7F);
319 if (highVoltageVid > bValue)
320 highVoltageVid = bValue;
323 /* Get PSmax's index */
324 msr = rdmsr(0xC0010061);
325 bValue = (u8) ((msr.lo >> PS_MAX_VAL_SHFT) & BIT_MASK_3);
327 /* Get PSmax's VID */
328 msr = rdmsr(0xC0010064 + bValue);
329 lowVoltageVid = (u8) ((msr.lo >> PS_CPU_VID_SHFT) & 0x7F);
330 if (!(msr.hi & 0x80000000)) {
331 printk(BIOS_ERR,"P-state info in MSR%8x is invalid !!!\n",0xC0010064 + bValue);
332 lowVoltageVid = (u8) ((pci_read_config32(dev, 0x1E0+(bValue*4))
333 >> PS_CPU_VID_SHFT) & 0x7F);
336 /* If SVI, we only care about CPU VID.
337 * If PVI, determine the higher voltage b/t NB and CPU
341 bValue = (u8) ((msr.lo >> PS_NB_VID_SHFT) & 0x7F);
342 if (lowVoltageVid > bValue)
343 lowVoltageVid = bValue;
347 dtemp = pci_read_config32(dev, 0xDC);
348 bValue = (u8) (dtemp & BIT_MASK_7);
350 /* Use the VID with the lowest voltage (higher VID) */
351 if (lowVoltageVid < bValue)
352 lowVoltageVid = bValue;
354 u8 mobileFlag = get_platform_type() & AMD_PTYPE_MOB;
355 minimumSlamTime = (mobileFlag?2:4) * (vidTo100uV(highVoltageVid) - vidTo100uV(lowVoltageVid)); /* * 0.01 us */
358 /* Now round up to nearest register setting.
359 * Note that if we don't find a value, we
360 * will fall through to a value of 7
362 for (bValue = 0; bValue < 7; bValue++) {
363 if (minimumSlamTime <= vSlamTimes[bValue])
367 /* Apply the value */
368 dtemp = pci_read_config32(dev, 0xD8);
369 dtemp &= VSSLAM_MASK;
371 pci_write_config32(dev, 0xd8, dtemp);
374 static u32 nb_clk_did(int node, u32 cpuRev,u8 procPkg) {
377 if (AMD_CpuFindCapability(node, 0, &offset)) {
378 link0isGen3 = (AMD_checkLinkType(node, 0, offset) & HTPHY_LINKTYPE_HT3 );
380 /* FIXME: NB_CLKDID should be 101b for AMD_DA_C2 in package
381 S1g3 in link Gen3 mode, but I don't know how to tell
382 package S1g3 from S1g4 */
383 if ((cpuRev & AMD_DA_C2) && (procPkg & AMD_PKGTYPE_S1gX)
385 return 5 ; /* divide clk by 128*/
387 return 4 ; /* divide clk by 16 */
392 static u32 power_up_down(int node, u8 procPkg) {
394 /* from CPU rev guide #41322 rev 3.74 June 2010 Table 26 */
395 u8 singleLinkFlag = ((procPkg == AMD_PKGTYPE_AM3_2r2)
396 || (procPkg == AMD_PKGTYPE_S1gX)
397 || (procPkg == AMD_PKGTYPE_ASB2));
399 if (singleLinkFlag) {
401 * PowerStepUp=01000b - 50nS
402 * PowerStepDown=01000b - 50ns
404 dword |= PW_STP_UP50 | PW_STP_DN50;
406 u32 dispRefModeEn = (pci_read_config32(NODE_PCI(node,0),0x68) >> 24) & 1;
409 for(j=0 ; (j<4) && (!isocEn) ; j++ ) {
411 if (AMD_CpuFindCapability(node, j, &offset)) {
412 isocEn = (pci_read_config32(NODE_PCI(node,0),offset+4) >>12) & 1;
416 if (dispRefModeEn || isocEn) {
417 dword |= PW_STP_UP50 | PW_STP_DN50 ;
419 /* get number of cores for PowerStepUp & PowerStepDown in server
420 1 core - 400nS - 0000b
421 2 cores - 200nS - 0010b
422 3 cores - 133nS -> 100nS - 0011b
423 4 cores - 100nS - 0011b
425 switch (get_core_num_in_bsp(node)) {
427 dword |= PW_STP_UP400 | PW_STP_DN400;
431 dword |= PW_STP_UP200 | PW_STP_DN200;
434 dword |= PW_STP_UP100 | PW_STP_DN100;
437 dword |= PW_STP_UP100 | PW_STP_DN100;
445 static void config_clk_power_ctrl_reg0(int node, u32 cpuRev, u8 procPkg) {
446 device_t dev = NODE_PCI(node, 3);
448 /* Program fields in Clock Power/Control register0 (F3xD4) */
450 /* set F3xD4 Clock Power/Timing Control 0 Register
451 * NbClkDidApplyAll=1b
452 * NbClkDid=100b or 101b
453 * PowerStepUp= "platform dependent"
454 * PowerStepDown= "platform dependent"
456 * ClkRampHystCtl=HW default
457 * ClkRampHystSel=1111b
459 u32 dword= pci_read_config32(dev, 0xd4);
461 dword |= NB_CLKDID_ALL | LNK_PLL_LOCK | CLK_RAMP_HYST_SEL_VAL;
462 dword |= (nb_clk_did(node,cpuRev,procPkg) << NB_CLKDID_SHIFT);
464 dword |= power_up_down(node, procPkg);
466 pci_write_config32(dev, 0xd4, dword);
470 static void config_power_ctrl_misc_reg(device_t dev,u32 cpuRev, u8 procPkg) {
472 u32 dword = pci_read_config32(dev, 0xA0);
474 /* BKDG r31116 2010-04-22 2.4.1.7 step b F3xA0[VSSlamVidMod] */
475 /* PllLockTime and PsiVidEn set in ruleset in defaults.h */
476 if (dword & PVI_MODE) { /* PVI */
477 /* set slamVidMode to 0 for PVI */
478 dword &= VID_SLAM_OFF ;
480 /* set slamVidMode to 1 for SVI */
481 dword |= VID_SLAM_ON;
483 /* set the rest of A0 since we're at it... */
485 if (cpuRev & (AMD_DA_Cx | AMD_RB_C3 )) {
486 dword |= NB_PSTATE_FORCE_ON;
487 } // else should we clear it ?
490 if ((procPkg == AMD_PKGTYPE_G34) || (procPkg == AMD_PKGTYPE_C32) ) {
491 dword |= BP_INS_TRI_EN_ON ;
494 /* TODO: look into C1E state and F3xA0[IdleExitEn]*/
495 #if CONFIG_SVI_HIGH_FREQ
496 if (cpuRev & AMD_FAM10_C3) {
497 dword |= SVI_HIGH_FREQ_ON;
500 pci_write_config32(dev, 0xA0, dword);
503 static void config_nb_syn_ptr_adj(device_t dev, u32 cpuRev) {
504 /* Note the following settings are additional from the ported
505 * function setFidVidRegs()
507 /* adjust FIFO between nb and core clocks to max allowed
508 values (min latency) */
509 u32 nbPstate = pci_read_config32(dev,0x1f0) & NB_PSTATE_MASK;
511 if ((cpuRev & (AMD_DR_Bx|AMD_DA_Cx) )
512 || ( (cpuRev & AMD_RB_C3) && (nbPstate!=0))) {
518 u32 dword = pci_read_config32(dev, 0xDc);
519 dword &= ~ NB_SYN_PTR_ADJ_MASK;
520 dword |= nbSynPtrAdj << NB_SYN_PTR_ADJ_POS;
521 /* NbsynPtrAdj set to 5 or 6 per BKDG (needs reset) */
522 pci_write_config32(dev, 0xdc, dword);
525 static void config_acpi_pwr_state_ctrl_regs(device_t dev, u32 cpuRev, u8 procPkg) {
526 /* step 1, chapter 2.4.2.6 of AMD Fam 10 BKDG #31116 Rev 3.48 22.4.2010 */
529 if (cpuRev & (AMD_DR_Bx)) {
530 // will coreboot ever enable cache scrubbing ?
531 // if it does, will it be enough to check the current state
532 // or should we configure for what we'll set up later ?
533 dword = pci_read_config32(dev, 0x58);
534 u32 scrubbingCache = dword &
535 ( (0x1F << 16) // DCacheScrub
536 | (0x1F << 8) ); // L2Scrub
537 if (scrubbingCache) {
542 } else { // rev C or later
543 // same doubt as cache scrubbing: ok to check current state ?
544 dword = pci_read_config32(dev, 0xDC);
545 u32 cacheFlushOnHalt = dword & (7 << 16);
546 if (!cacheFlushOnHalt) {
550 dword = (c1 << 24) | (0xE641E6);
551 pci_write_config32(dev, 0x84, dword);
554 /* FIXME: BKDG Table 100 says if the link is at a Gen1
555 frequency and the chipset does not support a 10us minimum LDTSTOP
556 assertion time, then { If ASB2 && SVI then smaf001 = F6h else
557 smaf001=87h. } else ... I hardly know what it means or how to check
558 it from here, so I bluntly assume it is false and code here the else,
562 if (cpuRev & AMD_DR_Bx ) {
565 #if CONFIG_SVI_HIGH_FREQ
566 if (cpuRev & (AMD_RB_C3 | AMD_DA_C3)) {
571 u32 fidvidChange = 0;
572 if (((cpuRev & AMD_DA_Cx) && (procPkg & AMD_PKGTYPE_S1gX))
573 || (cpuRev & AMD_RB_C3) ) {
576 dword = (0xE6 << 24) | (fidvidChange << 16)
577 | (smaf001 << 8) | 0x81;
578 pci_write_config32(dev, 0x80, dword);
581 static void prep_fid_change(void)
588 /* This needs to be run before any Pstate changes are requested */
592 for (i = 0; i < nodes; i++) {
593 printk(BIOS_DEBUG, "Prep FID/VID Node:%02x \n", i);
594 dev = NODE_PCI(i, 3);
595 u32 cpuRev = mctGetLogicalCPUID(0xFF) ;
596 u8 procPkg = mctGetProcessorPackageType();
599 /* BKDG r31116 2010-04-22 2.4.1.7 step b F3xD8[VSSlamTime] */
600 /* Figure out the value for VsSlamTime and program it */
601 recalculateVsSlamTimeSettingOnCorePre(dev);
603 config_clk_power_ctrl_reg0(i,cpuRev,procPkg);
605 config_power_ctrl_misc_reg(dev,cpuRev,procPkg);
606 config_nb_syn_ptr_adj(dev,cpuRev);
608 config_acpi_pwr_state_ctrl_regs(dev,cpuRev,procPkg);
610 dword = pci_read_config32(dev, 0x80);
611 printk(BIOS_DEBUG, " F3x80: %08x \n", dword);
612 dword = pci_read_config32(dev, 0x84);
613 printk(BIOS_DEBUG, " F3x84: %08x \n", dword);
614 dword = pci_read_config32(dev, 0xD4);
615 printk(BIOS_DEBUG, " F3xD4: %08x \n", dword);
616 dword = pci_read_config32(dev, 0xD8);
617 printk(BIOS_DEBUG, " F3xD8: %08x \n", dword);
618 dword = pci_read_config32(dev, 0xDC);
619 printk(BIOS_DEBUG, " F3xDC: %08x \n", dword);
625 static void waitCurrentPstate(u32 target_pstate){
626 msr_t initial_msr = rdmsr(TSC_MSR);
627 msr_t pstate_msr = rdmsr(CUR_PSTATE_MSR);
631 /* paranoia ? I fear when we run fixPsNbVidBeforeWR we can enter a
632 * P1 that is a copy of P0, therefore has the same NB DID but the
633 * TSC will count twice per tick, so we have to wait for twice the
634 * count to achieve the desired timeout. But I'm likely to
635 * misunderstand this...
637 u32 corrected_timeout = ( (pstate_msr.lo==1)
638 && (!(rdmsr(0xC0010065).lo & NB_DID_M_ON)) ) ?
639 WAIT_PSTATE_TIMEOUT*2 : WAIT_PSTATE_TIMEOUT ;
642 timeout.lo = initial_msr.lo + corrected_timeout ;
643 timeout.hi = initial_msr.hi;
644 if ( (((u32)0xffffffff) - initial_msr.lo) < corrected_timeout ) {
648 // assuming TSC ticks at 1.25 ns per tick (800 MHz)
650 pstate_msr = rdmsr(CUR_PSTATE_MSR);
651 tsc_msr = rdmsr(TSC_MSR);
652 timedout = (tsc_msr.hi > timeout.hi)
653 || ((tsc_msr.hi == timeout.hi) && (tsc_msr.lo > timeout.lo ));
654 } while ( (pstate_msr.lo != target_pstate) && (! timedout) ) ;
656 if (pstate_msr.lo != target_pstate) {
657 msr_t limit_msr = rdmsr(0xc0010061);
658 printk(BIOS_ERR, "*** Time out waiting for P-state %01x. Current P-state %01x P-state current limit MSRC001_0061=%02x\n", target_pstate, pstate_msr.lo, limit_msr.lo);
660 do { // should we just go on instead ?
661 pstate_msr = rdmsr(CUR_PSTATE_MSR);
662 } while ( pstate_msr.lo != target_pstate ) ;
666 static void set_pstate(u32 nonBoostedPState) {
669 // Transition P0 for calling core.
670 msr = rdmsr(0xC0010062);
672 msr.lo = nonBoostedPState;
673 wrmsr(0xC0010062, msr);
675 /* Wait for P0 to set. */
676 waitCurrentPstate(nonBoostedPState);
682 static void UpdateSinglePlaneNbVid(void)
688 /* copy higher voltage (lower VID) of NBVID & CPUVID to both */
689 for (i = 0; i < 5; i++) {
690 msr = rdmsr(PS_REG_BASE + i);
691 nbVid = (msr.lo & PS_CPU_VID_M_ON) >> PS_CPU_VID_SHFT;
692 cpuVid = (msr.lo & PS_NB_VID_M_ON) >> PS_NB_VID_SHFT;
694 if (nbVid != cpuVid) {
698 msr.lo = msr.lo & PS_BOTH_VID_OFF;
699 msr.lo = msr.lo | (u32) ((nbVid) << PS_NB_VID_SHFT);
700 msr.lo = msr.lo | (u32) ((nbVid) << PS_CPU_VID_SHFT);
701 wrmsr(PS_REG_BASE + i, msr);
706 static void fixPsNbVidBeforeWR(u32 newNbVid, u32 coreid, u32 dev, u8 pviMode)
711 /* This function sets NbVid before the warm reset.
712 * Get StartupPstate from MSRC001_0071.
713 * Read Pstate register pointed by [StartupPstate].
714 * and copy its content to P0 and P1 registers.
715 * Copy newNbVid to P0[NbVid].
716 * transition to P1 on all cores,
717 * then transition to P0 on core 0.
718 * Wait for MSRC001_0063[CurPstate] = 000b on core 0.
719 * see BKDG rev 3.48 2.4.2.9.1 BIOS NB COF and VID Configuration
720 * for SVI and Single-Plane PVI Systems
723 msr = rdmsr(0xc0010071);
724 startup_pstate = (msr.hi >> (32 - 32)) & 0x07;
726 /* Copy startup pstate to P1 and P0 MSRs. Set the maxvid for
727 * this node in P0. Then transition to P1 for corex and P0
728 * for core0. These setting will be cleared by the warm reset
730 msr = rdmsr(0xC0010064 + startup_pstate);
731 wrmsr(0xC0010065, msr);
732 wrmsr(0xC0010064, msr);
734 /* missing step 2 from BDKG , F3xDC[PstateMaxVal] =
735 * max(1,F3xDC[PstateMaxVal] ) because it would take
736 * synchronization between cores and we don't think
737 * PstatMaxVal is going to be 0 on cold reset anyway ?
739 if ( ! (pci_read_config32(dev, 0xDC) & (~ PS_MAX_VAL_MASK)) ) {
740 printk(BIOS_ERR,"F3xDC[PstateMaxVal] is zero. Northbridge voltage setting will fail. fixPsNbVidBeforeWR in fidvid.c needs fixing. See AMD # 31116 rev 3.48 BKDG 2.4.2.9.1 \n");
743 msr.lo &= ~0xFE000000; // clear nbvid
744 msr.lo |= (newNbVid << 25);
745 wrmsr(0xC0010064, msr);
747 if (pviMode) { /* single plane*/
748 UpdateSinglePlaneNbVid();
751 // Transition to P1 for all APs and P0 for core0.
758 /* missing step 7 (restore PstateMax to 0 if needed) because
764 static u32 needs_NB_COF_VID_update(void)
766 u8 nb_cof_vid_update;
770 /* If any node has nb_cof_vid_update set all nodes need an update. */
772 nb_cof_vid_update = 0;
773 for (i = 0; i < nodes; i++) {
774 u32 cpuRev = mctGetLogicalCPUID(i) ;
775 u32 nbCofVidUpdateDefined = (cpuRev & (AMD_FAM10_LT_D));
776 if (nbCofVidUpdateDefined
777 && (pci_read_config32(NODE_PCI(i, 3), 0x1FC)
778 & NB_COF_VID_UPDATE_MASK)) {
779 nb_cof_vid_update = 1;
783 return nb_cof_vid_update;
786 static u32 init_fidvid_core(u32 nodeid, u32 coreid)
791 u8 nb_cof_vid_update = needs_NB_COF_VID_update();
795 /* Steps 1-6 of BIOS NB COF and VID Configuration
796 * for SVI and Single-Plane PVI Systems. BKDG 2.4.2.9 #31116 rev 3.48
799 dev = NODE_PCI(nodeid, 3);
800 pvimode = pci_read_config32(dev, PW_CTL_MISC) & PVI_MODE;
801 reg1fc = pci_read_config32(dev, 0x1FC);
803 if (nb_cof_vid_update) {
804 vid_max = (reg1fc & SINGLE_PLANE_NB_VID_MASK ) >> SINGLE_PLANE_NB_VID_SHIFT ;
805 fid_max = (reg1fc & SINGLE_PLANE_NB_FID_MASK ) >> SINGLE_PLANE_NB_FID_SHIFT ;
807 if (!pvimode) { /* SVI, dual power plane */
808 vid_max = vid_max - ((reg1fc & DUAL_PLANE_NB_VID_OFF_MASK ) >> DUAL_PLANE_NB_VID_SHIFT );
809 fid_max = fid_max + ((reg1fc & DUAL_PLANE_NB_FID_OFF_MASK ) >> DUAL_PLANE_NB_FID_SHIFT );
811 /* write newNbVid to P-state Reg's NbVid always if NbVidUpdatedAll=1 */
812 fixPsNbVidBeforeWR(vid_max, coreid,dev,pvimode);
814 /* fid setup is handled by the BSP at the end. */
816 } else { /* ! nb_cof_vid_update */
819 UpdateSinglePlaneNbVid();
822 return ((nb_cof_vid_update << 16) | (fid_max << 8));
826 static void init_fidvid_ap(u32 apicid, u32 nodeid, u32 coreid)
830 printk(BIOS_DEBUG, "FIDVID on AP: %02x\n", apicid);
832 send = init_fidvid_core(nodeid,coreid);
833 send |= (apicid << 24); // ap apicid
835 // Send signal to BSP about this AP max fid
836 // This also indicates this AP is ready for warm reset (if required).
837 lapic_write(LAPIC_MSG_REG, send | F10_APSTATE_RESET);
840 static u32 calc_common_fid(u32 fid_packed, u32 fid_packed_new)
845 fidmax = (fid_packed >> 8) & 0xFF;
847 fidmax_new = (fid_packed_new >> 8) & 0xFF;
849 if (fidmax > fidmax_new) {
853 fid_packed &= 0xFF << 16;
854 fid_packed |= (fidmax << 8);
855 fid_packed |= fid_packed_new & (0xFF << 16); // set nb_cof_vid_update
860 static void init_fidvid_bsp_stage1(u32 ap_apicid, void *gp)
865 struct fidvid_st *fvp = gp;
868 print_debug_fv("Wait for AP stage 1: ap_apicid = ", ap_apicid);
872 if (lapic_remote_read(ap_apicid, LAPIC_MSG_REG, &readback) != 0)
874 if ((readback & 0x3f) == 1) {
876 break; /* target ap is in stage 1 */
881 printk(BIOS_DEBUG, "%s: timed out reading from ap %02x\n",
882 __func__, ap_apicid);
886 print_debug_fv("\treadback = ", readback);
888 fvp->common_fid = calc_common_fid(fvp->common_fid, readback);
890 print_debug_fv("\tcommon_fid(packed) = ", fvp->common_fid);
894 static void fixPsNbVidAfterWR(u32 newNbVid, u8 NbVidUpdatedAll,u8 pviMode)
900 /* BKDG 2.4.2.9.1 11-12
901 * This function copies newNbVid to NbVid bits in P-state
902 * Registers[4:0] if its NbDid bit=0, and IddValue!=0 in case of
903 * NbVidUpdatedAll =0 or copies newNbVid to NbVid bits in
904 * P-state Registers[4:0] if its IddValue!=0 in case of
905 * NbVidUpdatedAll=1. Then transition to StartPstate.
908 /* write newNbVid to P-state Reg's NbVid if its NbDid=0 */
909 for (i = 0; i < 5; i++) {
910 msr = rdmsr(0xC0010064 + i);
911 /* NbDid (bit 22 of P-state Reg) == 0 or NbVidUpdatedAll = 1 */
912 if ( (msr.hi & PS_IDD_VALUE_MASK)
913 && (msr.hi & PS_EN_MASK)
914 &&(((msr.lo & PS_NB_DID_MASK) == 0) || NbVidUpdatedAll)) {
915 msr.lo &= PS_NB_VID_M_OFF;
916 msr.lo |= (newNbVid & 0x7F) << PS_NB_VID_SHFT;
917 wrmsr(0xC0010064 + i, msr);
921 /* Not documented. Would overwrite Nb_Vids just copied
922 * should we just update cpu_vid or nothing at all ?
924 if (pviMode) { //single plane
925 UpdateSinglePlaneNbVid();
927 /* For each core in the system, transition all cores to StartupPstate */
928 msr = rdmsr(0xC0010071);
929 StartupPstate = msr.hi & 0x07;
931 /* Set and wait for StartupPstate to set. */
932 set_pstate(StartupPstate);
936 static void finalPstateChange(void)
938 /* Enble P0 on all cores for best performance.
939 * Linux can slow them down later if need be.
940 * It is safe since they will be in C1 halt
941 * most of the time anyway.
946 static void init_fidvid_stage2(u32 apicid, u32 nodeid)
953 u8 nb_cof_vid_update = needs_NB_COF_VID_update();
957 /* After warm reset finish the fid/vid setup for all cores. */
959 /* If any node has nb_cof_vid_update set all nodes need an update. */
961 dev = NODE_PCI(nodeid, 3);
962 pvimode = (pci_read_config32(dev, 0xA0) >> 8) & 1;
963 reg1fc = pci_read_config32(dev, 0x1FC);
964 nbvid = (reg1fc >> 7) & 0x7F;
965 NbVidUpdateAll = (reg1fc >> 1) & 1;
967 if (nb_cof_vid_update) {
968 if (!pvimode) { /* SVI */
969 nbvid = nbvid - ((reg1fc >> 17) & 0x1F);
971 /* write newNbVid to P-state Reg's NbVid if its NbDid=0 */
972 fixPsNbVidAfterWR(nbvid, NbVidUpdateAll,pvimode);
973 } else { /* !nb_cof_vid_update */
975 UpdateSinglePlaneNbVid();
977 dtemp = pci_read_config32(dev, 0xA0);
978 dtemp &= PLLLOCK_OFF;
979 dtemp |= PLLLOCK_DFT_L;
980 pci_write_config32(dev, 0xA0, dtemp);
983 applyBoostFIDOffset(dev);
984 enableNbPState1(dev);
988 /* Set TSC to tick at the P0 ndfid rate */
995 #if CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST
996 struct ap_apicid_st {
998 // it could use 256 bytes for 64 node quad core system
999 u8 apicid[NODE_NUMS * 4];
1002 static void store_ap_apicid(unsigned ap_apicid, void *gp)
1004 struct ap_apicid_st *p = gp;
1006 p->apicid[p->num++] = ap_apicid;
1012 static int init_fidvid_bsp(u32 bsp_apicid, u32 nodes)
1014 #if CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST
1015 struct ap_apicid_st ap_apicidx;
1018 struct fidvid_st fv;
1020 printk(BIOS_DEBUG, "FIDVID on BSP, APIC_id: %02x\n", bsp_apicid);
1022 /* Steps 1-6 of BIOS NB COF and VID Configuration
1023 * for SVI and Single-Plane PVI Systems.
1026 fv.common_fid = init_fidvid_core(0,0);
1028 print_debug_fv("BSP fid = ", fv.common_fid);
1030 #if CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST && !CONFIG_SET_FIDVID_CORE0_ONLY
1031 /* For all APs (We know the APIC ID of all APs even when the APIC ID
1032 is lifted) remote read from AP LAPIC_MSG_REG about max fid.
1033 Then calculate the common max fid that can be used for all
1037 for_each_ap(bsp_apicid, CONFIG_SET_FIDVID_CORE_RANGE, store_ap_apicid, &ap_apicidx);
1039 for (i = 0; i < ap_apicidx.num; i++) {
1040 init_fidvid_bsp_stage1(ap_apicidx.apicid[i], &fv);
1043 for_each_ap(bsp_apicid, CONFIG_SET_FIDVID_CORE0_ONLY, init_fidvid_bsp_stage1, &fv);
1046 print_debug_fv("common_fid = ", fv.common_fid);
1048 if (fv.common_fid & (1 << 16)) { /* check nb_cof_vid_update */
1050 // Enable the common fid and other settings.
1051 enable_fid_change((fv.common_fid >> 8) & 0x1F);
1053 // nbfid change need warm reset, so reset at first
1057 return 0; // No FID/VID changes. Don't reset