2 * This file is part of the coreboot project.
4 * Copyright (C) 2010 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #include <console/console.h>
24 #include <device/device.h>
25 #include <device/pci.h>
26 #include <device/pci_ids.h>
27 #include <device/pci_ops.h>
28 #include <cpu/x86/msr.h>
29 #include <cpu/amd/mtrr.h>
30 #include <boot/coreboot_tables.h>
35 static u32 nb_read_index(device_t dev, u32 index_reg, u32 index)
37 pci_write_config32(dev, index_reg, index);
38 return pci_read_config32(dev, index_reg + 0x4);
41 static void nb_write_index(device_t dev, u32 index_reg, u32 index, u32 data)
43 pci_write_config32(dev, index_reg, index);
44 pci_write_config32(dev, index_reg + 0x4, data);
47 /* extension registers */
48 u32 pci_ext_read_config32(device_t nb_dev, device_t dev, u32 reg)
50 /*get BAR3 base address for nbcfg0x1c */
51 u32 addr = pci_read_config32(nb_dev, 0x1c) & ~0xF;
52 printk(BIOS_DEBUG, "addr=%x,bus=%x,devfn=%x\n", addr, dev->bus->secondary,
54 addr |= dev->bus->secondary << 20 | /* bus num */
55 dev->path.pci.devfn << 12 | reg;
56 return *((u32 *) addr);
59 void pci_ext_write_config32(device_t nb_dev, device_t dev, u32 reg_pos, u32 mask, u32 val)
63 /*get BAR3 base address for nbcfg0x1c */
64 u32 addr = pci_read_config32(nb_dev, 0x1c) & ~0xF;
65 /*printk(BIOS_DEBUG, "write: addr=%x,bus=%x,devfn=%x\n", addr, dev->bus->secondary,
66 dev->path.pci.devfn);*/
67 addr |= dev->bus->secondary << 20 | /* bus num */
68 dev->path.pci.devfn << 12 | reg_pos;
70 reg = reg_old = *((u32 *) addr);
74 *((u32 *) addr) = reg;
78 u32 nbmisc_read_index(device_t nb_dev, u32 index)
80 return nb_read_index((nb_dev), NBMISC_INDEX, (index));
83 void nbmisc_write_index(device_t nb_dev, u32 index, u32 data)
85 nb_write_index((nb_dev), NBMISC_INDEX, ((index) | 0x80), (data));
88 u32 nbpcie_p_read_index(device_t dev, u32 index)
90 return nb_read_index((dev), NBPCIE_INDEX, (index));
93 void nbpcie_p_write_index(device_t dev, u32 index, u32 data)
95 nb_write_index((dev), NBPCIE_INDEX, (index), (data));
98 u32 nbpcie_ind_read_index(device_t nb_dev, u32 index)
100 return nb_read_index((nb_dev), NBPCIE_INDEX, (index));
103 void nbpcie_ind_write_index(device_t nb_dev, u32 index, u32 data)
105 nb_write_index((nb_dev), NBPCIE_INDEX, (index), (data));
108 u32 htiu_read_index(device_t nb_dev, u32 index)
110 return nb_read_index((nb_dev), NBHTIU_INDEX, (index));
113 void htiu_write_index(device_t nb_dev, u32 index, u32 data)
115 nb_write_index((nb_dev), NBHTIU_INDEX, ((index) | 0x100), (data));
118 u32 nbmc_read_index(device_t nb_dev, u32 index)
120 return nb_read_index((nb_dev), NBMC_INDEX, (index));
123 void nbmc_write_index(device_t nb_dev, u32 index, u32 data)
125 nb_write_index((nb_dev), NBMC_INDEX, ((index) | 1 << 9), (data));
128 void set_nbcfg_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, u32 val)
131 reg = reg_old = pci_read_config32(nb_dev, reg_pos);
134 if (reg != reg_old) {
135 pci_write_config32(nb_dev, reg_pos, reg);
139 void set_nbcfg_enable_bits_8(device_t nb_dev, u32 reg_pos, u8 mask, u8 val)
142 reg = reg_old = pci_read_config8(nb_dev, reg_pos);
145 if (reg != reg_old) {
146 pci_write_config8(nb_dev, reg_pos, reg);
150 void set_nbmc_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, u32 val)
153 reg = reg_old = nbmc_read_index(nb_dev, reg_pos);
156 if (reg != reg_old) {
157 nbmc_write_index(nb_dev, reg_pos, reg);
161 void set_htiu_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, u32 val)
164 reg = reg_old = htiu_read_index(nb_dev, reg_pos);
167 if (reg != reg_old) {
168 htiu_write_index(nb_dev, reg_pos, reg);
172 void set_nbmisc_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, u32 val)
175 reg = reg_old = nbmisc_read_index(nb_dev, reg_pos);
178 if (reg != reg_old) {
179 nbmisc_write_index(nb_dev, reg_pos, reg);
183 void set_pcie_enable_bits(device_t dev, u32 reg_pos, u32 mask, u32 val)
186 reg = reg_old = nb_read_index(dev, NBPCIE_INDEX, reg_pos);
189 if (reg != reg_old) {
190 nb_write_index(dev, NBPCIE_INDEX, reg_pos, reg);
194 /***********************************************************
195 * To access bar3 we need to program PCI MMIO 7 in K8.
197 * 1: enable/enter k8 temp mmio base
199 ***********************************************************/
200 void ProgK8TempMmioBase(u8 in_out, u32 pcie_base_add, u32 mmio_base_add)
202 /* K8 Function1 is address map */
203 device_t k8_f1 = dev_find_slot(0, PCI_DEVFN(0x18, 1));
204 device_t k8_f0 = dev_find_slot(0, PCI_DEVFN(0x18, 0));
209 /* Get SBLink value (HyperTransport I/O Hub Link ID). */
210 dword = pci_read_config32(k8_f0, 0x64);
211 sblk = (dword >> 8) & 0x3;
213 /* Fill MMIO limit/base pair. */
214 pci_write_config32(k8_f1, 0xbc,
215 (((pcie_base_add + 0x10000000 -
216 1) >> 8) & 0xffffff00) | 0x80 | (sblk << 4));
217 pci_write_config32(k8_f1, 0xb8, (pcie_base_add >> 8) | 0x3);
218 pci_write_config32(k8_f1, 0xb4,
219 (((mmio_base_add + 0x10000000 -
220 1) >> 8) & 0xffffff00) | (sblk << 4));
221 pci_write_config32(k8_f1, 0xb0, (mmio_base_add >> 8) | 0x3);
223 pci_write_config32(k8_f1, 0xb8, 0);
224 pci_write_config32(k8_f1, 0xbc, 0);
225 pci_write_config32(k8_f1, 0xb0, 0);
226 pci_write_config32(k8_f1, 0xb4, 0);
230 void PcieReleasePortTraining(device_t nb_dev, device_t dev, u32 port)
233 case 2: /* GFX, bit4-5 */
235 set_nbmisc_enable_bits(nb_dev, PCIE_LINK_CFG,
236 1 << (port + 2), 0 << (port + 2));
238 case 4: /* GPPSB, bit20-24 */
242 set_nbmisc_enable_bits(nb_dev, PCIE_LINK_CFG,
243 1 << (port + 17), 0 << (port + 17));
245 case 9: /* GPP, bit 4,5 of miscind 0x2D */
247 set_nbmisc_enable_bits(nb_dev, 0x2D,
248 1 << (port - 5), 0 << (port - 5));
253 /********************************************************************************************************
255 * 0: no device is present.
256 * 1: device is present and is trained.
257 ********************************************************************************************************/
258 u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port)
261 u32 lc_state, reg, current_link_width, lane_mask;
262 int8_t current, res = 0;
264 void set_pcie_dereset(void);
265 void set_pcie_reset(void);
269 gfx_gpp_sb_sel = PCIE_CORE_INDEX_GFX;
272 gfx_gpp_sb_sel = PCIE_CORE_INDEX_GPPSB;
275 gfx_gpp_sb_sel = PCIE_CORE_INDEX_GPP;
285 lc_state = nbpcie_p_read_index(dev, 0xa5); /* lc_state */
286 printk(BIOS_DEBUG, "PcieLinkTraining port=%x:lc current state=%x\n",
288 current = lc_state & 0x3f; /* get LC_CURRENT_STATE, bit0-5 */
291 case 0x00: /* 0x00-0x04 means no device is present */
300 /* read back current link width [6:4]. */
301 current_link_width = (nbpcie_p_read_index(dev, 0xA2) >> 4) & 0x7;
302 /* 4 means 7:4 and 15:12
303 * 3 means 7:2 and 15:10
304 * 2 means 7:1 and 15:9
305 * egnoring the reversal case
307 lane_mask = (0xFF << (current_link_width - 2) * 2) & 0xFF;
308 reg = nbpcie_ind_read_index(nb_dev, 0x65 | gfx_gpp_sb_sel);
309 reg |= lane_mask << 8 | lane_mask;
310 reg = 0xE0E0; /* TODO: See the comments in rs780_pcie.c, at about line 145. */
311 nbpcie_ind_write_index(nb_dev, 0x65 | gfx_gpp_sb_sel, reg);
312 printk(BIOS_DEBUG, "link_width=%x, lane_mask=%x",
313 current_link_width, lane_mask);
318 case 0x07: /* device is in compliance state (training sequence is done). Move to train the next device */
324 pci_ext_read_config32(nb_dev, dev,
325 PCIE_VC0_RESOURCE_STATUS);
326 printk(BIOS_DEBUG, "PcieTrainPort reg=0x%x\n", reg);
328 if (reg & VC_NEGOTIATION_PENDING) { /* bit1=1 means the link needs to be re-trained. */
329 /* set bit8=1, bit0-2=bit4-6 */
332 nbpcie_p_read_index(dev,
334 tmp = (reg >> 4) && 0x3; /* get bit4-6 */
335 reg &= 0xfff8; /* clear bit0-2 */
336 reg += tmp; /* merge */
338 count++; /* CIM said "keep in loop"? */
344 default: /* reset pcie */
346 count = 0; /* break loop */
354 * Compliant with CIM_33's ATINB_SetToms.
355 * Set Top Of Memory below and above 4G.
357 void rs780_set_tom(device_t nb_dev)
359 extern uint64_t uma_memory_base;
362 pci_write_config32(nb_dev, 0x90, uma_memory_base);
363 //nbmc_write_index(nb_dev, 0x1e, uma_memory_base);
366 // extract single bit
367 u32 extractbit(u32 data, int bit_number)
369 return (data >> bit_number) & 1;
373 u32 extractbits(u32 source, int lsb, int msb)
375 int field_width = msb - lsb + 1;
376 u32 mask = 0xFFFFFFFF >> (32 - field_width);
377 return (source >> lsb) & mask;
380 // return AMD cpuid family
381 int cpuidFamily(void)
383 u32 baseFamily, extendedFamily, fms;
386 baseFamily = extractbits (fms, 8, 11);
387 extendedFamily = extractbits (fms, 20, 27);
388 return baseFamily + extendedFamily;
392 // return non-zero for AMD family 0Fh processor found
393 int is_family0Fh(void)
395 return cpuidFamily() == 0x0F;
399 // return non-zero for AMD family 10h processor found
400 int is_family10h(void)
402 return cpuidFamily() == 0x10;