2 * This file is part of the coreboot project.
4 * Copyright (C) 2011 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 /*----------------------------------------------------------------------------------------
21 * M O D U L E S U S E D
22 *----------------------------------------------------------------------------------------
30 #define FILECODE UNASSIGNED_FILE_FILECODE
32 /*----------------------------------------------------------------------------------------
33 * D E F I N I T I O N S A N D M A C R O S
34 *----------------------------------------------------------------------------------------
37 #define SB_GPIO_REG01 1
41 #define SB_GPIO_REG07 7
45 #define SB_GPIO_REG25 25
49 #define SB_GPIO_REG26 26
53 #define SB_GPIO_REG27 27
56 /*----------------------------------------------------------------------------------------
57 * T Y P E D E F S A N D S T R U C T U R E S
58 *----------------------------------------------------------------------------------------
61 /*----------------------------------------------------------------------------------------
62 * P R O T O T Y P E S O F L O C A L F U N C T I O N S
63 *----------------------------------------------------------------------------------------
65 void gpioEarlyInit (void);
67 /*----------------------------------------------------------------------------------------
68 * E X P O R T E D F U N C T I O N S
69 *----------------------------------------------------------------------------------------
72 /*---------------------------------------------------------------------------------------
73 * L O C A L F U N C T I O N S
74 *---------------------------------------------------------------------------------------
91 u32 IoMuxMmioAddr = 0;
96 // Enable HUDSON MMIO Base (AcpiMmioAddr)
97 ReadPMIO (SB_PMIOA_REG24, AccWidthUint8, &Data8);
99 WritePMIO (SB_PMIOA_REG24, AccWidthUint8, &Data8);
100 // Get HUDSON MMIO Base (AcpiMmioAddr)
101 ReadPMIO (SB_PMIOA_REG24 + 3, AccWidthUint8, &Data8);
103 ReadPMIO (SB_PMIOA_REG24 + 2, AccWidthUint8, &Data8);
105 AcpiMmioAddr = (u32)Data16 << 16;
106 GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;
107 IoMuxMmioAddr = AcpiMmioAddr + IOMUX_BASE;
108 MiscMmioAddr = AcpiMmioAddr + MISC_BASE;
109 Data8 = Mmio8_G (MiscMmioAddr, SB_MISC_REG80);
110 if ((Data8 & BIT4) == 0) {
111 BoardType = 0; // external clock board
113 Data8 = Mmio8_G (GpioMmioAddr, GPIO_30);
114 StripInfo = (Data8 & BIT7) >> 7;
115 Data8 = Mmio8_G (GpioMmioAddr, GPIO_31);
116 StripInfo |= (Data8 & BIT7) >> 6;
117 if (StripInfo < boardRevC) { // for old board. Rev B
118 Mmio8_And_Or (IoMuxMmioAddr, GPIO_111, 0x00, 3); // function 3
119 Mmio8_And_Or (IoMuxMmioAddr, GPIO_113, 0x00, 0); // function 0
121 for (Index = 0; Index < MAX_GPIO_NO; Index++) {
122 if (!(((Index >= GPIO_RSVD_ZONE0_S) && (Index <= GPIO_RSVD_ZONE0_E)) || ((Index >= GPIO_RSVD_ZONE1_S) && (Index <= GPIO_RSVD_ZONE1_E)))) {
123 if ((StripInfo >= boardRevC) || ((Index != GPIO_111) && (Index != GPIO_113))) {
124 // Configure multi-funtion
125 Mmio8_And_Or (IoMuxMmioAddr, Index, 0x00, (gpio_table[Index].select & ~NonGpio));
128 if(!((gpio_table[Index].NonGpioGevent & NonGpio))) {
129 Mmio8_And_Or (GpioMmioAddr, Index, 0xDF, gpio_table[Index].type);
130 Mmio8_And_Or (GpioMmioAddr, Index, 0xA3, gpio_table[Index].value);
132 if (Index == GPIO_65) {
133 if ( BoardType == 0 ) {
134 Mmio8_And_Or (IoMuxMmioAddr, GPIO_65, 0x00, 3); // function 3
139 if ((Index >= GEVENT_00) && (Index <= GEVENT_23) && ((gevent_table[Index - GEVENT_00].EventEnable))) {
140 SmiMmioAddr = AcpiMmioAddr + SMI_BASE;
142 andMask32 = ~(1 << (Index - GEVENT_00));
144 //EventEnable: 0-Disable, 1-Enable
145 Mmio32_And_Or (SmiMmioAddr, SMIREG_EVENT_ENABLE, andMask32, (gevent_table[Index - GEVENT_00].EventEnable << (Index - GEVENT_00)));
147 //SciTrig: 0-Falling Edge, 1-Rising Edge
148 Mmio32_And_Or (SmiMmioAddr, SMIREG_SCITRIG, andMask32, (gevent_table[Index - GEVENT_00].SciTrig << (Index - GEVENT_00)));
150 //SciLevl: 0-Edge trigger, 1-Level Trigger
151 Mmio32_And_Or (SmiMmioAddr, SMIREG_SCILEVEL, andMask32, (gevent_table[Index - GEVENT_00].SciLevl << (Index - GEVENT_00)));
153 //SmiSciEn: 0-Not send SMI, 1-Send SMI
154 Mmio32_And_Or (SmiMmioAddr, SMIREG_SMISCIEN, andMask32, (gevent_table[Index - GEVENT_00].SmiSciEn << (Index - GEVENT_00)));
156 //SciS0En: 0-Disable, 1-Enable
157 Mmio32_And_Or (SmiMmioAddr, SMIREG_SCIS0EN, andMask32, (gevent_table[Index - GEVENT_00].SciS0En << (Index - GEVENT_00)));
159 //SciMap: 00000b ~ 11111b
160 RegIndex8=(u8)((Index - GEVENT_00) >> 2);
161 Data8=(u8)(((Index - GEVENT_00) & 0x3) * 8);
162 Mmio32_And_Or (SmiMmioAddr, SMIREG_SCIMAP0+RegIndex8, ~(GEVENT_SCIMASK << Data8), (gevent_table[Index - GEVENT_00].SciMap << Data8));
164 //SmiTrig: 0-Active Low, 1-Active High
165 Mmio32_And_Or (SmiMmioAddr, SMIREG_SMITRIG, ~(gevent_table[Index - GEVENT_00].SmiTrig << (Index - GEVENT_00)), (gevent_table[Index - GEVENT_00].SmiTrig << (Index - GEVENT_00)));
167 //SmiControl: 0-Disable, 1-SMI, 2-NMI, 3-IRQ13
168 RegIndex8=(u8)((Index - GEVENT_00) >> 4);
169 Data8=(u8)(((Index - GEVENT_00) & 0xF) * 2);
170 Mmio32_And_Or (SmiMmioAddr, SMIREG_SMICONTROL0+RegIndex8, ~(SMICONTROL_MASK << Data8), (gevent_table[Index - GEVENT_00].SmiControl << Data8));
176 // GPIO9: Input for MXM_PRESENT2#
177 // GPIO10: Input for MXM_PRESENT1#
178 // GPIO28: Input for MXM_PWRGD
179 // GPIO35: Output for MXM Reset
180 // GPIO45: Output for MXM Power Enable, active HIGH
181 // GPIO55: Output for MXM_PWR_EN, 1 - Enable, 0 - Disable
182 // GPIO32: Output for PCIE_SW, 1 - MXM, 0 - LASSO
184 // set INTE#/GPIO32 as GPO for PCIE_SW
185 RWMEM (IoMuxMmioAddr + SB_GPIO_REG32, AccWidthUint8, 00, 0x1); // GPIO
186 RWMEM (GpioMmioAddr + SB_GPIO_REG32, AccWidthUint8, 0x03, 0); // GPO
187 RWMEM (GpioMmioAddr + SB_GPIO_REG32, AccWidthUint8, 0x23, BIT3+BIT6);
189 // set SATA_IS4#/FANOUT3/GPIO55 as GPO for MXM_PWR_EN
190 RWMEM (IoMuxMmioAddr + SB_GPIO_REG55, AccWidthUint8, 00, 0x2); // GPIO
191 RWMEM (GpioMmioAddr + SB_GPIO_REG55, AccWidthUint8, 0x03, 0); // GPO
193 // set AD9/GPIO9 as GPI for MXM_PRESENT2#
194 RWMEM (IoMuxMmioAddr + SB_GPIO_REG09, AccWidthUint8, 00, 0x1); // GPIO
195 RWMEM (GpioMmioAddr + SB_GPIO_REG09, AccWidthUint8, 0x03, BIT5); // GPI
197 // set AD10/GPIO10 as GPI for MXM_PRESENT1#
198 RWMEM (IoMuxMmioAddr + SB_GPIO_REG10, AccWidthUint8, 00, 0x1); // GPIO
199 RWMEM (GpioMmioAddr + SB_GPIO_REG10, AccWidthUint8, 0x03, BIT5); // GPI
201 // set GNT1#/GPIO44 as GPO for MXM Reset
202 RWMEM (IoMuxMmioAddr + SB_GPIO_REG44, AccWidthUint8, 00, 0x1); // GPIO
203 RWMEM (GpioMmioAddr + SB_GPIO_REG44, AccWidthUint8, 0x03, 0); // GPO
205 // set GNT2#/SD_LED/GPO45 as GPO for MXM Power Enable
206 RWMEM (IoMuxMmioAddr + SB_GPIO_REG45, AccWidthUint8, 00, 0x2); // GPIO
207 RWMEM (GpioMmioAddr + SB_GPIO_REG45, AccWidthUint8, 0x03, 0); // GPO
209 // set AD28/GPIO28 as GPI for MXM_PWRGD
210 RWMEM (IoMuxMmioAddr + SB_GPIO_REG28, AccWidthUint8, 00, 0x1); // GPIO
211 RWMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, 0x03, BIT5); // GPI
213 // set BIT3=1 (PULLUP disable), BIT4=0 (PULLDOWN Disable), BIT6=0 (Output LOW)
214 RWMEM (GpioMmioAddr + SB_GPIO_REG55, AccWidthUint8, 0x23, BIT3);
215 RWMEM (GpioMmioAddr + SB_GPIO_REG09, AccWidthUint8, 0x23, BIT3);
216 RWMEM (GpioMmioAddr + SB_GPIO_REG10, AccWidthUint8, 0x23, BIT3);
217 RWMEM (GpioMmioAddr + SB_GPIO_REG44, AccWidthUint8, 0x23, BIT3);
218 RWMEM (GpioMmioAddr + SB_GPIO_REG45, AccWidthUint8, 0x23, BIT3);
219 RWMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, 0x23, BIT3);
222 // [GPIO] STRP_DATA: 1->RS880M VCC_NB 1.0V. 0->RS880M VCC_NB 1.1V (Default).
224 //Fusion_Llano BLWriteNBMISC_Dword (ATI_MISC_REG42, (BLReadNBMISC_Dword (ATI_MISC_REG42) | BIT20));
225 //Fusion_Llano BLWriteNBMISC_Dword (ATI_MISC_REG40, (BLReadNBMISC_Dword (ATI_MISC_REG40) & (~BIT20)));
227 // check if there any GFX card
229 // Value32 = MmPci32 (0, SB_ISA_BUS, SB_ISA_DEV, SB_ISA_FUNC, R_SB_ISA_GPIO_CONTROL);
230 // Data8 = Mmio8 (GpioMmioAddr, SB_GPIO_REG09);
231 ReadMEM (GpioMmioAddr + SB_GPIO_REG09, AccWidthUint8, &Data8);
234 //Data8 = Mmio8 (GpioMmioAddr, SB_GPIO_REG10);
235 ReadMEM (GpioMmioAddr + SB_GPIO_REG10, AccWidthUint8, &Data8);
243 // [GPIO] GPIO44: PE_GPIO0 MXM Reset set to 0 for reset, ENH164467
244 RWMEM (GpioMmioAddr + SB_GPIO_REG44, AccWidthUint8, 0xBF, 0);
246 // [GPIO] GPIO45: PE_GPIO1 MXM_POWER_ENABLE, SET HIGH
247 RWMEM (GpioMmioAddr + SB_GPIO_REG45, AccWidthUint8, 0xFF, BIT6);
249 //PeiStall (PeiServices, NULL, 100); //delay 100 ms (should be >1ms)
252 // Write the GPIO55(MXM_PWR_EN) to enable the integrated power module
253 RWMEM (GpioMmioAddr + SB_GPIO_REG55, AccWidthUint8, 0xFF, BIT6);
255 //PeiStall (PeiServices, NULL, 100); //delay 100 ms (should be >1ms)
256 // WAIT POWER READY: GPIO28 (MXM_PWRGD)
257 //while (!(Mmio8 (GpioMmioAddr, SB_GPIO_REG28) && BIT7)){}
258 ReadMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, &Data8);
259 while (!(Data8 && BIT7))
261 ReadMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, &Data8);
263 // [GPIO] GPIO44: PE_GPIO0 MXM Reset set to 1 for reset
264 // RWMEM (GpioMmioAddr + SB_GPIO_REG44, AccWidthUint8, 0xBF, BIT6);
268 // Write the GPIO55(MXM_PWR_EN) to disable the integrated power module
269 RWMEM (GpioMmioAddr + SB_GPIO_REG55, AccWidthUint8, 0xBF, 0);
271 //PeiStall (PeiServices, NULL, 100); //delay 100 ms (should be >1ms)
274 // [GPIO] GPIO45: PE_GPIO1 MXM_POWER_ENABLE down
275 RWMEM (GpioMmioAddr + SB_GPIO_REG45, AccWidthUint8, 0xBF, 0);
279 // APU GPP0: On board LAN
280 // GPIO25: PCIE_RST#_LAN, LOW active
281 // GPIO63: LAN_CLKREQ#
282 // GPIO197: LOM_POWER, HIGH Active
285 // Set EC_PWM0/EC_TIMER0/GPIO197 as GPO for LOM_POWER
286 RWMEM (IoMuxMmioAddr + SB_GPIO_REG197, AccWidthUint8, 00, 0x2); // GPIO
287 // RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x03, 0); // GPO
288 RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x03, BIT6); // output HIGH
289 RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x63, BIT3); // pullup DISABLE
291 // Setup AD25/GPIO25 as GPO for PCIE_RST#_LAN:
292 RWMEM (IoMuxMmioAddr + SB_GPIO_REG25, AccWidthUint8, 00, 0x1); // GPIO
293 // RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x03, 0); // GPO
294 RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x03, BIT6); // output HIGH
295 RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x63, BIT3); // pullup DISABLE
298 // set CLK_REQ3#/SATA_IS1#/GPIO63 as CLK_REQ for LAN_CLKREQ#
299 RWMEM (IoMuxMmioAddr + SB_GPIO_REG63, AccWidthUint8, 00, 0x0); // CLK_REQ3#
300 RWMEM (MiscMmioAddr + SB_MISC_REG00+1, AccWidthUint8, 0x0F, 0xF0); // Enable GPP_CLK3
304 // GPIO1: MPCIE_RST2#, LOW active
305 // GPIO13: WU_DISABLE#, LOW active
306 // GPIO177: MPICE_PD2, 1 - DISABLE, 0 - ENABLE (Default)
308 // Setup VIN2/SATA1_1/GPIO177 as GPO for MPCIE_PD2#: wireless disable
309 RWMEM (IoMuxMmioAddr + SB_GPIO_REG177, AccWidthUint8, 00, 0x2); // GPIO
310 // RWMEM (GpioMmioAddr + SB_GPIO_REG177, AccWidthUint8, 0x03, 0); // GPO
311 RWMEM (GpioMmioAddr + SB_GPIO_REG177, AccWidthUint8, 0x03, 0); // output LOW
312 RWMEM (GpioMmioAddr + SB_GPIO_REG177, AccWidthUint8, 0x63, BIT3); // pullup DISABLE
314 // Setup AD01/GPIO01 as GPO for MPCIE_RST2#
315 RWMEM (IoMuxMmioAddr + SB_GPIO_REG01, AccWidthUint8, 00, 0x1); // GPIO
316 // RWMEM (GpioMmioAddr + SB_GPIO_REG01, AccWidthUint8, 0x03, 0); // GPO
317 RWMEM (GpioMmioAddr + SB_GPIO_REG01, AccWidthUint8, 0x03, BIT6); // output LOW
318 RWMEM (GpioMmioAddr + SB_GPIO_REG01, AccWidthUint8, 0x63, BIT3); // pullup DISABLE
320 // Setup AD13/GPIO13 as GPO for WU_DISABLE#: disable WUSB
321 // RWMEM (IoMuxMmioAddr + SB_GPIO_REG13, AccWidthUint8, 00, 0x1); // GPIO
322 // RWMEM (GpioMmioAddr + SB_GPIO_REG13, AccWidthUint8, 0x03, 0); // GPO
323 // RWMEM (GpioMmioAddr + SB_GPIO_REG13, AccWidthUint8, 0x03, BIT6); // output HIGH
324 // RWMEM (GpioMmioAddr + SB_GPIO_REG13, AccWidthUint8, 0x63, BIT3); // pullup DISABLE
328 // GPIO0: MPCIE_RST1#, LOW active
329 // GPIO14: WP_DISABLE#, LOW active
330 // GPIO176: MPICE_PD1, 1 - DISABLE, 0 - ENABLE (Default)
332 // Set VIN1/GPIO176 as GPO for MPCIE_PD1# for wireless disable
333 RWMEM (IoMuxMmioAddr + SB_GPIO_REG176, AccWidthUint8, 00, 0x1); // GPIO
334 // RWMEM (GpioMmioAddr + SB_GPIO_REG176, AccWidthUint8, 0x03, 0); // GPO
335 RWMEM (GpioMmioAddr + SB_GPIO_REG176, AccWidthUint8, 0x03, 0); // output LOW
336 RWMEM (GpioMmioAddr + SB_GPIO_REG176, AccWidthUint8, 0x63, BIT3); // pullup DISABLE
338 // Set AD00/GPIO00 as GPO for MPCIE_RST1#
339 RWMEM (IoMuxMmioAddr + SB_GPIO_REG00, AccWidthUint8, 00, 0x1); // GPIO
340 // RWMEM (GpioMmioAddr + SB_GPIO_REG00, AccWidthUint8, 0x03, 0); // GPO
341 // RWMEM (GpioMmioAddr + SB_GPIO_REG00, AccWidthUint8, 0x03, BIT6); // output LOW
342 RWMEM (GpioMmioAddr + SB_GPIO_REG00, AccWidthUint8, 0x63, BIT3); // pullup DISABLE
344 // Set AD14/GPIO14 as GPO for WP_DISABLE#: disable WWAN
345 // RWMEM (IoMuxMmioAddr + SB_GPIO_REG14, AccWidthUint8, 00, 0x1); // GPIO
346 // RWMEM (GpioMmioAddr + SB_GPIO_REG14, AccWidthUint8, 0x03, 0); // GPO
347 // RWMEM (GpioMmioAddr + SB_GPIO_REG14, AccWidthUint8, 0x03, BIT6);
348 // RWMEM (GpioMmioAddr + SB_GPIO_REG14, AccWidthUint8, 0x63, BIT3);
352 // GPIO59: Power control, HIGH active
353 // GPIO27: PCIE_RST#_1394, LOW active
357 // Setup SATA_IS5#/FANIN3/GPIO59 as GPO for 1394_ON:
358 RWMEM (IoMuxMmioAddr + SB_GPIO_REG59, AccWidthUint8, 00, 0x2); // GPIO
359 // RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x03, 0); // GPO
360 RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x03, BIT6); // output HIGH
361 RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x63, BIT3); // pullup DISABLE
363 // Setup AD27/GPIO27 as GPO for MPCIE_RST#_1394
364 RWMEM (IoMuxMmioAddr + SB_GPIO_REG27, AccWidthUint8, 00, 0x1); // GPIO
365 // RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x03, 0); // GPO
366 RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x03, BIT6); // output HIGH
367 RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x63, BIT3); // pullup DISABLE
369 // set REQ2#/CLK_REQ2#/GPIO41 as CLK_REQ#
370 RWMEM (IoMuxMmioAddr + SB_GPIO_REG41, AccWidthUint8, 00, 0x1); // CLK_REQ2#
372 // set AZ_SDIN3/GPIO170 as GPO for GPIO_GATE_C
373 RWMEM (IoMuxMmioAddr + SB_GPIO_REG170, AccWidthUint8, 00, 0x1); // GPIO
374 RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0x03, 0); // GPO
375 RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0x03, BIT6); // output HIGH
376 RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0x63, BIT3); // pullup DISABLE
377 // To fix glitch issue
378 RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0xBF, 0); // set GPIO_GATE_C to LOW
380 // Enable/Disable OnBoard LAN
382 if (!CONFIG_ONBOARD_LAN)
384 RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0xBF, 0); // LOM_POWER off
385 RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0xBF, 0);
386 RWMEM (GpioMmioAddr + SB_GPIO_REG63, AccWidthUint8, 0xFF, BIT3); // PULL UP - DISABLED
387 RWMEM (MiscMmioAddr + SB_MISC_REG00+1, AccWidthUint8, 0x0F, 0); // Disable GPP_CLK3
391 // // set BIT3=1 (PULLUP disable), BIT4=0 (PULLDOWN Disable)
392 // RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x23, BIT3);
393 // RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x23, BIT3);
398 // Enable/Disable 1394
400 if (!CONFIG_ONBOARD_1394)
402 // RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0xBF, 0); // set GPIO_GATE_C to LOW
403 RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0xBF, 0); // 1394 power off
404 RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0xBF, 0);
405 RWMEM (GpioMmioAddr + SB_GPIO_REG41, AccWidthUint8, 0xFF, BIT3); // pullup DISABLE
406 RWMEM (MiscMmioAddr + SB_MISC_REG04, AccWidthUint8, 0xF0, 0); // DISABLE GPP_CLK8
407 // RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0xBF, BIT6); // set GPIO_GATE_C to HIGH
411 // // set BIT3=1 (PULLUP disable), BIT4=0 (PULLDOWN Disable), BIT6=1 (output HIGH)
412 // RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x03, BIT6);
413 // RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x63, BIT3);
415 // RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x03, BIT6);
416 // RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x63, BIT3);
420 // external USB 3.0 control:
421 // amdExternalUSBController: CMOS, 0 - AUTO, 1 - DISABLE
422 // GPIO26: PCIE_RST#_USB3.0
423 // GPIO46: PCIE_USB30_CLKREQ#
424 // GPIO200: NEC_USB30_PWR_EN, 0 - OFF, 1 - ON
426 // GPIO172 used as FCH_USB3.0PORT_EN# 0:ENABLE; 1:DISABLE
427 // if ((Amd_SystemConfiguration.XhciSwitch == 1) || (SystemConfiguration.amdExternalUSBController == 1)) {
428 // disable Onboard NEC USB3.0 controller
429 if (!CONFIG_ONBOARD_USB30) {
430 RWMEM (GpioMmioAddr + SB_GPIO_REG200, AccWidthUint8, 0xBF, 0);
431 RWMEM (GpioMmioAddr + SB_GPIO_REG26, AccWidthUint8, 0xBF, 0);
432 RWMEM (GpioMmioAddr + SB_GPIO_REG46, AccWidthUint8, 0xFF, BIT3); // PULL_UP DISABLE
433 RWMEM (MiscMmioAddr + SB_MISC_REG00+3, AccWidthUint8, 0x0F, 0); // DISABLE GPP_CLK7
434 RWMEM (GpioMmioAddr + SB_GPIO_REG172, AccWidthUint8, 0xBF, 0); // FCH_USB3.0PORT_EN# 0:ENABLE; 1:DISABLE
439 // BlueTooth control: BT_ON
440 // amdBlueTooth: CMOS, 0 - AUTO, 1 - DISABLE
441 // GPIO07: BT_ON, 0 - OFF, 1 - ON
443 if (!CONFIG_ONBOARD_BLUETOOTH) {
444 //- if (SystemConfiguration.amdBlueTooth == 1) {
445 RWMEM (GpioMmioAddr + SB_GPIO_REG07, AccWidthUint8, 0xBF, 0);
451 // amdWebCam: CMOS, 0 - AUTO, 1 - DISABLE
452 // GPIO34: WEBCAM_ON#, 0 - ON, 1 - OFF
454 if (!CONFIG_ONBOARD_WEBCAM) {
455 //- if (SystemConfiguration.amdWebCam == 1) {
456 RWMEM (GpioMmioAddr + SB_GPIO_REG34, AccWidthUint8, 0xBF, BIT6);
462 // amdTravisCtrl: CMOS, 0 - DISABLE, 1 - ENABLE
463 // GPIO66: TRAVIS_EN#, 0 - ENABLE, 1 - DISABLE
465 if (!CONFIG_ONBOARD_TRAVIS) {
466 //- if (SystemConfiguration.amdTravisCtrl == 0) {
467 RWMEM (GpioMmioAddr + SB_GPIO_REG66, AccWidthUint8, 0xBF, BIT6);
472 // Disable Light Sensor if needed
474 if (CONFIG_ONBOARD_LIGHTSENSOR) {
475 //- if (SystemConfiguration.amdLightSensor == 1) {
476 RWMEM (IoMuxMmioAddr + SB_GEVENT_REG12, AccWidthUint8, 0x00, 0x1);