2 * This file is part of the coreboot project.
4 * Copyright (C) 2008 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #include <console/console.h>
21 #include <device/device.h>
22 #include <device/pci.h>
23 #include <device/pci_ids.h>
24 #include <device/pci_ops.h>
28 static void ht_dev_set_resources(device_t dev)
30 #if CONFIG_EXT_CONF_SUPPORT == 1
33 resource_t rbase, rend;
35 struct resource *resource;
37 printk(BIOS_DEBUG,"%s %s\n", dev_path(dev), __func__);
39 resource = probe_resource(dev, 0x1C);
41 set_nbmisc_enable_bits(dev, 0x0, 1 << 3, 0 << 3); // make bar3 visible
42 set_nbcfg_enable_bits(dev, 0x7C, 1 << 30, 1 << 30); /* Enables writes to the BAR3 register. */
43 set_nbcfg_enable_bits(dev, 0x84, 7 << 16, 0 << 16); // program bus range: 255 busses
44 pci_write_config32(dev, 0x1C, resource->base);
45 /* Enable MMCONFIG decoding. */
46 set_htiu_enable_bits(dev, 0x32, 1 << 28, 1 << 28); /* PCIEMiscInit */
47 set_nbcfg_enable_bits(dev, 0x7C, 1 << 30, 0 << 30); /* Disable writes to the BAR3 register. */
48 set_nbmisc_enable_bits(dev, 0x0, 1 << 3, 1 << 3); // hide bar 3
50 // setup resource nonposted in k8 mmio
51 /* Get the base address */
52 rbase = resource->base;
53 /* Get the limit (rounded up) */
54 rend = resource_end(resource);
55 printk(BIOS_DEBUG,"%s: %s[0x1C] base = %0llx limit = %0llx\n", __func__, dev_path(dev), rbase, rend);
56 k8_f1 = dev_find_slot(0,PCI_DEVFN(0x18,1));
57 // find a not assigned resource
58 for( reg = 0xb8; reg >= 0x80; reg -= 8 ) {
59 base = pci_read_config32(k8_f1,reg);
60 limit = pci_read_config32(k8_f1,reg+4);
61 if( !(base & 3) ) break; // found a not assigned resource
65 device_t k8_f0 = dev_find_slot(0, PCI_DEVFN(0x18, 0));
66 /* Remember this resource has been stored. */
67 resource->flags |= IORESOURCE_STORED;
68 report_resource_stored(dev, resource, " <mmconfig>");
69 /* Get SBLink value (HyperTransport I/O Hub Link ID). */
70 sblk = (pci_read_config32(k8_f0, 0x64) >> 8) & 0x3;
72 base |= ((rbase >> 8) & 0xffffff00);
75 limit |= ((rend >> 8) & 0xffffff00);
78 printk(BIOS_INFO, "%s <- index %x base %04x limit %04x\n", dev_path(k8_f1), reg, base, limit);
79 pci_write_config32(k8_f1, reg+4, limit);
80 pci_write_config32(k8_f1, reg, base);
84 pci_dev_set_resources(dev);
87 static void ht_dev_read_resources(device_t dev)
89 #if CONFIG_EXT_CONF_SUPPORT == 1
92 printk(BIOS_DEBUG,"%s %s\n", dev_path(dev), __func__);
93 set_nbmisc_enable_bits(dev, 0x0, 1 << 3, 1 << 3); // hide bar 3
96 pci_dev_read_resources(dev);
98 #if CONFIG_EXT_CONF_SUPPORT == 1
99 /* Add an MMCONFIG resource. */
100 res = new_resource(dev, 0x1C);
101 res->base = EXT_CONF_BASE_ADDRESS;
102 res->size = 256 * 1024 * 1024; // 256 busses, 1MB memory space each
103 res->align = log2(res->size);
104 res->gran = log2(res->size);
105 res->limit = 0xffffffffffffffffULL; /* 64bit */
106 res->flags = IORESOURCE_FIXED | IORESOURCE_MEM | IORESOURCE_PCI64 | IORESOURCE_ASSIGNED;
108 compact_resources(dev);
112 /* for UMA internal graphics */
113 void avoid_lpc_dma_deadlock(device_t nb_dev, device_t sb_dev)
118 k8_f0 = dev_find_slot(0, PCI_DEVFN(0x18, 0));
119 set_nbcfg_enable_bits(k8_f0, 0x68, 3 << 21, 1 << 21);
121 reg = nbpcie_p_read_index(sb_dev, 0x10);
122 reg |= 0x100; /* bit9=1 */
123 nbpcie_p_write_index(sb_dev, 0x10, reg);
125 reg = nbpcie_p_read_index(nb_dev, 0x10);
126 reg |= 0x100; /* bit9=1 */
127 nbpcie_p_write_index(nb_dev, 0x10, reg);
129 /* Enable NP protocol over PCIE for memory-mapped writes targeting LPC
130 * Set this bit to avoid a deadlock condition. */
131 reg = htiu_read_index(nb_dev, 0x6);
132 reg |= 0x1000000; /* bit26 */
133 htiu_write_index(nb_dev, 0x6, reg);
136 static void pcie_init(struct device *dev)
138 /* Enable pci error detecting */
141 printk(BIOS_INFO, "pcie_init in rs690_ht.c\n");
143 /* System error enable */
144 dword = pci_read_config32(dev, 0x04);
145 dword |= (1 << 8); /* System error enable */
146 dword |= (1 << 30); /* Clear possible errors */
147 pci_write_config32(dev, 0x04, dword);
151 * 18 is enable nb to accept A4 interrupt request from SB.
153 dword = pci_read_config32(dev, 0x4C);
154 dword |= 1 << 1 | 1 << 18; /* Clear possible errors */
155 pci_write_config32(dev, 0x4C, dword);
158 static void ht_dev_set_subsystem(struct device *dev, unsigned vendor, unsigned device)
160 pci_write_config32(dev, 0x50, ((device & 0xffff) << 16) | (vendor & 0xffff));
163 static struct pci_operations lops_pci = {
164 .set_subsystem = ht_dev_set_subsystem,
167 static struct device_operations ht_ops = {
168 .read_resources = ht_dev_read_resources,
169 .set_resources = ht_dev_set_resources,
170 .enable_resources = pci_dev_enable_resources,
173 .ops_pci = &lops_pci,
176 static const struct pci_driver ht_driver __pci_driver = {
178 .vendor = PCI_VENDOR_ID_ATI,
179 .device = PCI_DEVICE_ID_ATI_RS690_HT,