src/mainboard/supermicro/h8qgi/romstage.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2011 Advanced Micro Devices, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18  */
  19
  20 #include <lib.h>
  21 #include <reset.h>
  22 #include <stdint.h>
  23 #include <arch/io.h>
  24 #include <arch/romcc_io.h>
  25 #include <arch/cpu.h>
  26 #include <console/console.h>
  27 #include <arch/stages.h>
  28 #include "cpu/x86/bist.h"
  29 #include "cpu/x86/lapic/boot_cpu.c"
  30 #include "agesawrapper.h"
  31 #include "northbridge/amd/agesa/family10/reset_test.h"
  32 #include "southbridge/amd/sr5650/sr5650.h"
  33 #include "southbridge/amd/sb700/sb700.h"
  34 #include "superio/nuvoton/wpcm450/wpcm450.h"
  35
  36 extern void disable_cache_as_ram(void); /* cache_as_ram.inc */
  37
  38 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
  39 {
  40         u32 val;
  41
  42         agesawrapper_amdinitmmio();
  43         if (!cpu_init_detectedx && boot_cpu()) {
  44                 post_code(0x30);
  45                 /* SR56x0 pcie bridges block pci_locate_device() before pcie training.
  46                  * disable all pcie bridges on SR56x0 to work around it
  47                  */
  48                 sr5650_disable_pcie_bridge();
  49                 post_code(0x31);
  50                 sb7xx_51xx_lpc_port80();
  51                 post_code(0x32);
  52         }
  53
  54         /* Halt if there was a built in self test failure */
  55         post_code(0x33);
  56         report_bist_failure(bist);
  57
  58         enable_sr5650_dev8();
  59         sb7xx_51xx_lpc_init();
  60         sb7xx_51xx_enable_wideio(0, 0x1600); /* though UARTs are on the NUVOTON BMC */
  61         wpcm450_enable_dev(WPCM450_SP1, CONFIG_SIO_PORT, CONFIG_TTYS0_BASE);
  62         sb7xx_51xx_disable_wideio(0);
  63         post_code(0x34);
  64
  65         uart_init();
  66         post_code(0x35);
  67         console_init();
  68
  69         val = cpuid_eax(1);
  70         printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
  71         printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
  72
  73         post_code(0x37);
  74         val = agesawrapper_amdinitreset();
  75         if (val) {
  76                 printk(BIOS_DEBUG, "agesawrapper_amdinitreset failed: %x \n", val);
  77         } else {
  78                 printk(BIOS_DEBUG, "agesawrapper_amdinitreset passed\n");
  79         }
  80
  81         post_code(0x38);
  82         val = agesawrapper_amdinitearly();
  83         if(val) {
  84                 printk(BIOS_DEBUG, "agesawrapper_amdinitearly failed: %x \n", val);
  85         } else {
  86                 printk(BIOS_DEBUG, "agesawrapper_amdinitearly passed\n");
  87         }
  88
  89         sr5650_early_setup();
  90         post_code(0x39);
  91
  92         sb7xx_51xx_early_setup();
  93         sr5650_htinit();
  94         /* Reset for HT, FIDVID, PLL and errata changes to take affect. */
  95         if (!warm_reset_detect(0)) {
  96                 print_info("...WARM RESET...\n\n\n");
  97                 distinguish_cpu_resets(0);
  98                 soft_reset();
  99                 die("After soft_reset_x - shouldn't see this message!!!\n");
 100         }
 101
 102         post_code(0x40);
 103         val = agesawrapper_amdinitpost();
 104         if (val) {
 105                 printk(BIOS_DEBUG, "agesawrapper_amdinitpost failed: %x \n", val);
 106         }
 107         printk(BIOS_DEBUG, "agesawrapper_amdinitpost passed\n");
 108
 109         post_code(0x41);
 110         val = agesawrapper_amdinitenv();
 111         if(val) {
 112                 printk(BIOS_DEBUG, "agesawrapper_amdinitenv failed: %x \n", val);
 113         }
 114         printk(BIOS_DEBUG, "agesawrapper_amdinitenv passed\n");
 115
 116         post_code(0x42);
 117         sr5650_before_pci_init();
 118         sb7xx_51xx_before_pci_init();
 119
 120         post_code(0x50);
 121         print_debug("Disabling cache as ram ");
 122         disable_cache_as_ram();
 123         print_debug("done\n");
 124
 125         post_code(0x51);
 126         copy_and_run(0);
 127
 128         /* We will not return,  Should never see this message and post code. */
 129         print_debug("should not be here -\n");
 130         post_code(0x54);
 131 }
 132