2 * This file is part of the coreboot project.
4 * Copyright (C) 2006 Tyan
5 * Copyright (C) 2006 AMD
6 * Written by Yinghai Lu <yinghailu@gmail.com> for Tyan and AMD.
8 * Copyright (C) 2007 University of Mannheim
9 * Written by Philipp Degler <pdegler@rumms.uni-mannheim.de> for University of Mannheim
10 * Copyright (C) 2009 University of Heidelberg
11 * Written by Mondrian Nuessle <nuessle@uni-heidelberg.de> for University of Heidelberg
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 #define FAM10_SCAN_PCI_BUS 0
29 #define FAM10_ALLOCATE_IO_RANGE 1
33 #include <device/pci_def.h>
34 #include <device/pci_ids.h>
36 #include <device/pnp_def.h>
37 #include <arch/romcc_io.h>
38 #include <cpu/x86/lapic.h>
39 #include "option_table.h"
40 #include <console/console.h>
41 #include <cpu/amd/model_10xxx_rev.h>
42 #include "southbridge/broadcom/bcm5785/early_smbus.c"
43 #include "northbridge/amd/amdfam10/raminit.h"
44 #include "northbridge/amd/amdfam10/amdfam10.h"
47 #include "cpu/amd/model_10xxx/apic_timer.c"
48 #include "lib/delay.c"
49 #include "cpu/x86/lapic/boot_cpu.c"
50 #include "northbridge/amd/amdfam10/reset_test.c"
51 #include "superio/serverengines/pilot/early_serial.c"
52 #include "superio/serverengines/pilot/early_init.c"
53 #include "superio/nsc/pc87417/early_serial.c"
54 #include "cpu/x86/bist.h"
55 #include "northbridge/amd/amdfam10/debug.c"
56 #include "cpu/x86/mtrr/earlymtrr.c"
57 //#include "northbridge/amd/amdfam10/setup_resource_map.c"
58 #include "southbridge/broadcom/bcm5785/early_setup.c"
60 #define SERIAL_DEV PNP_DEV(0x2e, PILOT_SP1)
61 #define RTC_DEV PNP_DEV(0x4e, PC87417_RTC)
63 static inline void activate_spd_rom(const struct mem_controller *ctrl)
71 outb((val & ~3) | ctrl->spd_switch_addr, 0xcd7);
74 static inline int spd_read_byte(unsigned device, unsigned address)
76 return smbus_read_byte(device, address);
79 #include "northbridge/amd/amdfam10/amdfam10.h"
80 #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
81 #include "northbridge/amd/amdfam10/pci.c"
82 #include "cpu/amd/quadcore/quadcore.c"
83 #include "cpu/amd/car/post_cache_as_ram.c"
84 #include "cpu/amd/microcode/microcode.c"
86 #if CONFIG_UPDATE_CPU_MICROCODE
87 #include "cpu/amd/model_10xxx/update_microcode.c"
90 #include "cpu/amd/model_10xxx/init_cpus.c"
91 #include "northbridge/amd/amdfam10/early_ht.c"
93 static const u8 spd_addr[] = {
94 // switch addr, 1A addr, 2A addr, 3A addr, 4A addr, 1B addr, 2B addr, 3B addr 4B addr
96 RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
97 #if CONFIG_MAX_PHYSICAL_CPUS > 1
99 RC01, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
103 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
105 struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
106 u32 bsp_apicid = 0, val;
109 if (!cpu_init_detectedx && boot_cpu()) {
110 /* Nothing special needs to be done to find bus 0 */
111 /* Allow the HT devices to be found */
112 /* mov bsp to bus 0xff when > 8 nodes */
113 set_bsp_node_CHtExtNodeCfgEn();
114 enumerate_ht_chain();
115 bcm5785_enable_lpc();
116 pc87417_enable_dev(RTC_DEV); /* Enable RTC */
122 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
124 pilot_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
128 /* Halt if there was a built in self test failure */
129 report_bist_failure(bist);
131 pilot_early_init(SERIAL_DEV); //config port is being taken from SERIAL_DEV
134 printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
135 printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
136 printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid);
137 printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
139 /* Setup sysinfo defaults */
140 set_sysinfo_in_ram(0);
142 #if CONFIG_UPDATE_CPU_MICROCODE
143 update_microcode(val);
150 amd_ht_init(sysinfo);
153 /* Setup nodes PCI space and start core 0 AP init. */
154 finalize_node_setup(sysinfo);
158 /* wait for all the APs core0 started by finalize_node_setup. */
159 /* FIXME: A bunch of cores are going to start output to serial at once.
160 * It would be nice to fixup prink spinlocks for ROM XIP mode.
161 * I think it could be done by putting the spinlock flag in the cache
162 * of the BSP located right after sysinfo.
165 wait_all_core0_started();
167 #if CONFIG_LOGICAL_CPUS==1
168 /* Core0 on each node is configured. Now setup any additional cores. */
169 printk(BIOS_DEBUG, "start_other_cores()\n");
172 wait_all_other_cores_started(bsp_apicid);
175 #if CONFIG_SET_FIDVID
176 msr = rdmsr(0xc0010071);
177 printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
179 /* FIXME: The sb fid change may survive the warm reset and only
180 * need to be done once.*/
182 enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
186 if (!warm_reset_detect(0)) { // BSP is node 0
187 init_fidvid_bsp(bsp_apicid, sysinfo->nodes);
189 init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0
194 /* show final fid and vid */
195 msr=rdmsr(0xc0010071);
196 printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
201 /* Reset for HT, FIDVID, PLL and errata changes to take affect. */
202 if (!warm_reset_detect(0)) {
203 print_info("...WARM RESET...\n\n\n");
205 die("After soft_reset_x - shouldn't see this message!!!\n");
208 /* It's the time to set ctrl in sysinfo now; */
209 fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
212 //do we need apci timer, tsc...., only debug need it for better output
213 /* all ap stopped? */
214 // init_timer(); // Need to use TMICT to synconize FID/VID
216 printk(BIOS_DEBUG, "raminit_amdmct()\n");
217 raminit_amdmct(sysinfo);
220 bcm5785_early_setup();
226 * BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List)
228 * This routine is called every time a non-coherent chain is processed.
229 * BUID assignment may be controlled explicitly on a non-coherent chain. Provide a
230 * swap list. The first part of the list controls the BUID assignment and the
231 * second part of the list provides the device to device linking. Device orientation
232 * can be detected automatically, or explicitly. See documentation for more details.
234 * Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially
235 * based on each device's unit count.
238 * @param[in] u8 node = The node on which this chain is located
239 * @param[in] u8 link = The link on the host for this chain
240 * @param[out] u8** list = supply a pointer to a list
241 * @param[out] BOOL result = true to use a manual list
242 * false to initialize the link automatically
244 BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List)
246 static const u8 swaplist[] = { 0xFF, CONFIG_HT_CHAIN_UNITID_BASE, CONFIG_HT_CHAIN_END_UNITID_BASE, 0xFF };
247 /* If the BUID was adjusted in early_ht we need to do the manual override */
248 if ((CONFIG_HT_CHAIN_UNITID_BASE != 0) && (CONFIG_HT_CHAIN_END_UNITID_BASE != 0)) {
249 printk(BIOS_DEBUG, "AMD_CB_ManualBUIDSwapList()\n");
250 if ((node == 0) && (link == 0)) { /* BSP SB link */