2 * This file is part of the coreboot project.
4 * Copyright (C) 2011 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
23 #include "heapManager.h"
24 #include "PlatformGnbPcieComplex.h"
27 #define FILECODE PROC_GNB_PCIE_FAMILY_0X12_F12PCIECOMPLEXCONFIG_FILECODE
29 PCIe_PORT_DESCRIPTOR PortList [] = {
30 // Initialize Port descriptor (PCIe port, Lanes 8:15, PCI Device Number 2, ...)
33 PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 8, 15),
34 PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 2, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, BIT2)
36 // Initialize Port descriptor (PCIe port, Lanes 16:19, PCI Device Number 3, ...)
39 PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 16, 19),
40 PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 3, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, BIT3)
42 // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...)
44 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array
45 PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4),
46 PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0)
48 // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...)
50 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array
51 PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5),
52 PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 5, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0)
54 // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...)
56 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array
57 PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6),
58 PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 6, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0)
60 // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...)
62 DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array
63 PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7),
64 PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 7, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0)
66 // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)
68 // DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array
69 // PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 8, 8),
70 // PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0)
74 PCIe_DDI_DESCRIPTOR DdiList [] = {
75 // Initialize Ddi descriptor (DDI interface Lanes 24:27, DdA, ...)
78 PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 24, 27),
79 PCIE_DDI_DATA_INITIALIZER (ConnectorTypeNutmegDpToVga, Aux2, Hdp2)
81 // Initialize Ddi descriptor (DDI interface Lanes 28:31, DdB, ...)
83 DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array
84 PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 28, 31),
85 PCIE_DDI_DATA_INITIALIZER (ConnectorTypeEDP, Aux1, Hdp1)
89 PCIe_COMPLEX_DESCRIPTOR Llano = {
90 DESCRIPTOR_TERMINATE_LIST,
96 /*---------------------------------------------------------------------------------------*/
98 * OemCustomizeInitEarly
101 * This is the stub function will call the host environment through the binary block
102 * interface (call-out port) to provide a user hook opportunity
105 * @param[in] **PeiServices
106 * @param[in] *InitEarly
111 /*---------------------------------------------------------------------------------------*/
113 OemCustomizeInitEarly (
114 IN OUT AMD_EARLY_PARAMS *InitEarly
118 VOID *LlanoPcieComplexListPtr;
119 VOID *LlanoPciePortPtr;
120 VOID *LlanoPcieDdiPtr;
122 ALLOCATE_HEAP_PARAMS AllocHeapParams;
124 // GNB PCIe topology Porting
127 // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
129 AllocHeapParams.RequestedBufferSize = (sizeof (PCIe_COMPLEX_DESCRIPTOR) +
130 sizeof (PCIe_PORT_DESCRIPTOR) * 7 +
131 sizeof (PCIe_DDI_DESCRIPTOR)) * 6;
133 AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START;
134 AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
135 Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader);
136 if ( Status!= AGESA_SUCCESS) {
137 // Could not allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
142 LlanoPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
144 AllocHeapParams.BufferPtr += sizeof (PCIe_COMPLEX_DESCRIPTOR);
145 LlanoPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr;
147 AllocHeapParams.BufferPtr += sizeof (PCIe_PORT_DESCRIPTOR) * 7;
148 LlanoPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr;
150 LibAmdMemFill (LlanoPcieComplexListPtr,
152 sizeof (PCIe_COMPLEX_DESCRIPTOR),
153 &InitEarly->StdHeader);
155 LibAmdMemFill (LlanoPciePortPtr,
157 sizeof (PCIe_PORT_DESCRIPTOR) * 7,
158 &InitEarly->StdHeader);
160 LibAmdMemFill (LlanoPcieDdiPtr,
162 sizeof (PCIe_DDI_DESCRIPTOR) * 6,
163 &InitEarly->StdHeader);
165 LibAmdMemCopy (LlanoPcieComplexListPtr, &Llano, sizeof (PCIe_COMPLEX_DESCRIPTOR), &InitEarly->StdHeader);
166 LibAmdMemCopy (LlanoPciePortPtr, &PortList[0], sizeof (PCIe_PORT_DESCRIPTOR) * 7, &InitEarly->StdHeader);
167 LibAmdMemCopy (LlanoPcieDdiPtr, &DdiList[0], sizeof (PCIe_DDI_DESCRIPTOR) * 6, &InitEarly->StdHeader);
170 ((PCIe_COMPLEX_DESCRIPTOR*)LlanoPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)LlanoPciePortPtr;
171 ((PCIe_COMPLEX_DESCRIPTOR*)LlanoPcieComplexListPtr)->DdiLinkList = (PCIe_DDI_DESCRIPTOR*)LlanoPcieDdiPtr;
173 InitEarly->GnbConfig.PcieComplexList = LlanoPcieComplexListPtr;
174 InitEarly->GnbConfig.PsppPolicy = 0;