src/mainboard/amd/torpedo/fadt.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2011 Advanced Micro Devices, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18  */
  19
  20
  21 /*
  22  * ACPI - create the Fixed ACPI Description Tables (FADT)
  23  */
  24
  25
  26 #include <string.h>
  27 #include <console/console.h>
  28 #include <arch/acpi.h>
  29 #include <arch/io.h>
  30 #include <device/device.h>
  31 //#include "../../../southbridge/amd/sb900/sb900.h"
  32
  33 /*extern*/ u16 pm_base = 0x800;
  34 /* pm_base should be set in sb acpi */
  35 /* pm_base should be got from bar2 of sb900. Here I compact ACPI
  36  * registers into 32 bytes limit.
  37  * */
  38
  39 #define ACPI_PM_EVT_BLK         (pm_base + 0x00) /* 4 bytes */
  40 #define ACPI_PM1_CNT_BLK        (pm_base + 0x04) /* 2 bytes */
  41 #define ACPI_PM2_CNT_BLK        (pm_base + 0x0F) /* 1 byte */
  42 #define ACPI_PM_TMR_BLK         (pm_base + 0x08) /* 4 bytes */
  43 #define ACPI_GPE0_BLK           (pm_base + 0x20) /* 8 bytes */
  44 #define ACPI_CPU_CONTORL        (pm_base + 0x10) /* 6 bytes */
  45 void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
  46 {
  47         acpi_header_t *header = &(fadt->header);
  48
  49         pm_base &= 0xFFFF;
  50         printk(BIOS_DEBUG, "pm_base: 0x%04x\n", pm_base);
  51
  52         /* Prepare the header */
  53         memset((void *)fadt, 0, sizeof(acpi_fadt_t));
  54         memcpy(header->signature, "FACP", 4);
  55         header->length = 244;
  56         header->revision = 1;
  57         memcpy(header->oem_id, OEM_ID, 6);
  58   memcpy(header->oem_table_id, "AMD     ", 8);
  59         memcpy(header->asl_compiler_id, ASLC, 4);
  60         header->asl_compiler_revision = 0;
  61
  62         fadt->firmware_ctrl = (u32) facs;
  63         fadt->dsdt = (u32) dsdt;
  64         /* 3=Workstation,4=Enterprise Server, 7=Performance Server */
  65         fadt->preferred_pm_profile = 0x03;
  66         fadt->sci_int = 9;
  67         /* disable system management mode by setting to 0: */
  68         fadt->smi_cmd = 0;
  69         fadt->acpi_enable = 0xf0;
  70         fadt->acpi_disable = 0xf1;
  71         fadt->s4bios_req = 0x0;
  72         fadt->pstate_cnt = 0xe2;
  73
  74         pm_iowrite(0x60, ACPI_PM_EVT_BLK & 0xFF);
  75         pm_iowrite(0x61, ACPI_PM_EVT_BLK >> 8);
  76         pm_iowrite(0x62, ACPI_PM1_CNT_BLK & 0xFF);
  77         pm_iowrite(0x63, ACPI_PM1_CNT_BLK >> 8);
  78         pm_iowrite(0x64, ACPI_PM_TMR_BLK & 0xFF);
  79         pm_iowrite(0x65, ACPI_PM_TMR_BLK >> 8);
  80         pm_iowrite(0x68, ACPI_GPE0_BLK & 0xFF);
  81         pm_iowrite(0x69, ACPI_GPE0_BLK >> 8);
  82
  83         /* CpuControl is in \_PR.CPU0, 6 bytes */
  84         pm_iowrite(0x66, ACPI_CPU_CONTORL & 0xFF);
  85         pm_iowrite(0x67, ACPI_CPU_CONTORL >> 8);
  86
  87         pm_iowrite(0x6A, 0);    /* AcpiSmiCmdLo */
  88         pm_iowrite(0x6B, 0);    /* AcpiSmiCmdHi */
  89
  90         pm_iowrite(0x6E, ACPI_PM2_CNT_BLK & 0xFF);
  91         pm_iowrite(0x6F, ACPI_PM2_CNT_BLK >> 8);
  92
  93         pm_iowrite(0x74, 1<<0 | 1<<1 | 1<<4 | 1<<2); /* AcpiDecodeEnable, When set, SB uses
  94                                         * the contents of the PM registers at
  95                                         * index 60-6B to decode ACPI I/O address.
  96                                         * AcpiSmiEn & SmiCmdEn*/
  97         /* RTC_En_En, TMR_En_En, GBL_EN_EN */
  98         outl(0x1, ACPI_PM1_CNT_BLK);              /* set SCI_EN */
  99         fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK;
 100         fadt->pm1b_evt_blk = 0x0000;
 101         fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK;
 102         fadt->pm1b_cnt_blk = 0x0000;
 103         fadt->pm2_cnt_blk = ACPI_PM2_CNT_BLK;
 104         fadt->pm_tmr_blk = ACPI_PM_TMR_BLK;
 105         fadt->gpe0_blk = ACPI_GPE0_BLK;
 106         fadt->gpe1_blk = 0x0000;        /* we dont have gpe1 block, do we? */
 107
 108         fadt->pm1_evt_len = 4;
 109         fadt->pm1_cnt_len = 2;
 110         fadt->pm2_cnt_len = 1;
 111         fadt->pm_tmr_len = 4;
 112         fadt->gpe0_blk_len = 8;
 113         fadt->gpe1_blk_len = 0;
 114         fadt->gpe1_base = 0;
 115
 116         fadt->cst_cnt = 0xe3;
 117         fadt->p_lvl2_lat = 101;
 118         fadt->p_lvl3_lat = 1001;
 119         fadt->flush_size = 0;
 120         fadt->flush_stride = 0;
 121         fadt->duty_offset = 1;
 122         fadt->duty_width = 3;
 123         fadt->day_alrm = 0;     /* 0x7d these have to be */
 124         fadt->mon_alrm = 0;     /* 0x7e added to cmos.layout */
 125         fadt->century = 0;      /* 0x7f to make rtc alrm work */
 126         fadt->iapc_boot_arch = 0x3;     /* See table 5-11 */
 127         fadt->flags = 0x0001c1a5;/* 0x25; */
 128
 129         fadt->res2 = 0;
 130
 131         fadt->reset_reg.space_id = 1;
 132         fadt->reset_reg.bit_width = 8;
 133         fadt->reset_reg.bit_offset = 0;
 134         fadt->reset_reg.resv = 0;
 135         fadt->reset_reg.addrl = 0xcf9;
 136         fadt->reset_reg.addrh = 0x0;
 137
 138         fadt->reset_value = 6;
 139         fadt->x_firmware_ctl_l = (u32) facs;
 140         fadt->x_firmware_ctl_h = 0;
 141         fadt->x_dsdt_l = (u32) dsdt;
 142         fadt->x_dsdt_h = 0;
 143
 144         fadt->x_pm1a_evt_blk.space_id = 1;
 145         fadt->x_pm1a_evt_blk.bit_width = 32;
 146         fadt->x_pm1a_evt_blk.bit_offset = 0;
 147         fadt->x_pm1a_evt_blk.resv = 0;
 148         fadt->x_pm1a_evt_blk.addrl = ACPI_PM_EVT_BLK;
 149         fadt->x_pm1a_evt_blk.addrh = 0x0;
 150
 151         fadt->x_pm1b_evt_blk.space_id = 1;
 152         fadt->x_pm1b_evt_blk.bit_width = 4;
 153         fadt->x_pm1b_evt_blk.bit_offset = 0;
 154         fadt->x_pm1b_evt_blk.resv = 0;
 155         fadt->x_pm1b_evt_blk.addrl = 0x0;
 156         fadt->x_pm1b_evt_blk.addrh = 0x0;
 157
 158
 159         fadt->x_pm1a_cnt_blk.space_id = 1;
 160         fadt->x_pm1a_cnt_blk.bit_width = 16;
 161         fadt->x_pm1a_cnt_blk.bit_offset = 0;
 162         fadt->x_pm1a_cnt_blk.resv = 0;
 163         fadt->x_pm1a_cnt_blk.addrl = ACPI_PM1_CNT_BLK;
 164         fadt->x_pm1a_cnt_blk.addrh = 0x0;
 165
 166         fadt->x_pm1b_cnt_blk.space_id = 1;
 167         fadt->x_pm1b_cnt_blk.bit_width = 2;
 168         fadt->x_pm1b_cnt_blk.bit_offset = 0;
 169         fadt->x_pm1b_cnt_blk.resv = 0;
 170         fadt->x_pm1b_cnt_blk.addrl = 0x0;
 171         fadt->x_pm1b_cnt_blk.addrh = 0x0;
 172
 173
 174         fadt->x_pm2_cnt_blk.space_id = 1;
 175         fadt->x_pm2_cnt_blk.bit_width = 0;
 176         fadt->x_pm2_cnt_blk.bit_offset = 0;
 177         fadt->x_pm2_cnt_blk.resv = 0;
 178         fadt->x_pm2_cnt_blk.addrl = ACPI_PM2_CNT_BLK;
 179         fadt->x_pm2_cnt_blk.addrh = 0x0;
 180
 181
 182         fadt->x_pm_tmr_blk.space_id = 1;
 183         fadt->x_pm_tmr_blk.bit_width = 32;
 184         fadt->x_pm_tmr_blk.bit_offset = 0;
 185         fadt->x_pm_tmr_blk.resv = 0;
 186         fadt->x_pm_tmr_blk.addrl = ACPI_PM_TMR_BLK;
 187         fadt->x_pm_tmr_blk.addrh = 0x0;
 188
 189
 190         fadt->x_gpe0_blk.space_id = 1;
 191         fadt->x_gpe0_blk.bit_width = 32;
 192         fadt->x_gpe0_blk.bit_offset = 0;
 193         fadt->x_gpe0_blk.resv = 0;
 194         fadt->x_gpe0_blk.addrl = ACPI_GPE0_BLK;
 195         fadt->x_gpe0_blk.addrh = 0x0;
 196
 197
 198         fadt->x_gpe1_blk.space_id = 1;
 199         fadt->x_gpe1_blk.bit_width = 0;
 200         fadt->x_gpe1_blk.bit_offset = 0;
 201         fadt->x_gpe1_blk.resv = 0;
 202         fadt->x_gpe1_blk.addrl = 0;
 203         fadt->x_gpe1_blk.addrh = 0x0;
 204
 205         header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t));
 206
 207 }