src/southbridge/via/k8t890/ctrl.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
   5  * Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me@gmail.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  19  */
  20
  21 #include <device/device.h>
  22 #include <device/pci.h>
  23 #include <device/pci_ops.h>
  24 #include <device/pci_ids.h>
  25 #include <console/console.h>
  26 #include "k8x8xx.h"
  27
  28 /* We support here K8M890/K8T890 and VT8237R PCI1/Vlink which setup is not in separate
  29  * PCI device 0:11.7, but it is mapped to PCI 0:0.7 (0x70-0x7c for PCI1)
  30  */
  31
  32 static void vt8237r_cfg(struct device *dev, struct device *devsb)
  33 {
  34         u8 regm, regm3;
  35
  36         device_t devfun3;
  37
  38         devfun3 = dev_find_device(PCI_VENDOR_ID_VIA,
  39                                            PCI_DEVICE_ID_VIA_K8T800_DRAM, 0);
  40
  41         if (!devfun3)
  42                 devfun3 = dev_find_device(PCI_VENDOR_ID_VIA,
  43                                            PCI_DEVICE_ID_VIA_K8M800_DRAM, 0);
  44
  45         if (!devfun3)
  46                 devfun3 = dev_find_device(PCI_VENDOR_ID_VIA,
  47                                            PCI_DEVICE_ID_VIA_K8T890CE_3, 0);
  48
  49         if (!devfun3)
  50                 devfun3 = dev_find_device(PCI_VENDOR_ID_VIA,
  51                                            PCI_DEVICE_ID_VIA_K8T890CF_3, 0);
  52
  53         if (!devfun3)
  54                 devfun3 = dev_find_device(PCI_VENDOR_ID_VIA,
  55                                            PCI_DEVICE_ID_VIA_K8M890CE_3, 0);
  56
  57         if(!devfun3)
  58                 die("\n vt8237r_cfg: Unable to find K8x8xx bridge via PCI scan. Stopping.\n");
  59
  60         pci_write_config8(dev, 0x70, 0xc2);
  61
  62         /* PCI Control */
  63         pci_write_config8(dev, 0x72, 0xee);
  64         pci_write_config8(dev, 0x73, 0x01);
  65         pci_write_config8(dev, 0x74, 0x24);
  66         pci_write_config8(dev, 0x75, 0x0f);
  67         pci_write_config8(dev, 0x76, 0x50);
  68         pci_write_config8(dev, 0x77, 0x08);
  69         pci_write_config8(dev, 0x78, 0x01);
  70         /* APIC on HT */
  71         pci_write_config8(dev, 0x7c, 0x7f);
  72         pci_write_config8(dev, 0x7f, 0x02);
  73
  74         /* WARNING: Need to copy some registers from NB (D0F3) to SB (D0F7). */
  75
  76         regm = pci_read_config8(devfun3, 0x88); /* Shadow mem CTRL */
  77         pci_write_config8(dev, 0x57, regm);
  78
  79         regm = pci_read_config8(devfun3, 0x80); /* Shadow page C */
  80         pci_write_config8(dev, 0x61, regm);
  81
  82         regm = pci_read_config8(devfun3, 0x81); /* Shadow page D */
  83         pci_write_config8(dev, 0x62, regm);
  84
  85         regm = pci_read_config8(devfun3, 0x86); /* SMM and APIC decoding */
  86         pci_write_config8(dev, 0xe6, regm);
  87
  88         regm3 = pci_read_config8(devfun3, 0x82);/* Shadow page E */
  89
  90         /*
  91          * All access bits for 0xE0000-0xEFFFF encode as just 2 bits!
  92          * So the NB reg is quite inconsistent, we expect there only 0xff or 0x00,
  93          * and write them to 0x63 7-6 but! VIA 8237A has the mirror at 0x64!
  94          */
  95         if (regm3 == 0xff)
  96                 regm3 = 0xc0;
  97         else
  98                 regm3 = 0x0;
  99
 100         /* Shadow page F + memhole copy */
 101         regm = pci_read_config8(devfun3, 0x83);
 102         pci_write_config8(dev, 0x63, regm3 | (regm & 0x3F));
 103
 104 }
 105
 106
 107
 108 /**
 109  * Setup the V-Link for VT8237R, 8X mode.
 110  *
 111  * For K8T890CF VIA recommends what is in VIA column, AW is award 8X:
 112  *
 113  *                                               REG   DEF   AW  VIA-8X VIA-4X
 114  *                                               -----------------------------
 115  * NB V-Link Manual Driving Control strobe       0xb5  0x46  0x46  0x88  0x88
 116  * NB V-Link Manual Driving Control - Data       0xb6  0x46  0x46  0x88  0x88
 117  * NB V-Link Receiving Strobe Delay              0xb7  0x02  0x02  0x61  0x01
 118  * NB V-Link Compensation Control bit4,0 (b5,b6) 0xb4  0x10  0x10  0x11  0x11
 119  * SB V-Link Strobe Drive Control                0xb9  0x00  0xa5  0x98  0x98
 120  * SB V-Link Data drive Control????              0xba  0x00  0xbb  0x77  0x77
 121  * SB V-Link Receive Strobe Delay????            0xbb  0x04  0x11  0x11  0x11
 122  * SB V-Link Compensation Control bit0 (use b9)  0xb8  0x00  0x01  0x01  0x01
 123  * V-Link CKG Control                            0xb0  0x05  0x05  0x06  0x03
 124  * V-Link CKG Control                            0xb1  0x05  0x05  0x01  0x03
 125  */
 126
 127 static void vt8237r_vlink_init(struct device *dev)
 128 {
 129         u8 reg;
 130
 131         /*
 132          * This init code is valid only for the VT8237R! For different
 133          * sounthbridges (e.g. VT8237A, VT8237S, VT8237 (without plus R)
 134          * and VT8251) a different init code is required.
 135          */
 136
 137         pci_write_config8(dev, 0xb5, 0x88);
 138         pci_write_config8(dev, 0xb6, 0x88);
 139         pci_write_config8(dev, 0xb7, 0x61);
 140
 141         reg = pci_read_config8(dev, 0xb4);
 142         reg |= 0x11;
 143         pci_write_config8(dev, 0xb4, reg);
 144
 145         pci_write_config8(dev, 0xb9, 0x98);
 146         pci_write_config8(dev, 0xba, 0x77);
 147         pci_write_config8(dev, 0xbb, 0x11);
 148
 149         reg = pci_read_config8(dev, 0xb8);
 150         reg |= 0x1;
 151         pci_write_config8(dev, 0xb8, reg);
 152
 153         pci_write_config8(dev, 0xb0, 0x06);
 154         pci_write_config8(dev, 0xb1, 0x01);
 155
 156         /* Program V-link 8X 16bit full duplex, parity enabled. */
 157         pci_write_config8(dev, 0x48, 0xa3);
 158 }
 159
 160 static void ctrl_init(struct device *dev)
 161 {
 162
 163         print_debug("K8x8xx: Initializing V-Link to VT8237R sb: ");
 164         /* TODO: Fix some ordering issue fo V-link set Rx77[6] and PCI1_Rx4F[0]
 165            should to 1 */
 166
 167         /* C2P Read ACK Return Priority */
 168         /* PCI CFG Address bits[27:24] are used as extended register address
 169            bit[11:8] */
 170
 171         pci_write_config8(dev, 0x47, 0x30);
 172
 173         /* VT8237R specific configuration  other SB are done in their own directories */
 174
 175         device_t devsb = dev_find_device(PCI_VENDOR_ID_VIA,
 176                                          PCI_DEVICE_ID_VIA_VT8237R_LPC, 0);
 177         if (devsb) {
 178                 vt8237r_vlink_init(dev);
 179                 vt8237r_cfg(dev, devsb);
 180         } else {
 181                 print_debug("VT8237R LPC not found !\n");
 182                 return;
 183         }
 184         print_debug(" Done\n");
 185         print_debug(" VIA_X_7 device dump:\n");
 186         dump_south(dev);
 187
 188 }
 189
 190 static const struct device_operations ctrl_ops = {
 191         .read_resources         = pci_dev_read_resources,
 192         .set_resources          = pci_dev_set_resources,
 193         .enable_resources       = pci_dev_enable_resources,
 194         .init                   = ctrl_init,
 195         .ops_pci                = 0,
 196 };
 197
 198 static const struct pci_driver northbridge_driver_t800 __pci_driver = {
 199         .ops    = &ctrl_ops,
 200         .vendor = PCI_VENDOR_ID_VIA,
 201         .device = PCI_DEVICE_ID_VIA_K8T800_NB_SB_CTR,
 202 };
 203
 204 static const struct pci_driver northbridge_driver_m800 __pci_driver = {
 205         .ops    = &ctrl_ops,
 206         .vendor = PCI_VENDOR_ID_VIA,
 207         .device = PCI_DEVICE_ID_VIA_K8M800_NB_SB_CTR,
 208 };
 209
 210 static const struct pci_driver northbridge_driver_t890 __pci_driver = {
 211         .ops    = &ctrl_ops,
 212         .vendor = PCI_VENDOR_ID_VIA,
 213         .device = PCI_DEVICE_ID_VIA_K8T890CE_7,
 214 };
 215
 216 static const struct pci_driver northbridge_driver_t890cf __pci_driver = {
 217         .ops    = &ctrl_ops,
 218         .vendor = PCI_VENDOR_ID_VIA,
 219         .device = PCI_DEVICE_ID_VIA_K8T890CF_7,
 220 };
 221
 222 static const struct pci_driver northbridge_driver_m890 __pci_driver = {
 223         .ops    = &ctrl_ops,
 224         .vendor = PCI_VENDOR_ID_VIA,
 225         .device = PCI_DEVICE_ID_VIA_K8M890CE_7,
 226 };