2 * This file is part of the coreboot project.
4 * Copyright (C) 2010 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #include <console/console.h>
21 #include <device/device.h>
22 #include <device/pci.h>
24 #include <boot/tables.h>
25 #include <cpu/x86/msr.h>
26 #include <cpu/amd/mtrr.h>
27 #include <device/pci_def.h>
28 #include <southbridge/amd/sb700/sb700.h>
29 #include "southbridge/amd/sb700/smbus.h"
32 #define ADT7461_ADDRESS 0x4C
33 #define ARA_ADDRESS 0x0C /* Alert Response Address */
35 #define ADT7461_read_byte(address) \
36 do_smbus_read_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address)
37 #define ARA_read_byte(address) \
38 do_smbus_read_byte(SMBUS_IO_BASE, ARA_ADDRESS, address)
39 #define ADT7461_write_byte(address, val) \
40 do_smbus_write_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address, val)
42 uint64_t uma_memory_base, uma_memory_size;
44 void set_pcie_dereset(void);
45 void set_pcie_reset(void);
46 u8 is_dev3_present(void);
48 void set_pcie_dereset()
53 /* set 0 to bit1 :disable GPM9 as SLP_S2 output */
54 /* set 0 to bit2 :disable GPM8 as AZ_RST output */
55 byte = pm_ioread(0x8d);
56 byte &= ~((1 << 1) | (1 << 2));
57 pm_iowrite(0x8d, byte);
59 /* set the GPM8 and GPM9 output enable and the value to 1 */
60 byte = pm_ioread(0x94);
61 byte &= ~((1 << 2) | (1 << 3));
62 byte |= ((1 << 0) | (1 << 1));
63 pm_iowrite(0x94, byte);
65 /* set the GPIO65 output enable and the value is 1 */
66 sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
67 word = pci_read_config16(sm_dev, 0x7e);
70 pci_write_config16(sm_dev, 0x7e, word);
79 /* set 0 to bit1 :disable GPM9 as SLP_S2 output */
80 /* set 0 to bit2 :disable GPM8 as AZ_RST output */
81 byte = pm_ioread(0x8d);
82 byte &= ~((1 << 1) | (1 << 2));
83 pm_iowrite(0x8d, byte);
85 /* set the GPM8 and GPM9 output enable and the value to 0 */
86 byte = pm_ioread(0x94);
87 byte &= ~((1 << 2) | (1 << 3));
88 byte &= ~((1 << 0) | (1 << 1));
89 pm_iowrite(0x94, byte);
91 /* set the GPIO65 output enable and the value is 0 */
92 sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
93 word = pci_read_config16(sm_dev, 0x7e);
96 pci_write_config16(sm_dev, 0x7e, word);
100 /********************************************************
101 * tilapia uses SB700 GPIO8 to detect IDE_DMA66.
102 * IDE_DMA66 is routed to GPIO 8. So we read Gpio 8 to
103 * get the cable type, 40 pin or 80 pin?
104 ********************************************************/
105 static void get_ide_dma66(void)
108 /*u32 sm_dev, ide_dev; */
109 device_t sm_dev, ide_dev;
111 sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
113 byte = pci_read_config8(sm_dev, 0xA9);
114 byte |= (1 << 4); /* Set Gpio8 as input */
115 pci_write_config8(sm_dev, 0xA9, byte);
117 ide_dev = dev_find_slot(0, PCI_DEVFN(0x14, 1));
118 byte = pci_read_config8(ide_dev, 0x56);
120 if ((1 << 4) & pci_read_config8(sm_dev, 0xAA))
121 byte |= 2 << 0; /* mode 2 */
123 byte |= 5 << 0; /* mode 5 */
124 pci_write_config8(ide_dev, 0x56, byte);
129 * justify the dev3 is exist or not
131 u8 is_dev3_present(void)
136 /* access the smbus extended register */
137 sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
139 /* put the GPIO68 output to tristate */
140 word = pci_read_config16(sm_dev, 0x7e);
142 pci_write_config16(sm_dev, 0x7e,word);
144 /* read the GPIO68 input status */
145 word = pci_read_config16(sm_dev, 0x7e);
147 if(word & (1 << 10)){
160 static void set_gpio40_gfx(void)
165 /* disable the GPIO40 as CLKREQ2# function */
166 byte = pm_ioread(0xd3);
168 pm_iowrite(0xd3, byte);
170 /* disable the GPIO40 as CLKREQ3# function */
171 byte = pm_ioread(0xd4);
173 pm_iowrite(0xd4, byte);
175 /* enable pull up for GPIO68 */
176 byte = pm2_ioread(0xf1);
178 pm2_iowrite(0xf1, byte);
180 /* access the smbus extended register */
181 sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
183 /*if the dev3 is present, set the gfx to 2x8 lanes*/
184 /*otherwise set the gfx to 1x16 lanes*/
185 if(is_dev3_present()){
187 printk(BIOS_INFO, "Dev3 is present. GFX Configuration is Two x8 slots\n");
188 /* when the gpio40 is configured as GPIO, this will enable the output */
189 pci_write_config32(sm_dev, 0xf8, 0x4);
190 dword = pci_read_config32(sm_dev, 0xfc);
193 /* When the gpio40 is configured as GPIO, this will represent the output value*/
194 /* 1 :enable two x8 , 0 : master slot enable only */
196 pci_write_config32(sm_dev, 0xfc, dword);
199 printk(BIOS_INFO, "Dev3 is not present. GFX Configuration is One x16 slot\n");
200 /* when the gpio40 is configured as GPIO, this will enable the output */
201 pci_write_config32(sm_dev, 0xf8, 0x4);
202 dword = pci_read_config32(sm_dev, 0xfc);
205 /* When the gpio40 is configured as GPIO, this will represent the output value*/
206 /* 1 :enable two x8 , 0 : master slot enable only */
208 pci_write_config32(sm_dev, 0xfc, dword);
215 static void set_thermal_config(void)
222 ADT7461_write_byte(0x0B, 0x50); /* Local Temperature Hight limit */
223 ADT7461_write_byte(0x0C, 0x00); /* Local Temperature Low limit */
224 ADT7461_write_byte(0x0D, 0x50); /* External Temperature Hight limit High Byte */
225 ADT7461_write_byte(0x0E, 0x00); /* External Temperature Low limit High Byte */
227 ADT7461_write_byte(0x19, 0x55); /* External THERM limit */
228 ADT7461_write_byte(0x20, 0x55); /* Local THERM limit */
230 byte = ADT7461_read_byte(0x02); /* read status register to clear it */
231 ARA_read_byte(0x05); /* A hardware alert can only be cleared by the master sending an ARA as a read command */
232 printk(BIOS_INFO, "Init adt7461 end , status 0x02 %02x\n", byte);
234 /* sb700 settings for thermal config */
235 /* set SB700 GPIO 64 to GPIO with pull-up */
236 byte = pm2_ioread(0x42);
238 pm2_iowrite(0x42, byte);
240 /* set GPIO 64 to input */
241 sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
242 word = pci_read_config16(sm_dev, 0x56);
244 pci_write_config16(sm_dev, 0x56, word);
246 /* set GPIO 64 internal pull-up */
247 byte = pm2_ioread(0xf0);
249 pm2_iowrite(0xf0, byte);
251 /* set Talert to be active low */
252 byte = pm_ioread(0x67);
254 pm_iowrite(0x67, byte);
256 /* set Talert to generate ACPI event */
257 byte = pm_ioread(0x3c);
259 pm_iowrite(0x3c, byte);
262 /* byte = pm_ioread(0x68);
264 * pm_iowrite(0x68, byte);
266 * byte = pm_ioread(0x55);
268 * pm_iowrite(0x55, byte);
270 * byte = pm_ioread(0x67);
271 * byte &= ~( 1 << 6);
272 * pm_iowrite(0x67, byte);
276 /*************************************************
277 * enable the dedicated function in tilapia board.
278 * This function called early than rs780_enable.
279 *************************************************/
280 static void tilapia_enable(device_t dev)
282 printk(BIOS_INFO, "Mainboard TILAPIA Enable. dev=0x%p\n", dev);
284 #if (CONFIG_GFXUMA == 1)
287 /* TOP_MEM: the top of DRAM below 4G */
288 msr = rdmsr(TOP_MEM);
290 "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n",
291 __func__, msr.lo, msr.hi);
293 /* TOP_MEM2: the top of DRAM above 4G */
294 msr2 = rdmsr(TOP_MEM2);
296 "%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n",
297 __func__, msr2.lo, msr2.hi);
300 case 0x10000000: /* 256M system memory */
301 uma_memory_size = 0x4000000; /* 64M recommended UMA */
304 case 0x20000000: /* 512M system memory */
305 uma_memory_size = 0x8000000; /* 128M recommended UMA */
308 default: /* 1GB and above system memory */
309 uma_memory_size = 0x10000000; /* 256M recommended UMA */
313 uma_memory_base = msr.lo - uma_memory_size; /* TOP_MEM1 */
314 printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n",
315 __func__, uma_memory_size, uma_memory_base);
319 uma_memory_size = 0x8000000; /* 128M recommended UMA */
320 uma_memory_base = 0x38000000; /* 1GB system memory supposed */
324 /* get_ide_dma66(); */
325 set_thermal_config();
329 int add_mainboard_resources(struct lb_memory *mem)
331 /* UMA is removed from system memory in the northbridge code, but
332 * in some circumstances we want the memory mentioned as reserved.
334 #if (CONFIG_GFXUMA == 1)
335 printk(BIOS_INFO, "uma_memory_start=0x%llx, uma_memory_size=0x%llx \n",
336 uma_memory_base, uma_memory_size);
337 lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base,
343 struct chip_operations mainboard_ops = {
344 CHIP_NAME("AMD TILAPIA Mainboard")
345 .enable_dev = tilapia_enable,