src/northbridge/intel/i855/raminit.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2006 Jon Dufresne <jon.dufresne@gmail.com>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  19  */
  20
  21 #include <assert.h>
  22 #include <spd.h>
  23 #include <sdram_mode.h>
  24 #include <stdlib.h>
  25 #include <delay.h>
  26 #include "i855.h"
  27
  28 /*-----------------------------------------------------------------------------
  29 Macros and definitions:
  30 -----------------------------------------------------------------------------*/
  31
  32 #define VALIDATE_DIMM_COMPATIBILITY
  33
  34 /* Debugging macros. */
  35 #if CONFIG_DEBUG_RAM_SETUP
  36 #define PRINTK_DEBUG(x...)      printk(BIOS_DEBUG, x)
  37 #define DUMPNORTH()             dump_pci_device(NORTHBRIDGE_MMC)
  38 #else
  39 #define PRINTK_DEBUG(x...)
  40 #define DUMPNORTH()
  41 #endif
  42
  43 #define delay() udelay(200)
  44
  45 #define VG85X_MODE (SDRAM_BURST_4 | SDRAM_BURST_INTERLEAVED | SDRAM_CAS_2_5)
  46
  47 /* DRC[10:8] - Refresh Mode Select (RMS).
  48  * 0x0 for Refresh Disabled (Self Refresh)
  49  * 0x1 for Refresh interval 15.6 us for 133MHz
  50  * 0x2 for Refresh interval 7.8 us for 133MHz
  51  * 0x7 for Refresh interval 64 Clocks. (Fast Refresh Mode)
  52  */
  53 #define RAM_COMMAND_REFRESH             0x1
  54
  55 /* DRC[6:4] - SDRAM Mode Select (SMS). */
  56 #define RAM_COMMAND_SELF_REFRESH        0x0
  57 #define RAM_COMMAND_NOP                 0x1
  58 #define RAM_COMMAND_PRECHARGE           0x2
  59 #define RAM_COMMAND_MRS                 0x3
  60 #define RAM_COMMAND_EMRS                0x4
  61 #define RAM_COMMAND_CBR                 0x6
  62 #define RAM_COMMAND_NORMAL              0x7
  63
  64 /* DRC[29] - Initialization Complete (IC). */
  65 #define RAM_COMMAND_IC                  0x1
  66
  67 struct dimm_size {
  68         unsigned int side1;
  69         unsigned int side2;
  70 };
  71
  72 static const uint32_t refresh_frequency[] = {
  73         /* Relative frequency (array value) of each E7501 Refresh Mode Select
  74          * (RMS) value (array index)
  75          * 0 == least frequent refresh (longest interval between refreshes)
  76          * [0] disabled  -> 0
  77          * [1] 15.6 usec -> 2
  78          * [2]  7.8 usec -> 3
  79          * [3] 64   usec -> 1
  80          * [4] reserved  -> 0
  81          * [5] reserved  -> 0
  82          * [6] reserved  -> 0
  83          * [7] 64 clocks -> 4
  84          */
  85         0, 2, 3, 1, 0, 0, 0, 4
  86 };
  87
  88 static const uint32_t refresh_rate_map[] = {
  89         /* Map the JEDEC spd refresh rates (array index) to i855 Refresh Mode
  90          * Select values (array value)
  91          * These are all the rates defined by JESD21-C Appendix D, Rev. 1.0
  92          * The i855 supports only 15.6 us (1), 7.8 us (2) and
  93          * 64 clock (481 ns) (7) refresh.
  94          * [0] ==  15.625 us -> 15.6 us
  95          * [1] ==   3.9   us -> 481  ns
  96          * [2] ==   7.8   us ->  7.8 us
  97          * [3] ==  31.3   us -> 15.6 us
  98          * [4] ==  62.5   us -> 15.6 us
  99          * [5] == 125     us -> 15.6 us
 100          */
 101         1, 7, 2, 1, 1, 1
 102 };
 103
 104 #define MAX_SPD_REFRESH_RATE ((sizeof(refresh_rate_map) / sizeof(uint32_t)) - 1)
 105
 106 /*-----------------------------------------------------------------------------
 107 SPD functions:
 108 -----------------------------------------------------------------------------*/
 109
 110 static void die_on_spd_error(int spd_return_value)
 111 {
 112         if (spd_return_value < 0)
 113                 PRINTK_DEBUG("Error reading SPD info: got %d\n", spd_return_value);
 114 /*
 115         if (spd_return_value < 0)
 116                 die("Error reading SPD info\n");
 117 */
 118 }
 119
 120 /**
 121  * Calculate the page size for each physical bank of the DIMM:
 122  *
 123  *   log2(page size) = (# columns) + log2(data width)
 124  *
 125  * NOTE: Page size is the total number of data bits in a row.
 126  *
 127  * @param dimm_socket_address SMBus address of DIMM socket to interrogate.
 128  * @return log2(page size) for each side of the DIMM.
 129  */
 130 static struct dimm_size sdram_spd_get_page_size(u8 dimm_socket_address)
 131 {
 132         uint16_t module_data_width;
 133         int value;
 134         struct dimm_size pgsz;
 135
 136         pgsz.side1 = 0;
 137         pgsz.side2 = 0;
 138
 139         // Side 1
 140         value = spd_read_byte(dimm_socket_address, SPD_NUM_COLUMNS);
 141         die_on_spd_error(value);
 142
 143         pgsz.side1 = value & 0xf;       // # columns in bank 1
 144
 145         /* Get the module data width and convert it to a power of two */
 146         value = spd_read_byte(dimm_socket_address, SPD_MODULE_DATA_WIDTH_MSB);
 147         die_on_spd_error(value);
 148
 149         module_data_width = (value & 0xff) << 8;
 150
 151         value = spd_read_byte(dimm_socket_address, SPD_MODULE_DATA_WIDTH_LSB);
 152         die_on_spd_error(value);
 153
 154         module_data_width |= (value & 0xff);
 155
 156         pgsz.side1 += log2(module_data_width);
 157
 158         /* side two */
 159         value = spd_read_byte(dimm_socket_address, SPD_NUM_DIMM_BANKS);
 160         die_on_spd_error(value);
 161
 162 /*
 163         if (value > 2)
 164                 die("Bad SPD value\n");
 165 */
 166         if (value > 2)
 167                 PRINTK_DEBUG("Bad SPD value\n");
 168
 169         if (value == 2) {
 170                 pgsz.side2 = pgsz.side1;        // Assume symmetric banks until we know differently
 171                 value = spd_read_byte(dimm_socket_address, SPD_NUM_COLUMNS);
 172                 die_on_spd_error(value);
 173
 174                 if ((value & 0xf0) != 0) {
 175                         // Asymmetric banks
 176                         pgsz.side2 -= value & 0xf;      /* Subtract out columns on side 1 */
 177                         pgsz.side2 += (value >> 4) & 0xf;       /* Add in columns on side 2 */
 178                 }
 179         }
 180
 181         return pgsz;
 182 }
 183
 184 /**
 185  * Read the width in bits of each DIMM side's DRAMs via SPD (i.e. 4, 8, 16).
 186  *
 187  * @param dimm_socket_address SMBus address of DIMM socket to interrogate.
 188  * @return Width in bits of each DIMM side's DRAMs.
 189  */
 190 static struct dimm_size sdram_spd_get_width(u8 dimm_socket_address)
 191 {
 192         int value;
 193         struct dimm_size width;
 194
 195         width.side1 = 0;
 196         width.side2 = 0;
 197
 198         value = spd_read_byte(dimm_socket_address, SPD_PRIMARY_SDRAM_WIDTH);
 199         die_on_spd_error(value);
 200
 201         width.side1 = value & 0x7f;     // Mask off bank 2 flag
 202
 203         if (value & 0x80) {
 204                 width.side2 = width.side1 << 1; // Bank 2 exists and is double-width
 205         } else {
 206                 // If bank 2 exists, it's the same width as bank 1
 207                 value = spd_read_byte(dimm_socket_address, SPD_NUM_DIMM_BANKS);
 208                 die_on_spd_error(value);
 209
 210 #ifdef ROMCC_IF_BUG_FIXED
 211                 if (value == 2)
 212                         width.side2 = width.side1;
 213 #else
 214                 switch (value) {
 215                 case 2:
 216                         width.side2 = width.side1;
 217                         break;
 218
 219                 default:
 220                         break;
 221                 }
 222 #endif
 223         }
 224
 225         return width;
 226 }
 227
 228 /**
 229  * Calculate the log base 2 size in bits of both DIMM sides.
 230  *
 231  * log2(# bits) = (# columns) + log2(data width) +
 232  *                (# rows) + log2(banks per SDRAM)
 233  *
 234  * Note that it might be easier to use SPD byte 31 here, it has the DIMM size
 235  * as a multiple of 4MB. The way we do it now we can size both sides of an
 236  * asymmetric DIMM.
 237  *
 238  * @param dimm SMBus address of DIMM socket to interrogate.
 239  * @return log2(number of bits) for each side of the DIMM.
 240  */
 241 static struct dimm_size spd_get_dimm_size(unsigned dimm)
 242 {
 243         int value;
 244
 245         // Start with log2(page size)
 246         struct dimm_size sz = sdram_spd_get_page_size(dimm);
 247
 248         if (sz.side1 > 0) {
 249                 value = spd_read_byte(dimm, SPD_NUM_ROWS);
 250                 die_on_spd_error(value);
 251
 252                 sz.side1 += value & 0xf;
 253
 254                 if (sz.side2 > 0) {
 255                         // Double-sided DIMM
 256                         if (value & 0xF0)
 257                                 sz.side2 += value >> 4; // Asymmetric
 258                         else
 259                                 sz.side2 += value;      // Symmetric
 260                 }
 261
 262                 value = spd_read_byte(dimm, SPD_NUM_BANKS_PER_SDRAM);
 263                 die_on_spd_error(value);
 264
 265                 value = log2(value);
 266                 sz.side1 += value;
 267                 if (sz.side2 > 0)
 268                         sz.side2 += value;
 269         }
 270
 271         return sz;
 272 }
 273
 274 /**
 275  * Scan for compatible DIMMs.
 276  *
 277  * @return A bitmask indicating which sockets contain a compatible DIMM.
 278  */
 279 static uint8_t spd_get_supported_dimms(void)
 280 {
 281         int i;
 282         uint8_t dimm_mask = 0;
 283
 284         for (i = 0; i < DIMM_SOCKETS; i++) {
 285                 u8 dimm = DIMM0 + i;
 286
 287 #ifdef VALIDATE_DIMM_COMPATIBILITY
 288                 struct dimm_size page_size;
 289                 struct dimm_size sdram_width;
 290 #endif
 291                 int spd_value;
 292
 293                 if (dimm == 0)
 294                         continue;       // No such socket on this mainboard
 295
 296                 if (spd_read_byte(dimm, SPD_MEMORY_TYPE) != SPD_MEMORY_TYPE_SDRAM_DDR)
 297                         continue;
 298
 299 #ifdef VALIDATE_DIMM_COMPATIBILITY
 300                 if ((spd_value = spd_read_byte(dimm, SPD_MODULE_VOLTAGE)) != SPD_VOLTAGE_SSTL2) {
 301                         PRINTK_DEBUG("Skipping DIMM with unsupported voltage: %02x\n", spd_value);
 302                         continue;       // Unsupported voltage
 303                 }
 304
 305 /*
 306                 // E7501 does not support unregistered DIMMs
 307                 spd_value = spd_read_byte(dimm, SPD_MODULE_ATTRIBUTES);
 308                 if (!(spd_value & MODULE_REGISTERED) || (spd_value < 0)) {
 309                         PRINTK_DEBUG("Skipping unregistered DIMM: %02x\n", spd_value);
 310                         continue;
 311                 }
 312 */
 313
 314                 page_size = sdram_spd_get_page_size(dimm);
 315                 sdram_width = sdram_spd_get_width(dimm);
 316
 317                 // Validate DIMM page size
 318                 // The i855 only supports page sizes of 4, 8, 16 KB per channel
 319                 // NOTE:  4 KB =  32 Kb = 2^15
 320                 //       16 KB = 128 Kb = 2^17
 321
 322                 if ((page_size.side1 < 15) || (page_size.side1 > 17)) {
 323                         PRINTK_DEBUG("Skipping DIMM with unsupported page size: %d\n", page_size.side1);
 324                         continue;
 325                 }
 326
 327                 // If DIMM is double-sided, verify side2 page size
 328                 if (page_size.side2 != 0) {
 329                         if ((page_size.side2 < 15) || (page_size.side2 > 17)) {
 330                                 PRINTK_DEBUG("Skipping DIMM with unsupported page size: %d\n", page_size.side2);
 331                                 continue;
 332                         }
 333                 }
 334                 // Validate SDRAM width
 335                 // The i855 only supports x8 and x16 devices
 336                 if ((sdram_width.side1 != 8) && (sdram_width.side1 != 16)) {
 337                         PRINTK_DEBUG("Skipping DIMM with unsupported width: %d\n", sdram_width.side2);
 338                         continue;
 339                 }
 340
 341                 // If DIMM is double-sided, verify side2 width
 342                 if (sdram_width.side2 != 0) {
 343                         if ((sdram_width.side2 != 8)
 344                             && (sdram_width.side2 != 16)) {
 345                                 PRINTK_DEBUG("Skipping DIMM with unsupported width: %d\n", sdram_width.side2);
 346                                 continue;
 347                         }
 348                 }
 349 #endif
 350                 // Made it through all the checks, this DIMM is usable
 351                 dimm_mask |= (1 << i);
 352         }
 353
 354         return dimm_mask;
 355 }
 356
 357 /*-----------------------------------------------------------------------------
 358 SDRAM configuration functions:
 359 -----------------------------------------------------------------------------*/
 360
 361 static void do_ram_command(uint8_t command, uint16_t jedec_mode_bits)
 362 {
 363         int i;
 364         u32 reg32;
 365         uint8_t dimm_start_32M_multiple = 0;
 366         uint16_t i855_mode_bits = jedec_mode_bits;
 367
 368         /* Configure the RAM command. */
 369         reg32 = pci_read_config32(NORTHBRIDGE_MMC, DRC);
 370         reg32 &= ~(7 << 4);
 371         reg32 |= (command << 4);
 372         PRINTK_DEBUG("  Sending RAM command 0x%08x\n", reg32);
 373         pci_write_config32(NORTHBRIDGE_MMC, DRC, reg32);
 374
 375         // RAM_COMMAND_NORMAL is an exception.
 376         // It affects only the memory controller and does not need to be "sent" to the DIMMs.
 377
 378         if (command != RAM_COMMAND_NORMAL) {
 379
 380                 // Send the command to all DIMMs by accessing a memory location within each
 381                 // NOTE: for mode select commands, some of the location address bits
 382                 // are part of the command
 383
 384                 // Map JEDEC mode bits to i855
 385                 if (command == RAM_COMMAND_MRS || command == RAM_COMMAND_EMRS) {
 386                         /* Host address lines [13:3] map to DIMM address lines [11, 9:0] */
 387                         i855_mode_bits = ((jedec_mode_bits & 0x800) << (13 - 11)) | ((jedec_mode_bits & 0x3ff) << (12 - 9));
 388                 }
 389
 390                 for (i = 0; i < (DIMM_SOCKETS * 2); ++i) {
 391                         uint8_t dimm_end_32M_multiple = pci_read_config8(NORTHBRIDGE_MMC, DRB + i);
 392                         if (dimm_end_32M_multiple > dimm_start_32M_multiple) {
 393
 394                                 uint32_t dimm_start_address = dimm_start_32M_multiple << 25;
 395                                 PRINTK_DEBUG("  Sending RAM command to 0x%08x\n", dimm_start_address + i855_mode_bits);
 396                                 read32(dimm_start_address + i855_mode_bits);
 397
 398                                 // Set the start of the next DIMM
 399                                 dimm_start_32M_multiple = dimm_end_32M_multiple;
 400                         }
 401                 }
 402         }
 403 }
 404
 405 static void set_initialize_complete(void)
 406 {
 407         uint32_t drc_reg;
 408
 409         drc_reg = pci_read_config32(NORTHBRIDGE_MMC, DRC);
 410         drc_reg |= (1 << 29);
 411         pci_write_config32(NORTHBRIDGE_MMC, DRC, drc_reg);
 412 }
 413
 414 static void sdram_enable(void)
 415 {
 416         int i;
 417
 418         print_debug("Ram enable 1\n");
 419         delay();
 420         delay();
 421
 422         /* NOP command */
 423         PRINTK_DEBUG(" NOP\n");
 424         do_ram_command(RAM_COMMAND_NOP, 0);
 425         delay();
 426         delay();
 427         delay();
 428
 429         /* Pre-charge all banks (at least 200 us after NOP) */
 430         PRINTK_DEBUG(" Pre-charging all banks\n");
 431         do_ram_command(RAM_COMMAND_PRECHARGE, 0);
 432         delay();
 433         delay();
 434         delay();
 435
 436         print_debug("Ram enable 4\n");
 437         do_ram_command(RAM_COMMAND_EMRS, SDRAM_EXTMODE_DLL_ENABLE);
 438         delay();
 439         delay();
 440         delay();
 441
 442         print_debug("Ram enable 5\n");
 443         do_ram_command(RAM_COMMAND_MRS, VG85X_MODE | SDRAM_MODE_DLL_RESET);
 444
 445         print_debug("Ram enable 6\n");
 446         do_ram_command(RAM_COMMAND_PRECHARGE, 0);
 447         delay();
 448         delay();
 449         delay();
 450
 451         /* 8 CBR refreshes (Auto Refresh) */
 452         PRINTK_DEBUG(" 8 CBR refreshes\n");
 453         for(i = 0; i < 8; i++) {
 454                 do_ram_command(RAM_COMMAND_CBR, 0);
 455                 delay();
 456                 delay();
 457                 delay();
 458         }
 459
 460         print_debug("Ram enable 8\n");
 461         do_ram_command(RAM_COMMAND_MRS, VG85X_MODE | SDRAM_MODE_NORMAL);
 462
 463         /* Set GME-M Mode Select bits back to NORMAL operation mode */
 464         PRINTK_DEBUG(" Normal operation mode\n");
 465         do_ram_command(RAM_COMMAND_NORMAL, 0);
 466         delay();
 467         delay();
 468         delay();
 469
 470         print_debug("Ram enable 9\n");
 471         set_initialize_complete();
 472
 473         delay();
 474         delay();
 475         delay();
 476         delay();
 477         delay();
 478
 479         print_debug("After configuration:\n");
 480         /* dump_pci_devices(); */
 481
 482         /*
 483         print_debug("\n\n***** RAM TEST *****\n");
 484         ram_check(0, 0xa0000);
 485         ram_check(0x100000, 0x40000000);
 486         */
 487 }
 488
 489 /*-----------------------------------------------------------------------------
 490 DIMM-independant configuration functions:
 491 -----------------------------------------------------------------------------*/
 492
 493 /**
 494  * Set only what I need until it works, then make it figure things out on boot
 495  * assumes only one DIMM is populated.
 496  */
 497 static void sdram_set_registers(void)
 498 {
 499         /*
 500         print_debug("Before configuration:\n");
 501         dump_pci_devices();
 502         */
 503 }
 504
 505 static void spd_set_row_attributes(uint8_t dimm_mask)
 506 {
 507         int i;
 508         uint16_t row_attributes = 0;
 509
 510         for (i = 0; i < DIMM_SOCKETS; i++) {
 511                 u8 dimm = DIMM0 + i;
 512                 struct dimm_size page_size;
 513                 struct dimm_size sdram_width;
 514
 515                 if (!(dimm_mask & (1 << i))) {
 516                         row_attributes |= 0x77 << (i << 3);
 517                         continue;       // This DIMM not usable
 518                 }
 519
 520                 // Get the relevant parameters via SPD
 521                 page_size = sdram_spd_get_page_size(dimm);
 522                 sdram_width = sdram_spd_get_width(dimm);
 523
 524                 // Update the DRAM Row Attributes.
 525                 // Page size is encoded as log2(page size in bits) - log2(2 KB) or 4 KB == 1, 8 KB == 3, 16KB == 3
 526                 // NOTE:  2 KB =  16 Kb = 2^14
 527                 row_attributes |= (page_size.side1 - 14) << (i << 3);   // Side 1 of each DIMM is an EVEN row
 528
 529                 if (sdram_width.side2 > 0)
 530                         row_attributes |= (page_size.side2 - 14) << ((i << 3) + 4);     // Side 2 is ODD
 531                 else
 532                         row_attributes |= 7 << ((i << 3) + 4);
 533                 /* go to the next DIMM */
 534         }
 535
 536         PRINTK_DEBUG("DRA: %04x\n", row_attributes);
 537
 538         /* Write the new row attributes register */
 539         pci_write_config16(NORTHBRIDGE_MMC, DRA, row_attributes);
 540 }
 541
 542 static void spd_set_dram_controller_mode(uint8_t dimm_mask)
 543 {
 544         int i;
 545
 546         // Initial settings
 547         u32 controller_mode = pci_read_config32(NORTHBRIDGE_MMC, DRC);
 548         u32 system_refresh_mode = (controller_mode >> 7) & 7;
 549
 550         controller_mode |= (1 << 20);  // ECC
 551         controller_mode |= (1 << 15);  // RAS lockout
 552         controller_mode |= (1 << 12);  // Address Tri-state enable (ADRTRIEN), FIXME: how is this detected?????
 553         controller_mode |= (2 << 10);  // FIXME: Undocumented, really needed?????
 554
 555         for (i = 0; i < DIMM_SOCKETS; i++) {
 556                 u8 dimm = DIMM0 + i;
 557                 uint32_t dimm_refresh_mode;
 558                 int value;
 559                 u8 tRCD, tRP;
 560
 561                 if (!(dimm_mask & (1 << i))) {
 562                         continue;       // This DIMM not usable
 563                 }
 564
 565                 // Disable ECC mode if any one of the DIMMs does not support ECC
 566                 value = spd_read_byte(dimm, SPD_DIMM_CONFIG_TYPE);
 567                 die_on_spd_error(value);
 568                 if (value != ERROR_SCHEME_ECC)
 569                         controller_mode &= ~(3 << 20);
 570
 571                 value = spd_read_byte(dimm, SPD_REFRESH);
 572                 die_on_spd_error(value);
 573                 value &= 0x7f;  // Mask off self-refresh bit
 574                 if (value > MAX_SPD_REFRESH_RATE) {
 575                         print_err("unsupported refresh rate\n");
 576                         continue;
 577                 }
 578                 // Get the appropriate i855 refresh mode for this DIMM
 579                 dimm_refresh_mode = refresh_rate_map[value];
 580                 if (dimm_refresh_mode > 7) {
 581                         print_err("unsupported refresh rate\n");
 582                         continue;
 583                 }
 584                 // If this DIMM requires more frequent refresh than others,
 585                 // update the system setting
 586                 if (refresh_frequency[dimm_refresh_mode] >
 587                     refresh_frequency[system_refresh_mode])
 588                         system_refresh_mode = dimm_refresh_mode;
 589
 590                 /* FIXME: is this correct? */
 591                 tRCD = spd_read_byte(dimm, SPD_tRCD);
 592                 tRP = spd_read_byte(dimm, SPD_tRP);
 593                 if (tRCD != tRP) {
 594                         PRINTK_DEBUG(" Disabling RAS lockouk due to tRCD (%d) != tRP (%d)\n", tRCD, tRP);
 595                         controller_mode &= ~(1 << 15);
 596                 }
 597
 598                 /* go to the next DIMM */
 599         }
 600
 601         controller_mode &= ~(7 << 7);
 602         controller_mode |= (system_refresh_mode << 7);
 603         PRINTK_DEBUG("DRC: %08x\n", controller_mode);
 604
 605         pci_write_config32(NORTHBRIDGE_MMC, DRC, controller_mode);
 606 }
 607
 608 static void spd_set_dram_timing(uint8_t dimm_mask)
 609 {
 610         int i;
 611         u32 dram_timing;
 612
 613         // CAS# latency bitmasks in SPD_ACCEPTABLE_CAS_LATENCIES format
 614         // NOTE: i82822 supports only 2.0 and 2.5
 615         uint32_t system_compatible_cas_latencies = SPD_CAS_LATENCY_2_0 | SPD_CAS_LATENCY_2_5;
 616         uint8_t slowest_row_precharge = 0;
 617         uint8_t slowest_ras_cas_delay = 0;
 618         uint8_t slowest_active_to_precharge_delay = 0;
 619
 620         for (i = 0; i < DIMM_SOCKETS; i++) {
 621                 u8 dimm = DIMM0 + i;
 622                 int value;
 623                 uint32_t current_cas_latency;
 624                 uint32_t dimm_compatible_cas_latencies;
 625                 if (!(dimm_mask & (1 << i)))
 626                         continue;       // This DIMM not usable
 627
 628                 value = spd_read_byte(dimm, SPD_ACCEPTABLE_CAS_LATENCIES);
 629                 PRINTK_DEBUG("SPD_ACCEPTABLE_CAS_LATENCIES: %d\n", value);
 630                 die_on_spd_error(value);
 631
 632                 dimm_compatible_cas_latencies = value & 0x7f;   // Start with all supported by DIMM
 633                 PRINTK_DEBUG("dimm_compatible_cas_latencies #1: %d\n", dimm_compatible_cas_latencies);
 634
 635                 current_cas_latency = 1 << log2(dimm_compatible_cas_latencies); // Max supported by DIMM
 636                 PRINTK_DEBUG("current_cas_latency: %d\n", current_cas_latency);
 637
 638                 // Can we support the highest CAS# latency?
 639                 value = spd_read_byte(dimm, SPD_MIN_CYCLE_TIME_AT_CAS_MAX);
 640                 die_on_spd_error(value);
 641                 PRINTK_DEBUG("SPD_MIN_CYCLE_TIME_AT_CAS_MAX: %d.%d\n", value >> 4, value & 0xf);
 642
 643                 // NOTE: At 133 MHz, 1 clock == 7.52 ns
 644                 if (value > 0x75) {
 645                         // Our bus is too fast for this CAS# latency
 646                         // Remove it from the bitmask of those supported by the DIMM that are compatible
 647                         dimm_compatible_cas_latencies &= ~current_cas_latency;
 648                         PRINTK_DEBUG("dimm_compatible_cas_latencies #2: %d\n", dimm_compatible_cas_latencies);
 649                 }
 650                 // Can we support the next-highest CAS# latency (max - 0.5)?
 651
 652                 current_cas_latency >>= 1;
 653                 if (current_cas_latency != 0) {
 654                         value = spd_read_byte(dimm, SPD_SDRAM_CYCLE_TIME_2ND);
 655                         die_on_spd_error(value);
 656                         PRINTK_DEBUG("SPD_SDRAM_CYCLE_TIME_2ND: %d.%d\n", value >> 4, value & 0xf);
 657                         if (value > 0x75) {
 658                                 dimm_compatible_cas_latencies &= ~current_cas_latency;
 659                                 PRINTK_DEBUG("dimm_compatible_cas_latencies #2: %d\n", dimm_compatible_cas_latencies);
 660                         }
 661                 }
 662                 // Can we support the next-highest CAS# latency (max - 1.0)?
 663                 current_cas_latency >>= 1;
 664                 if (current_cas_latency != 0) {
 665                         value = spd_read_byte(dimm, SPD_SDRAM_CYCLE_TIME_3RD);
 666                         PRINTK_DEBUG("SPD_SDRAM_CYCLE_TIME_3RD: %d.%d\n", value >> 4, value & 0xf);
 667                         die_on_spd_error(value);
 668                         if (value > 0x75) {
 669                                 dimm_compatible_cas_latencies &= ~current_cas_latency;
 670                                 PRINTK_DEBUG("dimm_compatible_cas_latencies #2: %d\n", dimm_compatible_cas_latencies);
 671                         }
 672                 }
 673                 // Restrict the system to CAS# latencies compatible with this DIMM
 674                 system_compatible_cas_latencies &= dimm_compatible_cas_latencies;
 675
 676                 value = spd_read_byte(dimm, SPD_MIN_ROW_PRECHARGE_TIME);
 677                 die_on_spd_error(value);
 678                 if (value > slowest_row_precharge)
 679                         slowest_row_precharge = value;
 680
 681                 value = spd_read_byte(dimm, SPD_MIN_RAS_TO_CAS_DELAY);
 682                 die_on_spd_error(value);
 683                 if (value > slowest_ras_cas_delay)
 684                         slowest_ras_cas_delay = value;
 685
 686                 value = spd_read_byte(dimm, SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY);
 687                 die_on_spd_error(value);
 688                 if (value > slowest_active_to_precharge_delay)
 689                         slowest_active_to_precharge_delay = value;
 690
 691                 /* go to the next DIMM */
 692         }
 693         PRINTK_DEBUG("CAS latency: %d\n", system_compatible_cas_latencies);
 694
 695         dram_timing = pci_read_config32(NORTHBRIDGE_MMC, DRT);
 696         dram_timing &= ~(DRT_CAS_MASK | DRT_TRP_MASK | DRT_RCD_MASK);
 697         PRINTK_DEBUG("DRT: %08x\n", dram_timing);
 698
 699         if (system_compatible_cas_latencies & SPD_CAS_LATENCY_2_0) {
 700                 dram_timing |= DRT_CAS_2_0;
 701         } else if (system_compatible_cas_latencies & SPD_CAS_LATENCY_2_5) {
 702                 dram_timing |= DRT_CAS_2_5;
 703         } else
 704                 die("No CAS# latencies compatible with all DIMMs!!\n");
 705
 706         uint32_t current_cas_latency = dram_timing & DRT_CAS_MASK;
 707
 708         /* tRP */
 709
 710         PRINTK_DEBUG("slowest_row_precharge: %d.%d\n", slowest_row_precharge >> 2, slowest_row_precharge & 0x3);
 711         // i855 supports only 2, 3 or 4 clocks for tRP
 712         if (slowest_row_precharge > ((30 << 2)))
 713                 die("unsupported DIMM tRP");    //  > 30.0 ns: 5 or more clocks
 714         else if (slowest_row_precharge > ((22 << 2) | (2 << 0)))
 715                 dram_timing |= DRT_TRP_4;       //  > 22.5 ns: 4 or more clocks
 716         else if (slowest_row_precharge > (15 << 2))
 717                 dram_timing |= DRT_TRP_3;       //  > 15.0 ns: 3 clocks
 718         else
 719                 dram_timing |= DRT_TRP_2;       // <= 15.0 ns: 2 clocks
 720
 721         /*  tRCD */
 722
 723         PRINTK_DEBUG("slowest_ras_cas_delay: %d.%d\n", slowest_ras_cas_delay >> 2, slowest_ras_cas_delay & 0x3);
 724         // i855 supports only 2, 3 or 4 clocks for tRCD
 725         if (slowest_ras_cas_delay > ((30 << 2)))
 726                 die("unsupported DIMM tRCD");   //  > 30.0 ns: 5 or more clocks
 727         else if (slowest_ras_cas_delay > ((22 << 2) | (2 << 0)))
 728                 dram_timing |= DRT_RCD_4;       //  > 22.5 ns: 4 or more clocks
 729         else if (slowest_ras_cas_delay > (15 << 2))
 730                 dram_timing |= DRT_RCD_3;       //  > 15.0 ns: 3 clocks
 731         else
 732                 dram_timing |= DRT_RCD_2;       // <= 15.0 ns: 2 clocks
 733
 734         /* tRAS, min */
 735
 736         PRINTK_DEBUG("slowest_active_to_precharge_delay: %d\n", slowest_active_to_precharge_delay);
 737         // i855 supports only 5, 6, 7 or 8 clocks for tRAS
 738         // 5 clocks ~= 37.6 ns, 6 clocks ~= 45.1 ns, 7 clocks ~= 52.6 ns, 8 clocks ~= 60.1 ns
 739         if (slowest_active_to_precharge_delay > 60)
 740                 die("unsupported DIMM tRAS");   // > 52 ns:      8 or more clocks
 741         else if (slowest_active_to_precharge_delay > 52)
 742                 dram_timing |= DRT_TRAS_MIN_8;  // 46-52 ns:     7 clocks
 743         else if (slowest_active_to_precharge_delay > 45)
 744                 dram_timing |= DRT_TRAS_MIN_7;  // 46-52 ns:     7 clocks
 745         else if (slowest_active_to_precharge_delay > 37)
 746                 dram_timing |= DRT_TRAS_MIN_6;  // 38-45 ns:     6 clocks
 747         else
 748                 dram_timing |= DRT_TRAS_MIN_5;  // < 38 ns:      5 clocks
 749
 750         /* FIXME: guess work starts here...
 751          *
 752          * Intel refers to DQ turn-arround values for back to calculate the values,
 753          * but i have no idea what this means
 754          */
 755
 756         /*
 757          * Back to Back Read-Write command spacing (DDR, different Rows/Bank)
 758          */
 759         /* Set to a 3 clock back to back read to write turn around.
 760          *  2 is a good delay if the CAS latency is 2.0 */
 761         dram_timing &= ~(3 << 28);
 762         if (current_cas_latency == DRT_CAS_2_0)
 763                 dram_timing |= (2 << 28);       // 2 clocks
 764         else
 765                 dram_timing |= (1 << 28);       // 3 clocks
 766
 767         /*
 768          * Back to Back Read-Write command spacing (DDR, same or different Rows/Bank)
 769          */
 770         dram_timing &= ~(3 << 26);
 771         if (current_cas_latency == DRT_CAS_2_0)
 772                 dram_timing |= (2 << 26);       // 5 clocks
 773         else
 774                 dram_timing |= (1 << 26);       // 6 clocks
 775
 776         /*
 777          * Back To Back Read-Read commands spacing (DDR, different Rows):
 778          */
 779         dram_timing &= ~(1 << 25);
 780         dram_timing |= (1 << 25);       // 3 clocks
 781
 782         PRINTK_DEBUG("DRT: %08x\n", dram_timing);
 783         pci_write_config32(NORTHBRIDGE_MMC, DRT, dram_timing);
 784 }
 785
 786 static void spd_set_dram_size(uint8_t dimm_mask)
 787 {
 788         int i;
 789         int total_dram = 0;
 790         uint32_t drb_reg = 0;
 791
 792         for (i = 0; i < DIMM_SOCKETS; i++) {
 793                 u8 dimm = DIMM0 + i;
 794                 struct dimm_size sz;
 795
 796                 if (!(dimm_mask & (1 << i))) {
 797                         /* fill values even for not present DIMMs */
 798                         drb_reg |= (total_dram << (i * 16));
 799                         drb_reg |= (total_dram << ((i * 16) + 8));
 800
 801                         continue;       // This DIMM not usable
 802                 }
 803                 sz = spd_get_dimm_size(dimm);
 804
 805                 total_dram += (1 << (sz.side1 - 28));
 806                 drb_reg |= (total_dram << (i * 16));
 807
 808                 total_dram += (1 << (sz.side2 - 28));
 809                 drb_reg |= (total_dram << ((i * 16) + 8));
 810         }
 811         PRINTK_DEBUG("DRB: %08x\n", drb_reg);
 812         pci_write_config32(NORTHBRIDGE_MMC, DRB, drb_reg);
 813 }
 814
 815
 816 static void spd_set_dram_pwr_management(void)
 817 {
 818         uint32_t pwrmg_reg;
 819
 820         pwrmg_reg = 0x10f10430;
 821         pci_write_config32(NORTHBRIDGE_MMC, PWRMG, pwrmg_reg);
 822 }
 823
 824 static void spd_set_dram_throttle_control(void)
 825 {
 826         uint32_t dtc_reg = 0;
 827
 828         /* DDR SDRAM Throttle Mode (TMODE):
 829          *   0011 = Both Rank and GMCH Thermal Sensor based throttling is enabled. When the external SO-
 830          *          DIMM Thermal Sensor is Tripped DDR SDRAM Throttling begins based on the setting in RTT
 831          */
 832         dtc_reg |= (3 << 28);
 833
 834         /* Read Counter Based Power Throttle Control (RCTC):
 835          *   0 = 85%
 836          */
 837         dtc_reg |= (0 << 24);
 838
 839         /* Write Counter Based Power Throttle Control (WCTC):
 840          *   0 = 85%
 841          */
 842         dtc_reg |= (0 << 20);
 843
 844         /* Read Thermal Based Power Throttle Control (RTTC):
 845          *   0xA = 20%
 846          */
 847         dtc_reg |= (0xA << 16);
 848
 849         /* Write Thermal Based Power Throttle Control (WTTC):
 850          *   0xA = 20%
 851          */
 852         dtc_reg |= (0xA << 12);
 853
 854         /* Counter Based Throttle Lock (CTLOCK): */
 855         dtc_reg |= (0 << 11);
 856
 857         /* Thermal Throttle Lock (TTLOCK): */
 858         dtc_reg |= (0 << 10);
 859
 860         /* Thermal Power Throttle Control fields Enable: */
 861         dtc_reg |= (1 << 9);
 862
 863         /* High Priority Stream Throttling Enable: */
 864         dtc_reg |= (0 << 8);
 865
 866         /* Global DDR SDRAM Sampling Window (GDSW): */
 867         dtc_reg |= 0xff;
 868         PRINTK_DEBUG("DTC: %08x\n", dtc_reg);
 869         pci_write_config32(NORTHBRIDGE_MMC, DTC, dtc_reg);
 870 }
 871
 872 static void spd_update(u8 reg, u32 new_value)
 873 {
 874 #if CONFIG_DEBUG_RAM_SETUP
 875         u32 value1 = pci_read_config32(NORTHBRIDGE_MMC, reg);
 876 #endif
 877         pci_write_config32(NORTHBRIDGE_MMC, reg, new_value);
 878 #if CONFIG_DEBUG_RAM_SETUP
 879         u32 value2 = pci_read_config32(NORTHBRIDGE_MMC, reg);
 880         PRINTK_DEBUG("update reg %02x, old: %08x, new: %08x, read back: %08x\n", reg, value1, new_value, value2);
 881 #endif
 882 }
 883
 884 /* if ram still doesn't work do this function */
 885 static void spd_set_undocumented_registers(void)
 886 {
 887         spd_update(0x74, 0x00000001);
 888         spd_update(0x78, 0x001fe974);
 889         spd_update(0x80, 0x00af0039);
 890         spd_update(0x84, 0x0000033c);
 891         spd_update(0x88, 0x00000010);
 892
 893         spd_update(0xc0, 0x00000003);
 894 }
 895
 896 static void northbridge_set_registers(void)
 897 {
 898         u16 value;
 899         int video_memory = 0;
 900
 901         printk(BIOS_DEBUG, "Setting initial Northbridge registers....\n");
 902
 903         /* Set the value for Fixed DRAM Hole Control Register */
 904         pci_write_config8(NORTHBRIDGE, FDHC, 0x00);
 905
 906         /* Set the value for Programable Attribute Map Registers
 907          * Ideally, this should be R/W for as many ranges as possible.
 908          */
 909         pci_write_config8(NORTHBRIDGE, PAM0, 0x30);
 910         pci_write_config8(NORTHBRIDGE, PAM1, 0x33);
 911         pci_write_config8(NORTHBRIDGE, PAM2, 0x33);
 912         pci_write_config8(NORTHBRIDGE, PAM3, 0x33);
 913         pci_write_config8(NORTHBRIDGE, PAM4, 0x33);
 914         pci_write_config8(NORTHBRIDGE, PAM5, 0x33);
 915         pci_write_config8(NORTHBRIDGE, PAM6, 0x33);
 916
 917         /* Set the value for System Management RAM Control Register */
 918         pci_write_config8(NORTHBRIDGE, SMRAM, 0x02);
 919
 920         /* Set the value for GMCH Control Register #1 */
 921         switch (CONFIG_VIDEO_MB) {
 922         case 1: /* 1M of memory */
 923                 video_memory = 0x1;
 924                 break;
 925         case 4: /* 4M of memory */
 926                 video_memory = 0x2;
 927                 break;
 928         case 8: /* 8M of memory */
 929                 video_memory = 0x3;
 930                 break;
 931         case 16: /* 16M of memory */
 932                 video_memory = 0x4;
 933                 break;
 934         case 32: /* 32M of memory */
 935                 video_memory = 0x5;
 936                 break;
 937         default: /* No memory */
 938                 pci_write_config16(NORTHBRIDGE, GMC, pci_read_config16(NORTHBRIDGE, GMC) | 1);
 939                 video_memory = 0x0;
 940         }
 941
 942         value = pci_read_config16(NORTHBRIDGE, GGC);
 943         value |= video_memory << 4;
 944         if (video_memory == 0) {
 945                 value &= ~(1 < 1);
 946         } else
 947                 value |= (1 < 1);
 948         pci_write_config16(NORTHBRIDGE, GGC, value);
 949
 950         /* AGPCMD: disable AGP, Data-Rate: 1x */
 951         pci_write_config32(NORTHBRIDGE, AGPCMD, 0x00000001);
 952
 953         pci_write_config8(NORTHBRIDGE, AMTT, 0x20);
 954         pci_write_config8(NORTHBRIDGE, LPTT, 0x10);
 955
 956         printk(BIOS_DEBUG, "Initial Northbridge registers have been set.\n");
 957 }
 958
 959 static void sdram_set_spd_registers(void)
 960 {
 961         uint8_t dimm_mask;
 962
 963         PRINTK_DEBUG("Reading SPD data...\n");
 964
 965         dimm_mask = spd_get_supported_dimms();
 966
 967         if (dimm_mask == 0) {
 968                 print_debug("No usable memory for this controller\n");
 969         } else {
 970                 PRINTK_DEBUG("DIMM MASK: %02x\n", dimm_mask);
 971
 972                 spd_set_row_attributes(dimm_mask);
 973                 spd_set_dram_controller_mode(dimm_mask);
 974                 spd_set_dram_timing(dimm_mask);
 975                 spd_set_dram_size(dimm_mask);
 976                 spd_set_dram_pwr_management();
 977                 spd_set_dram_throttle_control();
 978                 spd_set_undocumented_registers();
 979         }
 980
 981         /* Setup Initial Northbridge Registers */
 982         northbridge_set_registers();
 983 }
 984