2 *****************************************************************************
4 * This file is part of the coreboot project.
6 * Copyright (C) 2011 Advanced Micro Devices, Inc.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 * ***************************************************************************
26 #include <cpu/x86/msr.h>
27 #include <cpu/x86/lapic.h>
29 /* NOTE: We use the APIC TIMER register is to hold flags for AP init during
30 * pre-memory init (__PRE_RAM__). Don't use init_timer() and udelay is
31 * redirected to udelay_tsc().
37 /* Set the apic timer to no interrupts and periodic mode */
38 lapic_write(LAPIC_LVTT, (1 << 17)|(1<< 16)|(0 << 12)|(0 << 0));
40 /* Set the divider to 1, no divider */
41 lapic_write(LAPIC_TDCR, LAPIC_TDR_DIV_1);
43 /* Set the initial counter to 0xffffffff */
44 lapic_write(LAPIC_TMICT, 0xffffffff);
49 void udelay(u32 usecs)
51 u32 start, value, ticks;
52 /* Calculate the number of ticks to run, our FSB runs a 200Mhz */
54 start = lapic_read(LAPIC_TMCCT);
56 value = lapic_read(LAPIC_TMCCT);
57 } while((start - value) < ticks);