src/mainboard/supermicro/h8qgi/agesawrapper.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2011 Advanced Micro Devices, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18  */
  19
  20 /*----------------------------------------------------------------------------------------
  21  *                             M O D U L E S    U S E D
  22  *----------------------------------------------------------------------------------------
  23  */
  24
  25 #include <stdint.h>
  26 #include <string.h>
  27 #include "agesawrapper.h"
  28 #include "BiosCallOuts.h"
  29 #include "cpuRegisters.h"
  30 #include "cpuCacheInit.h"
  31 #include "cpuApicUtilities.h"
  32 #include "cpuEarlyInit.h"
  33 #include "cpuLateInit.h"
  34 #include "Dispatcher.h"
  35 #include "cpuCacheInit.h"
  36 #include "amdlib.h"
  37 #include "platform_oem.h"
  38 #include "Filecode.h"
  39 #include "heapManager.h"
  40 #include <cpuFamilyTranslation.h> /* CPU_SPECIFIC_SERVICES */
  41
  42 #define FILECODE UNASSIGNED_FILE_FILECODE
  43
  44 /*----------------------------------------------------------------------------------------
  45  *                   D E F I N I T I O N S    A N D    M A C R O S
  46  *----------------------------------------------------------------------------------------
  47  */
  48
  49 /* ACPI table pointers returned by AmdInitLate */
  50 VOID *DmiTable    = NULL;
  51 VOID *AcpiPstate  = NULL;
  52 VOID *AcpiSrat    = NULL;
  53 VOID *AcpiSlit    = NULL;
  54
  55 VOID *AcpiWheaMce = NULL;
  56 VOID *AcpiWheaCmc = NULL;
  57 //VOID *AcpiAlib    = NULL;
  58
  59
  60 /*----------------------------------------------------------------------------------------
  61  *                  T Y P E D E F S     A N D     S T R U C T U  R E S
  62  *----------------------------------------------------------------------------------------
  63  */
  64
  65 /*----------------------------------------------------------------------------------------
  66  *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
  67  *----------------------------------------------------------------------------------------
  68  */
  69
  70 /*----------------------------------------------------------------------------------------
  71  *                          E X P O R T E D    F U N C T I O N S
  72  *----------------------------------------------------------------------------------------
  73  */
  74
  75 /*---------------------------------------------------------------------------------------
  76  *                          L O C A L    F U N C T I O N S
  77  *---------------------------------------------------------------------------------------
  78  */
  79
  80 static UINT32 agesawrapper_amdinitcpuio(VOID)
  81 {
  82         AGESA_STATUS            Status;
  83         UINT32                  PciData;
  84         PCI_ADDR                PciAddress;
  85         AMD_CONFIG_PARAMS       StdHeader;
  86         UINT32                  nodes;
  87         UINT32                  node;
  88         UINT32                  sblink;
  89         UINT32                  i;
  90
  91         /* get the number of coherent nodes in the system */
  92         PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB, FUNC_0, 0x60);
  93         LibAmdPciRead(AccessWidth32, PciAddress, &PciData, &StdHeader);
  94         nodes = ((PciData >> 4) & 7) + 1; //NodeCnt[2:0]
  95
  96         /* Find out the Link ID of Node0 that connects to the
  97          * Southbridge (system IO hub). e.g. family10 MCM Processor,
  98          * sbLink is Processor0 Link2, internal Node0 Link3
  99          */
 100         PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB, FUNC_0, 0x64);
 101         LibAmdPciRead(AccessWidth32, PciAddress, &PciData, &StdHeader);
 102         sblink = (PciData >> 8) & 3; //assume ganged
 103
 104         /* Enable MMIO on AMD CPU Address Map Controller for all nodes */
 105         for (node = 0; node < nodes; node++) {
 106                 /* clear all MMIO Mapped Base/Limit Registers */
 107                 for (i = 0; i < 8; i++) {
 108                         PciData = 0x00000000;
 109                         PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x80 + i*8);
 110                         LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
 111                         PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x84 + i*8);
 112                         LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
 113                 }
 114
 115                 /* clear all IO Space Base/Limit Registers */
 116                 for (i = 0; i < 4; i++) {
 117                         PciData = 0x00000000;
 118                         PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xC4 + i*8);
 119                         LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
 120                         PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xC0 + i*8);
 121                         LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
 122                 }
 123
 124                 /* Set VGA Ram MMIO 0000A0000-0000BFFFF to Node0 sbLink */
 125                 PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x84);
 126                 PciData = 0x00000B00;
 127                 PciData |= sblink << 4;
 128                 LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
 129                 PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x80);
 130                 PciData = 0x00000A03;
 131                 LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
 132
 133                 /* Set F0000000-FFFFFFFF to Node0 sbLink. */
 134                 PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x8C);
 135                 PciData = 0x00FFFF00;
 136                 PciData |= sblink << 4;
 137                 LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
 138                 PciData = 0x00F00000 | 0x03;
 139                 PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x88);
 140                 LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
 141
 142                 /* Set MMCONF space to Node0 sbLink with NP set.
 143                  * default E0000000-EFFFFFFF
 144                  * Just have all mmio set to non-posted,
 145                  * coreboot not implemente the range by range setting yet.
 146                  */
 147                 PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xBC);
 148                 PciData = CONFIG_MMCONF_BASE_ADDRESS + (CONFIG_MMCONF_BUS_NUMBER * 0x100000);//1MB each bus
 149                 PciData = (PciData >> 8) & 0xFFFFFF00;
 150                 PciData |= 0x80; //NP
 151                 PciData |= sblink << 4;
 152                 LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
 153                 PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xB8);
 154                 PciData = (PCIE_BASE_ADDRESS >> 8) | 0x03;
 155                 LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
 156
 157
 158                 /* Start to set IO 0x9000-0xEFFF to Node0 sbLink with ISA&VGA set. */
 159                 PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xC4);
 160                 PciData = 0x0000E000;
 161                 PciData |= sblink << 4;
 162                 LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
 163                 PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xC0);
 164                 PciData = 0x00009033;
 165                 LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
 166         }
 167
 168         Status = AGESA_SUCCESS;
 169         return (UINT32)Status;
 170 }
 171
 172 UINT32 agesawrapper_amdinitmmio(VOID)
 173 {
 174         AGESA_STATUS                  Status;
 175         UINT64                        MsrReg;
 176         AMD_CONFIG_PARAMS             StdHeader;
 177
 178         /*
 179          * Set the MMIO Configuration Base Address and Bus Range onto
 180          * MMIO configuration base Address MSR register.
 181          */
 182         MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse(CONFIG_MMCONF_BUS_NUMBER) << 2) | 1;
 183         LibAmdMsrWrite(0xC0010058, &MsrReg, &StdHeader);
 184
 185         /*
 186          * Set the NB_CFG MSR register. Enable CF8 extended configuration cycles.
 187          */
 188         LibAmdMsrRead(0xC001001F, &MsrReg, &StdHeader);
 189         MsrReg = MsrReg | (1ULL << 46);
 190         LibAmdMsrWrite(0xC001001F, &MsrReg, &StdHeader);
 191
 192         /* Set ROM cache onto WP to decrease post time */
 193         MsrReg = (0x0100000000ull - CONFIG_ROM_SIZE) | 5;
 194         LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);
 195         MsrReg = (0x1000000000ull - CONFIG_ROM_SIZE) | 0x800;
 196         LibAmdMsrWrite(0x20D, &MsrReg, &StdHeader);
 197
 198         Status = AGESA_SUCCESS;
 199         return (UINT32)Status;
 200 }
 201
 202 UINT32 agesawrapper_amdinitreset(VOID)
 203 {
 204         AGESA_STATUS status = AGESA_SUCCESS;
 205         AMD_INTERFACE_PARAMS AmdParamStruct;
 206         AMD_RESET_PARAMS AmdResetParams;
 207
 208         LibAmdMemFill(&AmdParamStruct,
 209                         0,
 210                         sizeof(AMD_INTERFACE_PARAMS),
 211                         &(AmdParamStruct.StdHeader));
 212
 213         LibAmdMemFill(&AmdResetParams,
 214                         0,
 215                         sizeof(AMD_RESET_PARAMS),
 216                         &(AmdResetParams.StdHeader));
 217
 218         AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET;
 219         AmdParamStruct.AllocationMethod = ByHost;
 220         AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS);
 221         AmdParamStruct.NewStructPtr = &AmdResetParams;
 222         AmdParamStruct.StdHeader.AltImageBasePtr = 0;
 223         AmdParamStruct.StdHeader.CalloutPtr = NULL;
 224         AmdParamStruct.StdHeader.Func = 0;
 225         AmdParamStruct.StdHeader.ImageBasePtr = 0;
 226         AmdCreateStruct(&AmdParamStruct);
 227         AmdResetParams.HtConfig.Depth = 0;
 228
 229         //MARG34PI disabled AGESA_ENTRY_INIT_RESET by default
 230         //but we need to call AmdCreateStruct to call HeapManagerInit, or the event log not work
 231 #if (defined AGESA_ENTRY_INIT_RESET) && (AGESA_ENTRY_INIT_RESET == TRUE)
 232         status = AmdInitReset((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr);
 233 #endif
 234         if (status != AGESA_SUCCESS)
 235                 agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus);
 236         AmdReleaseStruct(&AmdParamStruct);
 237
 238         return (UINT32)status;
 239 }
 240
 241 UINT32 agesawrapper_amdinitearly(VOID)
 242 {
 243         AGESA_STATUS status;
 244         AMD_INTERFACE_PARAMS AmdParamStruct;
 245         AMD_EARLY_PARAMS     *AmdEarlyParamsPtr;
 246         UINT32 TscRateInMhz;
 247         CPU_SPECIFIC_SERVICES *FamilySpecificServices;
 248
 249         LibAmdMemFill(&AmdParamStruct,
 250                         0,
 251                         sizeof(AMD_INTERFACE_PARAMS),
 252                         &(AmdParamStruct.StdHeader));
 253
 254         AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY;
 255         AmdParamStruct.AllocationMethod = PreMemHeap;
 256         AmdParamStruct.StdHeader.AltImageBasePtr = 0;
 257         AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
 258         AmdParamStruct.StdHeader.Func = 0;
 259         AmdParamStruct.StdHeader.ImageBasePtr = 0;
 260         AmdCreateStruct(&AmdParamStruct);
 261
 262         AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr;
 263         OemCustomizeInitEarly(AmdEarlyParamsPtr);
 264
 265         status = AmdInitEarly((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr);
 266         if (status != AGESA_SUCCESS)
 267                 agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus);
 268
 269         GetCpuServicesOfCurrentCore(&FamilySpecificServices, &AmdParamStruct.StdHeader);
 270         FamilySpecificServices->GetTscRate(FamilySpecificServices, &TscRateInMhz, &AmdParamStruct.StdHeader);
 271         printk(BIOS_DEBUG, "BSP Frequency: %luMHz\n", TscRateInMhz);
 272
 273         AmdReleaseStruct(&AmdParamStruct);
 274         return (UINT32)status;
 275 }
 276
 277 UINT32 agesawrapper_amdinitpost(VOID)
 278 {
 279         AGESA_STATUS status;
 280         UINT16 i;
 281         UINT32 *HeadPtr;
 282         AMD_INTERFACE_PARAMS  AmdParamStruct;
 283         BIOS_HEAP_MANAGER    *BiosManagerPtr;
 284         UINT32 TscRateInMhz;
 285         CPU_SPECIFIC_SERVICES *FamilySpecificServices;
 286
 287         LibAmdMemFill(&AmdParamStruct,
 288                         0,
 289                         sizeof(AMD_INTERFACE_PARAMS),
 290                         &(AmdParamStruct.StdHeader));
 291
 292         AmdParamStruct.AgesaFunctionName = AMD_INIT_POST;
 293         AmdParamStruct.AllocationMethod = PreMemHeap;
 294         AmdParamStruct.StdHeader.AltImageBasePtr = 0;
 295         AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
 296         AmdParamStruct.StdHeader.Func = 0;
 297         AmdParamStruct.StdHeader.ImageBasePtr = 0;
 298
 299         AmdCreateStruct(&AmdParamStruct);
 300         status = AmdInitPost((AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr);
 301         if (status != AGESA_SUCCESS)
 302                 agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus);
 303         AmdReleaseStruct(&AmdParamStruct);
 304
 305         /* Initialize heap space */
 306         BiosManagerPtr = (BIOS_HEAP_MANAGER *)BIOS_HEAP_START_ADDRESS;
 307
 308         HeadPtr = (UINT32 *) ((UINT8 *) BiosManagerPtr + sizeof(BIOS_HEAP_MANAGER));
 309         for (i = 0; i < ((BIOS_HEAP_SIZE/4) - (sizeof(BIOS_HEAP_MANAGER)/4)); i++) {
 310                 *HeadPtr = 0x00000000;
 311                 HeadPtr++;
 312         }
 313         BiosManagerPtr->StartOfAllocatedNodes = 0;
 314         BiosManagerPtr->StartOfFreedNodes = 0;
 315
 316         GetCpuServicesOfCurrentCore (&FamilySpecificServices, &AmdParamStruct.StdHeader);
 317         FamilySpecificServices->GetTscRate (FamilySpecificServices, &TscRateInMhz, &AmdParamStruct.StdHeader);
 318         printk(BIOS_DEBUG, "BSP Frequency: %luMHz\n", TscRateInMhz);
 319
 320         return (UINT32)status;
 321 }
 322
 323 UINT32 agesawrapper_amdinitenv(VOID)
 324 {
 325         AGESA_STATUS status;
 326         AMD_INTERFACE_PARAMS AmdParamStruct;
 327
 328         LibAmdMemFill(&AmdParamStruct,
 329                         0,
 330                         sizeof(AMD_INTERFACE_PARAMS),
 331                         &(AmdParamStruct.StdHeader));
 332
 333         AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV;
 334         AmdParamStruct.AllocationMethod = PostMemDram;
 335         AmdParamStruct.StdHeader.AltImageBasePtr = 0;
 336         AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
 337         AmdParamStruct.StdHeader.Func = 0;
 338         AmdParamStruct.StdHeader.ImageBasePtr = 0;
 339         AmdCreateStruct(&AmdParamStruct);
 340         status = AmdInitEnv((AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr);
 341         if (status != AGESA_SUCCESS)
 342                 agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus);
 343
 344         AmdReleaseStruct(&AmdParamStruct);
 345         return (UINT32)status;
 346 }
 347
 348 VOID * agesawrapper_getlateinitptr(int pick)
 349 {
 350         switch (pick) {
 351                 case PICK_DMI:
 352                         return DmiTable;
 353
 354                 case PICK_PSTATE:
 355                         return AcpiPstate;
 356
 357                 case PICK_SRAT:
 358                         return AcpiSrat;
 359
 360                 case PICK_SLIT:
 361                         return AcpiSlit;
 362                 case PICK_WHEA_MCE:
 363                         return AcpiWheaMce;
 364                 case PICK_WHEA_CMC:
 365                         return AcpiWheaCmc;
 366 /*
 367                 case PICK_ALIB:
 368                         return AcpiAlib;
 369 */
 370                 default:
 371                         return NULL;
 372         }
 373
 374         return NULL;
 375 }
 376
 377 UINT32 agesawrapper_amdinitmid(VOID)
 378 {
 379         AGESA_STATUS status;
 380         AMD_INTERFACE_PARAMS AmdParamStruct;
 381
 382         /* Enable MMIO on AMD CPU Address Map Controller */
 383         agesawrapper_amdinitcpuio();
 384
 385         LibAmdMemFill(&AmdParamStruct,
 386                         0,
 387                         sizeof(AMD_INTERFACE_PARAMS),
 388                         &(AmdParamStruct.StdHeader));
 389
 390         AmdParamStruct.AgesaFunctionName = AMD_INIT_MID;
 391         AmdParamStruct.AllocationMethod = PostMemDram;
 392         AmdParamStruct.StdHeader.AltImageBasePtr = 0;
 393         AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
 394         AmdParamStruct.StdHeader.Func = 0;
 395         AmdParamStruct.StdHeader.ImageBasePtr = 0;
 396
 397         AmdCreateStruct(&AmdParamStruct);
 398         status = AmdInitMid((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr);
 399         if (status != AGESA_SUCCESS)
 400                 agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus);
 401         AmdReleaseStruct(&AmdParamStruct);
 402
 403         return (UINT32)status;
 404 }
 405
 406 UINT32 agesawrapper_amdinitlate(VOID)
 407 {
 408         AGESA_STATUS Status;
 409         AMD_LATE_PARAMS AmdLateParams;
 410
 411         LibAmdMemFill(&AmdLateParams,
 412                         0,
 413                         sizeof(AMD_LATE_PARAMS),
 414                         &(AmdLateParams.StdHeader));
 415
 416         AmdLateParams.StdHeader.AltImageBasePtr = 0;
 417         AmdLateParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
 418         AmdLateParams.StdHeader.Func = 0;
 419         AmdLateParams.StdHeader.ImageBasePtr = 0;
 420         AmdLateParams.StdHeader.HeapStatus = HEAP_SYSTEM_MEM;
 421
 422         Status = AmdInitLate(&AmdLateParams);
 423         if (Status != AGESA_SUCCESS) {
 424                 agesawrapper_amdreadeventlog(AmdLateParams.StdHeader.HeapStatus);
 425                 ASSERT(Status == AGESA_SUCCESS);
 426         }
 427
 428         DmiTable       = AmdLateParams.DmiTable;
 429         AcpiPstate     = AmdLateParams.AcpiPState;
 430         AcpiSrat       = AmdLateParams.AcpiSrat;
 431         AcpiSlit       = AmdLateParams.AcpiSlit;
 432
 433         AcpiWheaMce    = AmdLateParams.AcpiWheaMce;
 434         AcpiWheaCmc    = AmdLateParams.AcpiWheaCmc;
 435         //AcpiAlib       = AmdLateParams.AcpiAlib;
 436
 437         return (UINT32)Status;
 438 }
 439
 440 /**
 441  * @param[in] UINTN ApicIdOfCore,
 442  * @param[in] AP_EXE_PARAMS *LaunchApParams
 443  */
 444 UINT32 agesawrapper_amdlaterunaptask(UINT32 Data, VOID *ConfigPtr)
 445 {
 446         AGESA_STATUS Status;
 447         AMD_LATE_PARAMS AmdLateParams;
 448
 449         LibAmdMemFill(&AmdLateParams,
 450                         0,
 451                         sizeof(AMD_LATE_PARAMS),
 452                         &(AmdLateParams.StdHeader));
 453
 454         AmdLateParams.StdHeader.AltImageBasePtr = 0;
 455         AmdLateParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
 456         AmdLateParams.StdHeader.Func = 0;
 457         AmdLateParams.StdHeader.ImageBasePtr = 0;
 458         AmdLateParams.StdHeader.HeapStatus = HEAP_TEMP_MEM;
 459
 460         printk(BIOS_DEBUG, "AmdLateRunApTask on Core: %x\n", (uint32_t)Data);
 461         Status = AmdLateRunApTask((AP_EXE_PARAMS *)ConfigPtr);
 462         if (Status != AGESA_SUCCESS) {
 463                 agesawrapper_amdreadeventlog(AmdLateParams.StdHeader.HeapStatus);
 464                 ASSERT(Status <= AGESA_UNSUPPORTED);
 465         }
 466
 467         DmiTable       = AmdLateParams.DmiTable;
 468         AcpiPstate     = AmdLateParams.AcpiPState;
 469         AcpiSrat       = AmdLateParams.AcpiSrat;
 470         AcpiSlit       = AmdLateParams.AcpiSlit;
 471
 472         AcpiWheaMce    = AmdLateParams.AcpiWheaMce;
 473         AcpiWheaCmc    = AmdLateParams.AcpiWheaCmc;
 474         //  AcpiAlib       = AmdLateParams.AcpiAlib;
 475
 476         return (UINT32)Status;
 477 }
 478
 479 /**
 480  *
 481  */
 482 static void agesa_bound_check(EVENT_PARAMS *event)
 483 {
 484         switch (event->EventInfo) {
 485                 case CPU_ERROR_HEAP_IS_FULL:
 486                         printk(BIOS_DEBUG, "Heap allocation for specified buffer handle failed as heap is full\n");
 487                         break;
 488
 489                 case CPU_ERROR_HEAP_BUFFER_HANDLE_IS_ALREADY_USED:
 490                         printk(BIOS_DEBUG, "Allocation incomplete as buffer has previously been allocated\n");
 491                         break;
 492
 493                 case CPU_ERROR_HEAP_BUFFER_HANDLE_IS_NOT_PRESENT:
 494                         printk(BIOS_DEBUG, "Unable to locate buffer handle or deallocate heap as buffer handle cannot be located\n");
 495                         break;
 496
 497                 case CPU_ERROR_HEAP_BUFFER_IS_NOT_PRESENT:
 498                         printk(BIOS_DEBUG, "Unable to locate pointer to the heap buffer\n");
 499                         break;
 500
 501                 default:
 502                         break;
 503         }
 504 }
 505
 506 /**
 507  *
 508  */
 509 static void agesa_alert(EVENT_PARAMS *event)
 510 {
 511         switch (event->EventInfo) {
 512                 case MEM_ALERT_USER_TMG_MODE_OVERRULED:
 513                         printk(BIOS_DEBUG, "Socket %lx Dct %lx Channel %lx "
 514                                         "TIMING_MODE_SPECIFIC is requested but can not be applied to current configurations.\n",
 515                                         event->DataParam1,
 516                                         event->DataParam2,
 517                                         event->DataParam3);
 518                         break;
 519
 520                 case MEM_ALERT_ORG_MISMATCH_DIMM:
 521                         printk(BIOS_DEBUG, "Socket %lx Dct %lx Channel %lx "
 522                                         "DIMM organization miss-match\n",
 523                                         event->DataParam1,
 524                                         event->DataParam2,
 525                                         event->DataParam3);
 526                         break;
 527
 528                 case MEM_ALERT_BK_INT_DIS:
 529                         printk(BIOS_DEBUG, "Socket %lx Dct %lx Channel %lx "
 530                                         "Bank interleaving disable for internal issue\n",
 531                                         event->DataParam1,
 532                                         event->DataParam2,
 533                                         event->DataParam3);
 534                         break;
 535
 536                 case CPU_EVENT_BIST_ERROR:
 537                         printk(BIOS_DEBUG, "BIST error: %lx reported on Socket %lx Core %lx\n",
 538                                         event->DataParam1,
 539                                         event->DataParam2,
 540                                         event->DataParam3);
 541                         break;
 542
 543                 case HT_EVENT_HW_SYNCFLOOD:
 544                         printk(BIOS_DEBUG, "HT_EVENT_DATA_HW_SYNCFLOOD error on Socket %lx Link %lx\n",
 545                                         event->DataParam1,
 546                                         event->DataParam2);
 547                         break;
 548
 549                 case HT_EVENT_HW_HTCRC:
 550                         printk(BIOS_DEBUG, "HT_EVENT_HW_HTCRC error on Socket %lx Link %lx Lanemask:%lx\n",
 551                                         event->DataParam1,
 552                                         event->DataParam2,
 553                                         event->DataParam3);
 554                         break;
 555
 556                 default:
 557                         break;
 558         }
 559 }
 560
 561 /**
 562  *
 563  */
 564 static void agesa_warning(EVENT_PARAMS *event)
 565 {
 566 /*
 567         if (event->EventInfo == CPU_EVENT_STACK_REENTRY) {
 568                 printk(BIOS_DEBUG,
 569                                 "The stack has already been enabled and this is a
 570                                 redundant invocation of AMD_ENABLE_STACK. There is no event logged and
 571                                 no data values. The event sub-class is returned along with the status code\n");
 572                 return;
 573         }
 574 */
 575
 576         switch (event->EventInfo >> 24) {
 577                 case 0x04:
 578                         printk(BIOS_DEBUG, "Memory: Socket %lx Dct %lx Channel%lx ",
 579                                         event->DataParam1,
 580                                         event->DataParam2,
 581                                         event->DataParam3);
 582                         break;
 583
 584                 case 0x08:
 585                         printk(BIOS_DEBUG, "Processor: ");
 586                         break;
 587
 588                 case 0x10:
 589                         printk(BIOS_DEBUG, "Hyper Transport: ");
 590                         break;
 591
 592                 default:
 593                         break;
 594         }
 595
 596         switch (event->EventInfo) {
 597                 case MEM_WARNING_UNSUPPORTED_QRDIMM:
 598                         printk(BIOS_DEBUG, "QR DIMMs detected but not supported\n");
 599                         break;
 600
 601                 case MEM_WARNING_UNSUPPORTED_UDIMM:
 602                         printk(BIOS_DEBUG, "Unbuffered DIMMs detected but not supported\n");
 603                         break;
 604
 605                 case MEM_WARNING_UNSUPPORTED_SODIMM:
 606                         printk(BIOS_DEBUG, "SO-DIMMs detected but not supported");
 607                         break;
 608
 609                 case MEM_WARNING_UNSUPPORTED_X4DIMM:
 610                         printk(BIOS_DEBUG, "x4 DIMMs detected but not supported");
 611                         break;
 612
 613                 case MEM_WARNING_UNSUPPORTED_RDIMM:
 614                         printk(BIOS_DEBUG, "Registered DIMMs detected but not supported");
 615                         break;
 616
 617 /*
 618                 case MEM_WARNING_UNSUPPORTED_LRDIMM:
 619                         printk(BIOS_DEBUG, "Load Reduced DIMMs detected but not supported");
 620                         break;
 621 */
 622
 623                 case MEM_WARNING_NO_SPDTRC_FOUND:
 624                         printk(BIOS_DEBUG, "NO_SPDTRC_FOUND");
 625                         break;
 626
 627                 case MEM_WARNING_EMP_NOT_SUPPORTED:
 628                         printk(BIOS_DEBUG, "Processor is not capable for EMP");//
 629                         break;
 630
 631                 case MEM_WARNING_EMP_CONFLICT:
 632                         printk(BIOS_DEBUG, "EMP cannot be enabled if channel interleaving bank interleaving, or bank swizzle is enabled\n");//
 633                         break;
 634
 635                 case MEM_WARNING_EMP_NOT_ENABLED:
 636                         printk(BIOS_DEBUG, "Memory size is not power of two\n");//
 637                         break;
 638
 639                 case MEM_WARNING_PERFORMANCE_ENABLED_BATTERY_LIFE_PREFERRED:
 640                         printk(BIOS_DEBUG, "MEM_WARNING_PERFORMANCE_ENABLED_BATTERY_LIFE_PREFERRED\n");
 641                         break;
 642
 643                 case MEM_WARNING_NODE_INTERLEAVING_NOT_ENABLED:
 644                         printk(BIOS_DEBUG, "MEM_WARNING_NODE_INTERLEAVING_NOT_ENABLED\n");
 645                         break;
 646
 647                 case MEM_WARNING_CHANNEL_INTERLEAVING_NOT_ENABLED:
 648                         printk(BIOS_DEBUG, "MEM_WARNING_CHANNEL_INTERLEAVING_NOT_ENABLED\n");
 649                         break;
 650
 651                 case MEM_WARNING_BANK_INTERLEAVING_NOT_ENABLED:
 652                         printk(BIOS_DEBUG, "MEM_WARNING_BANK_INTERLEAVING_NOT_ENABLED\n");
 653                         break;
 654
 655                 case MEM_WARNING_VOLTAGE_1_35_NOT_SUPPORTED:
 656                         printk(BIOS_DEBUG, "MEM_WARNING_VOLTAGE_1_35_NOT_SUPPORTED\n");
 657                         break;
 658
 659 /*
 660                 case MEM_WARNING_INITIAL_DDR3VOLT_NONZERO:
 661                         printk(BIOS_DEBUG, "MEM_WARNING_INITIAL_DDR3VOLT_NONZERO\n");
 662                         break;
 663
 664                 case MEM_WARNING_NO_COMMONLY_SUPPORTED_VDDIO:
 665                         printk(BIOS_DEBUG, "MEM_WARNING_NO_COMMONLY_SUPPORTED_VDDIO\n");
 666                         break;
 667 */
 668
 669                 case CPU_EVENT_EXECUTION_CACHE_ALLOCATION_ERROR:
 670                         printk(BIOS_DEBUG, "Allocation rule number that has been violated:");
 671                         if ((event->EventInfo & 0x000000FF) == 0x01) {
 672                                 printk(BIOS_DEBUG, "AGESA_CACHE_SIZE_REDUCED\n");
 673                         } else if ((event->EventInfo & 0x000000FF) == 0x02) {
 674                                 printk(BIOS_DEBUG, "AGESA_CACHE_REGIONS_ACROSS_1MB\n");
 675                         } else if ((event->EventInfo & 0x000000FF) == 0x03) {
 676                                 printk(BIOS_DEBUG, "AGESA_CACHE_REGIONS_ACROSS_4GB\n");
 677                         }
 678                         printk(BIOS_DEBUG, "cache region index:%lx, start:%lx size:%lx\n",
 679                                         event->DataParam1,
 680                                         event->DataParam2,
 681                                         event->DataParam3);
 682                         break;
 683
 684                 case CPU_WARNING_ADJUSTED_LEVELING_MODE:
 685                         printk(BIOS_DEBUG, "CPU_WARNING_ADJUSTED_LEVELING_MODE "
 686                                         "requested: %lx, actual level:%lx\n",
 687                                         event->DataParam1,
 688                                         event->DataParam2);
 689                         break;
 690
 691                 case CPU_EVENT_PM_PSTATE_OVERCURRENT:
 692                         printk(BIOS_DEBUG, "CPU_EVENT_PM_PSTATE_OVERCURRENT "
 693                                                 "Socket: %lx, Pstate:%lx\n",
 694                                                 event->DataParam1,
 695                                                 event->DataParam2);
 696                         break;
 697
 698                 case CPU_WARNING_NONOPTIMAL_HT_ASSIST_CFG:
 699                         printk(BIOS_DEBUG, "CPU_WARNING_NONOPTIMAL_HT_ASSIST_CFG\n");
 700                         break;
 701
 702 /*
 703                 case CPU_EVENT_UNKNOWN_PROCESSOR_REVISION:
 704                         printk(BIOS_DEBUG, "CPU_EVENT_UNKNOWN_PROCESSOR_REVISION, socket: %lx, cpuid:%lx\n",
 705                                 event->DataParam1,
 706                                 event->DataParam2);
 707                         break;
 708 */
 709
 710                 case HT_EVENT_OPT_REQUIRED_CAP_RETRY:
 711                         printk(BIOS_DEBUG, "HT_EVENT_OPT_REQUIRED_CAP_RETRY, Socket %lx Link %lx Depth %lx\n",
 712                                 event->DataParam1,
 713                                 event->DataParam2,
 714                                 event->DataParam3);
 715                         break;
 716
 717                 case HT_EVENT_OPT_REQUIRED_CAP_GEN3:
 718                         printk(BIOS_DEBUG, "HT_EVENT_OPT_REQUIRED_CAP_GEN3, Socket %lx Link %lx Depth %lx\n",
 719                                         event->DataParam1,
 720                                         event->DataParam2,
 721                                         event->DataParam3);
 722                         break;
 723
 724                 case HT_EVENT_OPT_UNUSED_LINKS:
 725                         printk(BIOS_DEBUG, "HT_EVENT_OPT_UNUSED_LINKS, SocketA%lx LinkA%lx SocketB%lx LinkB%lx\n",
 726                                         event->DataParam1,
 727                                         event->DataParam2,
 728                                         event->DataParam3,
 729                                         event->DataParam4);
 730                         break;
 731
 732                 case HT_EVENT_OPT_LINK_PAIR_EXCEED:
 733                         printk(BIOS_DEBUG, "HT_EVENT_OPT_LINK_PAIR_EXCEED, SocketA%lx MasterLink%lx SocketB%lx AltLink%lx\n",
 734
 735                                         event->DataParam1,
 736                                         event->DataParam2,
 737                                         event->DataParam3,
 738                                         event->DataParam4);
 739                 default:
 740                         break;
 741         }
 742 }
 743
 744 /**
 745  *
 746  */
 747 static void agesa_error(EVENT_PARAMS *event)
 748 {
 749
 750         switch (event->EventInfo >> 24) {
 751                 case 0x04:
 752                         printk(BIOS_DEBUG, "Memory: Socket %lx Dct %lx Channel%lx ",
 753                                         event->DataParam1,
 754                                         event->DataParam2,
 755                                         event->DataParam3);
 756                         break;
 757
 758                 case 0x08:
 759                         printk(BIOS_DEBUG, "Processor: ");
 760                         break;
 761
 762                 case 0x10:
 763                         printk(BIOS_DEBUG, "Hyper Transport: ");
 764                         break;
 765
 766                 default:
 767                         break;
 768         }
 769
 770         switch (event->EventInfo) {
 771                 case MEM_ERROR_NO_DQS_POS_RD_WINDOW:
 772                         printk(BIOS_DEBUG, "No DQS Position window for RD DQS\n");
 773                         break;
 774
 775                 case MEM_ERROR_SMALL_DQS_POS_RD_WINDOW:
 776                         printk(BIOS_DEBUG, "Small DQS Position window for RD DQS\n");
 777                         break;
 778
 779                 case MEM_ERROR_NO_DQS_POS_WR_WINDOW:
 780                         printk(BIOS_DEBUG, "No DQS Position window for WR DQS\n");
 781                         break;
 782
 783                 case MEM_ERROR_SMALL_DQS_POS_WR_WINDOW:
 784                         printk(BIOS_DEBUG, "Small DQS Position window for WR DQS\n");
 785                         break;
 786
 787                 case MEM_ERROR_ECC_DIS:
 788                         printk(BIOS_DEBUG, "ECC has been disabled as a result of an internal issue\n");
 789                         break;
 790
 791                 case MEM_ERROR_DIMM_SPARING_NOT_ENABLED:
 792                         printk(BIOS_DEBUG, "DIMM sparing has not been enabled for an internal issues\n");
 793                         break;
 794
 795                 case MEM_ERROR_RCVR_EN_VALUE_TOO_LARGE:
 796                         printk(BIOS_DEBUG, "Receive Enable value is too large\n");
 797                         break;
 798                 case MEM_ERROR_RCVR_EN_NO_PASSING_WINDOW:
 799                         printk(BIOS_DEBUG, "There is no DQS receiver enable window\n");
 800                         break;
 801
 802                 case MEM_ERROR_DRAM_ENABLED_TIME_OUT:
 803                         printk(BIOS_DEBUG, "Time out when polling DramEnabled bit\n");
 804                         break;
 805
 806                 case MEM_ERROR_DCT_ACCESS_DONE_TIME_OUT:
 807                         printk(BIOS_DEBUG, "Time out when polling DctAccessDone bit\n");
 808                         break;
 809
 810                 case MEM_ERROR_SEND_CTRL_WORD_TIME_OUT:
 811                         printk(BIOS_DEBUG, "Time out when polling SendCtrlWord bit\n");
 812                         break;
 813
 814                 case MEM_ERROR_PREF_DRAM_TRAIN_MODE_TIME_OUT:
 815                         printk(BIOS_DEBUG, "Time out when polling PrefDramTrainMode bit\n");
 816                         break;
 817
 818                 case MEM_ERROR_ENTER_SELF_REF_TIME_OUT:
 819                         printk(BIOS_DEBUG, "Time out when polling EnterSelfRef bit\n");
 820                         break;
 821
 822                 case MEM_ERROR_FREQ_CHG_IN_PROG_TIME_OUT:
 823                         printk(BIOS_DEBUG, "Time out when polling FreqChgInProg bit\n");
 824                         break;
 825
 826                 case MEM_ERROR_EXIT_SELF_REF_TIME_OUT:
 827                         printk(BIOS_DEBUG, "Time out when polling ExitSelfRef bit\n");
 828                         break;
 829
 830                 case MEM_ERROR_SEND_MRS_CMD_TIME_OUT:
 831                         printk(BIOS_DEBUG, "Time out when polling SendMrsCmd bit\n");
 832                         break;
 833
 834                 case MEM_ERROR_SEND_ZQ_CMD_TIME_OUT:
 835                         printk(BIOS_DEBUG, "Time out when polling SendZQCmd bit\n");
 836                         break;
 837
 838                 case MEM_ERROR_DCT_EXTRA_ACCESS_DONE_TIME_OUT:
 839                         printk(BIOS_DEBUG, "Time out when polling DctExtraAccessDone bit\n");
 840                         break;
 841
 842                 case MEM_ERROR_MEM_CLR_BUSY_TIME_OUT:
 843                         printk(BIOS_DEBUG, "Time out when polling MemClrBusy bit\n");
 844                         break;
 845
 846                 case MEM_ERROR_MEM_CLEARED_TIME_OUT:
 847                         printk(BIOS_DEBUG, "Time out when polling MemCleared bit\n");
 848                         break;
 849
 850                 case MEM_ERROR_FLUSH_WR_TIME_OUT:
 851                         printk(BIOS_DEBUG, "Time out when polling FlushWr bit\n");
 852                         break;
 853
 854                 case MEM_ERROR_MAX_LAT_NO_WINDOW:
 855                         printk(BIOS_DEBUG, "Fail to find pass during Max Rd Latency training\n");
 856                         break;
 857
 858                 case MEM_ERROR_PARALLEL_TRAINING_LAUNCH_FAIL:
 859                         printk(BIOS_DEBUG, "Fail to launch training code on an AP\n");
 860                         break;
 861
 862                 case MEM_ERROR_PARALLEL_TRAINING_TIME_OUT:
 863                         printk(BIOS_DEBUG, "Fail to finish parallel training\n");
 864                         break;
 865
 866                 case MEM_ERROR_NO_ADDRESS_MAPPING:
 867                         printk(BIOS_DEBUG, "No address mapping found for a dimm\n");
 868                         break;
 869
 870                 case MEM_ERROR_RCVR_EN_NO_PASSING_WINDOW_EQUAL_LIMIT:
 871                         printk(BIOS_DEBUG, "There is no DQS receiver enable window and the value is equal to the largest value\n");
 872                         break;
 873
 874                 case MEM_ERROR_RCVR_EN_VALUE_TOO_LARGE_LIMIT_LESS_ONE:
 875                         printk(BIOS_DEBUG, "Receive Enable value is too large and is 1 less than limit\n");
 876                         break;
 877
 878                 case MEM_ERROR_CHECKSUM_NV_SPDCHK_RESTRT_ERROR:
 879                         printk(BIOS_DEBUG, "SPD Checksum error for NV_SPDCHK_RESTRT\n");
 880                         break;
 881
 882                 case MEM_ERROR_NO_CHIPSELECT:
 883                         printk(BIOS_DEBUG, "No chipselects found\n");
 884                         break;
 885
 886                 case MEM_ERROR_UNSUPPORTED_333MHZ_UDIMM:
 887                         printk(BIOS_DEBUG, "Unbuffered dimm is not supported at 333MHz\n");
 888                         break;
 889
 890                 case MEM_ERROR_WL_PRE_OUT_OF_RANGE:
 891                         printk(BIOS_DEBUG, "Returned PRE value during write levelizzation was out of range\n");
 892                         break;
 893
 894                 case CPU_ERROR_BRANDID_HEAP_NOT_AVAILABLE:
 895                         printk(BIOS_DEBUG, "No heap is allocated for BrandId structure\n");
 896                         break;
 897
 898                 case CPU_ERROR_MICRO_CODE_PATCH_IS_NOT_LOADED:
 899                         printk(BIOS_DEBUG, "Unable to load micro code patch\n");
 900                         break;
 901
 902                 case CPU_ERROR_PSTATE_HEAP_NOT_AVAILABLE:
 903                         printk(BIOS_DEBUG, "No heap is allocated for the Pstate structure\n");
 904                         break;
 905
 906 /*
 907                 case CPU_ERROR_PM_NB_PSTATE_MISMATCH:
 908                         printk(BIOS_DEBUG, "NB P-state indicated by Index was disabled due to mismatch between processors\n");
 909                         break;
 910 */
 911
 912                 case CPU_EVENT_EXECUTION_CACHE_ALLOCATION_ERROR:
 913                         printk(BIOS_DEBUG, "Allocation rule number that has been violated:");
 914                         if ((event->EventInfo & 0x000000FF) == 0x04) {
 915                                 printk(BIOS_DEBUG, "AGESA_REGION_NOT_ALIGNED_ON_BOUNDARY\n");
 916                         } else if ((event->EventInfo & 0x000000FF) == 0x05) {
 917                                 printk(BIOS_DEBUG, "AGESA_START_ADDRESS_LESS_D0000\n");
 918                         } else if ((event->EventInfo & 0x000000FF) == 0x06) {
 919                                 printk(BIOS_DEBUG, "AGESA_THREE_CACHE_REGIONS_ABOVE_1MB\n");
 920                         } else if ((event->EventInfo & 0x000000FF) == 0x07) {
 921                                 printk(BIOS_DEBUG, "AGESA_DEALLOCATE_CACHE_REGIONS\n");
 922                         }
 923                         printk(BIOS_DEBUG, "cache region index:%lx, start:%lx size:%lx\n",
 924                                         event->DataParam1,
 925                                         event->DataParam2,
 926                                         event->DataParam3);
 927                         break;
 928
 929                 case HT_EVENT_COH_NO_TOPOLOGY:
 930                         printk(BIOS_DEBUG, "no Matching Topology was found during coherent initializatio TotalHtNodes: %lx\n",
 931                                         event->DataParam1);
 932                         break;
 933
 934                 case HT_EVENT_NCOH_BUID_EXCEED:
 935                         printk(BIOS_DEBUG, "there is a limit of 32 unit IDs per chain Socket%lx Link%lx Depth%lx"
 936                                         "Current BUID: %lx, Unit Count: %lx\n",
 937                                         event->DataParam1,
 938                                         event->DataParam2,
 939                                         event->DataParam3,
 940                                         event->DataParam4 >> 16,
 941                                         event->DataParam4 & 0x0000FFFF);
 942                         break;
 943
 944                  case HT_EVENT_NCOH_BUS_MAX_EXCEED:
 945                         printk(BIOS_DEBUG, "maximum auto bus limit exceeded, Socket %lx Link %lx Bus %lx\n",
 946                                         event->DataParam1,
 947                                         event->DataParam2,
 948                                         event->DataParam3);
 949                         break;
 950
 951                 case HT_EVENT_NCOH_CFG_MAP_EXCEED:
 952                         printk(BIOS_DEBUG, "there is a limit of four non-coherent chains, Socket %lx Link %lx\n",
 953                                         event->DataParam1,
 954                                         event->DataParam2);
 955                         break;
 956
 957                 case HT_EVENT_NCOH_DEVICE_FAILED:
 958                         printk(BIOS_DEBUG, "after assigning an IO Device an ID, it does not respond at the new ID"
 959                                         "Socket %lx Link %lx Depth %lx DeviceID %lx\n",
 960                                         event->DataParam1,
 961                                         event->DataParam2,
 962                                         event->DataParam3,
 963                                         event->DataParam4);
 964                 default:
 965                         break;
 966         }
 967 }
 968 /**
 969  *
 970  */
 971 static void agesa_critical(EVENT_PARAMS *event)
 972 {
 973         switch (event->EventInfo) {
 974                 case MEM_ERROR_HEAP_ALLOCATE_FOR_DMI_TABLE_DDR3:
 975                         printk(BIOS_DEBUG, "Socket: %lx, Heap allocation error for DMI table for DDR3\n",
 976                                         event->DataParam1);
 977                         break;
 978
 979                 case MEM_ERROR_HEAP_ALLOCATE_FOR_DMI_TABLE_DDR2:
 980                         printk(BIOS_DEBUG, "Socket: %lx, Heap allocation error for DMI table for DDR2\n",
 981                                         event->DataParam1);
 982                         break;
 983
 984                 case MEM_ERROR_UNSUPPORTED_DIMM_CONFIG:
 985                         printk(BIOS_DEBUG, "Socket: %lx, Dimm population is not supported\n",
 986                                         event->DataParam1);
 987                         break;
 988
 989                 case HT_EVENT_COH_PROCESSOR_TYPE_MIX:
 990                         printk(BIOS_DEBUG, "Socket %lx Link %lx TotalSockets %lx, HT_EVENT_COH_PROCESSOR_TYPE_MIX \n",
 991                                         event->DataParam1,
 992                                         event->DataParam2,
 993                                         event->DataParam3);
 994                         break;
 995
 996                 case HT_EVENT_COH_MPCAP_MISMATCH:
 997                         printk(BIOS_DEBUG, "Socket %lx Link %lx MpCap %lx TotalSockets %lx, HT_EVENT_COH_MPCAP_MISMATCH\n",
 998                                         event->DataParam1,
 999                                         event->DataParam2,
1000                                         event->DataParam3,
1001                                         event->DataParam4);
1002                 default:
1003                         break;
1004         }
1005 }
1006
1007 /**
1008  *
1009  */
1010 static void agesa_fatal(EVENT_PARAMS *event)
1011 {
1012
1013         switch (event->EventInfo >> 24) {
1014                 case 0x04:
1015                         printk(BIOS_DEBUG, "Memory: Socket %lx Dct %lx Channel%lx ",
1016                                         event->DataParam1,
1017                                         event->DataParam2,
1018                                         event->DataParam3);
1019                         break;
1020
1021                 case 0x08:
1022                         printk(BIOS_DEBUG, "Processor: ");
1023                         break;
1024
1025                 case 0x10:
1026                         printk(BIOS_DEBUG, "Hyper Transport: ");
1027                         break;
1028
1029                 default:
1030                         break;
1031         }
1032
1033         switch (event->EventInfo) {
1034                 case MEM_ERROR_MINIMUM_MODE:
1035                         printk(BIOS_DEBUG, "Running in minimum mode\n");
1036                         break;
1037
1038                 case MEM_ERROR_MODULE_TYPE_MISMATCH_DIMM:
1039                         printk(BIOS_DEBUG, "DIMM modules are missmatched\n");
1040                         break;
1041
1042                 case MEM_ERROR_NO_DIMM_FOUND_ON_SYSTEM:
1043                         printk(BIOS_DEBUG, "No DIMMs have been foun\n");
1044                         break;
1045
1046                 case MEM_ERROR_MISMATCH_DIMM_CLOCKS:
1047                         printk(BIOS_DEBUG, "DIMM clocks miss-matched\n");
1048                         break;
1049
1050                 case MEM_ERROR_NO_CYC_TIME:
1051                         printk(BIOS_DEBUG, "No cycle time found\n");
1052                         break;
1053                 case MEM_ERROR_HEAP_ALLOCATE_DYN_STORING_OF_TRAINED_TIMINGS:
1054                         printk(BIOS_DEBUG, "Heap allocation error with dynamic storing of trained timings\n");
1055                         break;
1056
1057                 case MEM_ERROR_HEAP_ALLOCATE_FOR_DCT_STRUCT_AND_CH_DEF_STRUCTs:
1058                         printk(BIOS_DEBUG, "Heap allocation error for DCT_STRUCT and CH_DEF_STRUCT\n");
1059                         break;
1060
1061                 case MEM_ERROR_HEAP_ALLOCATE_FOR_REMOTE_TRAINING_ENV:
1062                         printk(BIOS_DEBUG, "Heap allocation error with REMOTE_TRAINING_ENV\n");
1063                         break;
1064
1065                 case MEM_ERROR_HEAP_ALLOCATE_FOR_SPD:
1066                         printk(BIOS_DEBUG, "Heap allocation error for SPD data\n");
1067                         break;
1068
1069                 case MEM_ERROR_HEAP_ALLOCATE_FOR_RECEIVED_DATA:
1070                         printk(BIOS_DEBUG, "Heap allocation error for RECEIVED_DATA during parallel training\n");
1071                         break;
1072
1073                 case MEM_ERROR_HEAP_ALLOCATE_FOR_S3_SPECIAL_CASE_REGISTERS:
1074                         printk(BIOS_DEBUG, "Heap allocation error for S3 \"SPECIAL_CASE_REGISTER\"\n");
1075                         break;
1076
1077                 case MEM_ERROR_HEAP_ALLOCATE_FOR_TRAINING_DATA:
1078                         printk(BIOS_DEBUG, "Heap allocation error for Training Data\n");
1079                         break;
1080
1081                 case MEM_ERROR_HEAP_ALLOCATE_FOR_IDENTIFY_DIMM_MEM_NB_BLOCK:
1082                         printk(BIOS_DEBUG, "Heap allocation error for  DIMM Identify \"MEM_NB_BLOCK\"\n");
1083                         break;
1084
1085                 case MEM_ERROR_NO_CONSTRUCTOR_FOR_IDENTIFY_DIMM:
1086                         printk(BIOS_DEBUG, "No Constructor for DIMM Identify\n");
1087                         break;
1088
1089                 case MEM_ERROR_VDDIO_UNSUPPORTED:
1090                         printk(BIOS_DEBUG, "VDDIO of the dimms on the board is not supported\n");
1091                         break;
1092
1093                 case CPU_EVENT_PM_ALL_PSTATE_OVERCURRENT:
1094                         printk(BIOS_DEBUG, "Socket: %lx, All PStates exceeded the motherboard current limit on specified socket\n",
1095                                 event->DataParam1);
1096                         break;
1097
1098                 default:
1099                         break;
1100         }
1101 }
1102
1103 /**
1104  *
1105  * Interprte the agesa event log to an user readable string
1106  */
1107 static void interpret_agesa_eventlog(EVENT_PARAMS *event)
1108 {
1109         switch (event->EventClass) {
1110                 case AGESA_BOUNDS_CHK:
1111                         agesa_bound_check(event);
1112                         break;
1113
1114                 case AGESA_ALERT:
1115                         agesa_alert(event);
1116                         break;
1117
1118                 case AGESA_WARNING:
1119                         agesa_warning(event);
1120                         break;
1121
1122                 case AGESA_ERROR:
1123                         agesa_error(event);
1124                         break;
1125
1126                 case AGESA_CRITICAL:
1127                         agesa_critical(event);
1128                         break;
1129
1130                 case AGESA_FATAL:
1131                         agesa_fatal(event);
1132                         break;
1133
1134                 default:
1135                         break;
1136         }
1137 }
1138
1139 /**
1140  * @param  HeapStatus -the current HeapStatus
1141  */
1142 UINT32 agesawrapper_amdreadeventlog(UINT8 HeapStatus)
1143 {
1144         AGESA_STATUS Status;
1145         EVENT_PARAMS AmdEventParams;
1146
1147         LibAmdMemFill(&AmdEventParams,
1148                         0,
1149                         sizeof(EVENT_PARAMS),
1150                         &(AmdEventParams.StdHeader));
1151
1152         AmdEventParams.StdHeader.AltImageBasePtr = 0;
1153         AmdEventParams.StdHeader.CalloutPtr = NULL;
1154         AmdEventParams.StdHeader.Func = 0;
1155         AmdEventParams.StdHeader.ImageBasePtr = 0;
1156         /* I have to know the current HeapStatus to Locate the EventLogHeapPointer */
1157         AmdEventParams.StdHeader.HeapStatus = HeapStatus;
1158         Status = AmdReadEventLog(&AmdEventParams);
1159         while (AmdEventParams.EventClass != 0) {
1160                 printk(BIOS_DEBUG,"\nEventLog:  EventClass = %lx, EventInfo = %lx.\n",AmdEventParams.EventClass,AmdEventParams.EventInfo);
1161                 printk(BIOS_DEBUG,"  Param1 = %lx, Param2 = %lx.\n",AmdEventParams.DataParam1,AmdEventParams.DataParam2);
1162                 printk(BIOS_DEBUG,"  Param3 = %lx, Param4 = %lx.\n",AmdEventParams.DataParam3,AmdEventParams.DataParam4);
1163                 interpret_agesa_eventlog(&AmdEventParams);
1164                 Status = AmdReadEventLog(&AmdEventParams);
1165         }
1166
1167         return (UINT32)Status;
1168 }
1169