2 * This file is part of the coreboot project.
4 * Copyright (C) 2010 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #ifndef _SB700_EARLY_SETUP_C_
21 #define _SB700_EARLY_SETUP_C_
26 #include <arch/romcc_io.h>
27 #include <console/console.h>
28 #include <cpu/x86/msr.h>
37 static void pmio_write(u8 reg, u8 value)
40 outb(value, PM_INDEX + 1);
43 static u8 pmio_read(u8 reg)
46 return inb(PM_INDEX + 1);
49 static void sb700_acpi_init(void)
52 pmio_write(0x20, ACPI_PM_EVT_BLK & 0xFF);
53 pmio_write(0x21, ACPI_PM_EVT_BLK >> 8);
54 pmio_write(0x22, ACPI_PM1_CNT_BLK & 0xFF);
55 pmio_write(0x23, ACPI_PM1_CNT_BLK >> 8);
56 pmio_write(0x24, ACPI_PM_TMR_BLK & 0xFF);
57 pmio_write(0x25, ACPI_PM_TMR_BLK >> 8);
58 pmio_write(0x28, ACPI_GPE0_BLK & 0xFF);
59 pmio_write(0x29, ACPI_GPE0_BLK >> 8);
61 /* CpuControl is in \_PR.CPU0, 6 bytes */
62 pmio_write(0x26, ACPI_CPU_CONTROL & 0xFF);
63 pmio_write(0x27, ACPI_CPU_CONTROL >> 8);
65 pmio_write(0x2A, 0); /* AcpiSmiCmdLo */
66 pmio_write(0x2B, 0); /* AcpiSmiCmdHi */
68 pmio_write(0x2C, ACPI_PMA_CNT_BLK & 0xFF);
69 pmio_write(0x2D, ACPI_PMA_CNT_BLK >> 8);
71 pmio_write(0x0E, 1<<3 | 0<<2); /* AcpiDecodeEnable, When set, SB uses
72 * the contents of the PM registers at
73 * index 20-2B to decode ACPI I/O address.
74 * AcpiSmiEn & SmiCmdEn*/
75 pmio_write(0x10, 1<<1 | 1<<3| 1<<5); /* RTC_En_En, TMR_En_En, GBL_EN_EN */
76 word = inl(ACPI_PM1_CNT_BLK);
78 outl(word, ACPI_PM1_CNT_BLK); /* set SCI_EN */
81 /* RPR 2.28: Get SB ASIC Revision. */
82 static u8 set_sb700_revision(void)
85 u8 rev_id, enable_14Mhz, byte;
88 /* if (rev != 0) return rev; */
90 dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0);
92 if (dev == PCI_DEV_INVALID) {
93 die("SMBUS controller not found\n");
96 rev_id = pci_read_config8(dev, 0x08);
99 enable_14Mhz = (pmio_read(0x53) >> 6) & 1;
100 if (enable_14Mhz == 0x0)
101 rev = 0x11; /* A11 */
102 else if (enable_14Mhz == 0x1) {
103 /* This happens, if does, only once. So later if we need to get
104 * the revision ID, we don't have to make such a big function.
105 * We just get reg 0x8 in smbus dev. 0x39 is A11, 0x3A is A12. */
107 byte = pci_read_config8(dev, 0x40);
109 pci_write_config8(dev, 0x40, byte);
111 pci_write_config8(dev, 0x08, 0x3A); /* Change 0x39 to 0x3A. */
114 pci_write_config8(dev, 0x40, byte);
116 } else if (rev_id == 0x3A) { /* A12 will be 0x3A after BIOS is initialized */
118 } else if (rev_id == 0x3C) {
120 } else if (rev_id == 0x3D) {
123 die("It is not SB700 or SB710\n");
128 /***************************************
129 * Legacy devices are mapped to LPC space.
132 * ACPI Micro-controller port
133 * This function does not change port 0x80 decoding.
134 * Console output through any port besides 0x3f8 is unsupported.
135 * If you use FWH ROMs, you have to setup IDSEL.
136 ***************************************/
137 void sb7xx_51xx_lpc_init(void)
143 dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); /* SMBUS controller */
144 /* NOTE: Set BootTimerDisable, otherwise it would keep rebooting!!
145 * This bit has no meaning if debug strap is not enabled. So if the
146 * board keeps rebooting and the code fails to reach here, we could
147 * disable the debug strap first. */
148 reg32 = pci_read_config32(dev, 0x4C);
150 pci_write_config32(dev, 0x4C, reg32);
152 /* Enable lpc controller */
153 reg32 = pci_read_config32(dev, 0x64);
155 pci_write_config32(dev, 0x64, reg32);
157 #if CONFIG_SOUTHBRIDGE_AMD_SP5100
159 dev = pci_locate_device(PCI_ID(0x1002, 0x439d), 0); /* LPC Controller */
160 reg8 = pci_read_config8(dev, 0xBB);
161 reg8 |= 1 << 2 | 1 << 3 | 1 << 6 | 1 << 7;
163 pci_write_config8(dev, 0xBB, reg8);
166 dev = pci_locate_device(PCI_ID(0x1002, 0x439d), 0); /* LPC Controller */
167 /* Decode port 0x3f8-0x3ff (Serial 0) */
168 // XXX Serial port decode on LPC is hardcoded to 0x3f8
169 reg8 = pci_read_config8(dev, 0x44);
171 #if CONFIG_SOUTHBRIDGE_AMD_SP5100
172 #if CONFIG_TTYS0_BASE == 0x2f8
176 pci_write_config8(dev, 0x44, reg8);
178 /* Decode port 0x60 & 0x64 (PS/2 keyboard) and port 0x62 & 0x66 (ACPI)*/
179 reg8 = pci_read_config8(dev, 0x47);
180 reg8 |= (1 << 5) | (1 << 6);
181 pci_write_config8(dev, 0x47, reg8);
183 /* Enable PrefetchEnSPIFromHost to speed up SPI flash read (does not affect LPC) */
184 reg8 = pci_read_config8(dev, 0xbb);
186 pci_write_config8(dev, 0xbb, reg8);
189 reg8 = pci_read_config8(dev, 0x48);
190 /* Decode ports 0x2e-0x2f, 0x4e-0x4f (SuperI/O configuration) */
191 reg8 |= (1 << 1) | (1 << 0);
192 /* Decode port 0x70-0x73 (RTC) */
194 pci_write_config8(dev, 0x48, reg8);
197 void sb7xx_51xx_enable_wideio(u8 wio_index, u16 base)
199 /* TODO: Now assume wio_index=0 */
203 dev = pci_locate_device(PCI_ID(0x1002, 0x439d), 0); /* LPC Controller */
204 pci_write_config32(dev, 0x64, base);
205 reg8 = pci_read_config8(dev, 0x48);
207 pci_write_config8(dev, 0x48, reg8);
210 void sb7xx_51xx_disable_wideio(u8 wio_index)
212 /* TODO: Now assume wio_index=0 */
216 dev = pci_locate_device(PCI_ID(0x1002, 0x439d), 0); /* LPC Controller */
217 pci_write_config32(dev, 0x64, 0);
218 reg8 = pci_read_config8(dev, 0x48);
220 pci_write_config8(dev, 0x48, reg8);
223 /* what is its usage? */
224 u32 __attribute__ ((weak)) get_sbdn(u32 bus)
228 /* Find the device. */
229 dev = pci_locate_device_on_bus(PCI_ID(0x1002, 0x4385), bus);
230 return (dev >> 15) & 0x1f;
233 static u8 dual_core(void)
235 return (pci_read_config32(PCI_DEV(0, 0x18, 3), 0xE8) & (0x3<<12)) != 0;
239 * RPR 2.4 C-state and VID/FID change for the K8 platform.
241 void __attribute__((weak)) enable_fid_change_on_sb(u32 sbbusn, u32 sbdn)
244 byte = pmio_read(0x9a);
250 pmio_write(0x9a, byte);
252 byte = pmio_read(0x8f);
255 pmio_write(0x8f, byte);
257 pmio_write(0x8b, 0x01); /* TODO: if the HT Link is 200 MHz, it is 0x0A. It doesnt often happen. */
258 pmio_write(0x8a, 0x90);
260 pmio_write(0x88, 0x10);
262 byte = pmio_read(0x7c);
264 pmio_write(0x7c, byte);
266 /* Must be 0 for K8 platform. */
267 byte = pmio_read(0x68);
269 pmio_write(0x68, byte);
270 /* Must be 0 for K8 platform. */
271 byte = pmio_read(0x8d);
273 pmio_write(0x8d, byte);
275 byte = pmio_read(0x61);
277 pmio_write(0x61, byte);
279 byte = pmio_read(0x42);
281 pmio_write(0x42, byte);
283 pmio_write(0x89, 0x10);
285 /* Toggle the LDT_STOP# during FID/VID Change, this bit is documented
287 While here, enable C states too
289 pmio_write(0x67, 0x6);
292 void sb7xx_51xx_pci_port80(void)
298 dev = pci_locate_device(PCI_ID(0x1002, 0x4384), 0);
300 /* Chip Control: Enable subtractive decoding */
301 byte = pci_read_config8(dev, 0x40);
303 pci_write_config8(dev, 0x40, byte);
305 /* Misc Control: Enable subtractive decoding if 0x40 bit 5 is set */
306 byte = pci_read_config8(dev, 0x4B);
308 pci_write_config8(dev, 0x4B, byte);
310 /* The same IO Base and IO Limit here is meaningful because we set the
311 * bridge to be subtractive. During early setup stage, we have to make
312 * sure that data can go through port 0x80.
314 /* IO Base: 0xf000 */
315 byte = pci_read_config8(dev, 0x1C);
317 pci_write_config8(dev, 0x1C, byte);
319 /* IO Limit: 0xf000 */
320 byte = pci_read_config8(dev, 0x1D);
322 pci_write_config8(dev, 0x1D, byte);
324 /* PCI Command: Enable IO response */
325 byte = pci_read_config8(dev, 0x04);
327 pci_write_config8(dev, 0x04, byte);
330 dev = pci_locate_device(PCI_ID(0x1002, 0x439D), 0);
332 byte = pci_read_config8(dev, 0x4A);
333 byte &= ~(1 << 5); /* disable lpc port 80 */
334 pci_write_config8(dev, 0x4A, byte);
337 void sb7xx_51xx_lpc_port80(void)
343 /* Enable LPC controller */
344 dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0);
345 reg32 = pci_read_config32(dev, 0x64);
346 reg32 |= 0x00100000; /* lpcEnable */
347 pci_write_config32(dev, 0x64, reg32);
349 /* Enable port 80 LPC decode in pci function 3 configuration space. */
350 dev = pci_locate_device(PCI_ID(0x1002, 0x439d), 0);
351 byte = pci_read_config8(dev, 0x4a);
352 byte |= 1 << 5; /* enable port 80 */
353 pci_write_config8(dev, 0x4a, byte);
356 /* sbDevicesPorInitTable */
357 static void sb700_devices_por_init(void)
361 #if CONFIG_SOUTHBRIDGE_AMD_SP5100
365 printk(BIOS_INFO, "sb700_devices_por_init()\n");
366 /* SMBus Device, BDF:0-20-0 */
367 printk(BIOS_INFO, "sb700_devices_por_init(): SMBus Device, BDF:0-20-0\n");
368 dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0);
370 if (dev == PCI_DEV_INVALID) {
371 die("SMBUS controller not found\n");
374 printk(BIOS_INFO, "SMBus controller enabled, sb revision is A%x\n",
375 set_sb700_revision());
377 /* sbPorAtStartOfTblCfg */
378 /* Set A-Link bridge access address. This address is set at device 14h, function 0, register 0xf0.
379 * This is an I/O address. The I/O address must be on 16-byte boundry. */
380 pci_write_config32(dev, 0xf0, AB_INDX);
382 /* To enable AB/BIF DMA access, a specific register inside the BIF register space needs to be configured first. */
383 /* 4.3:Enables the SB700 to send transactions upstream over A-Link Express interface. */
384 axcfg_reg(0x04, 1 << 2, 1 << 2);
385 axindxc_reg(0x21, 0xff, 0);
387 /* 2.5:Enabling Non-Posted Memory Write for the K8 Platform */
388 axindxc_reg(0x10, 1 << 9, 1 << 9);
389 /* END of sbPorAtStartOfTblCfg */
391 /* sbDevicesPorInitTables */
392 /* set smbus iobase */
393 pci_write_config32(dev, 0x90, SMBUS_IO_BASE | 1);
395 /* enable smbus controller interface */
396 byte = pci_read_config8(dev, 0xd2);
398 pci_write_config8(dev, 0xd2, byte);
401 pci_write_config8(dev, 0x40, 0x44);
403 /* Enable ISA Address 0-960K decoding */
404 pci_write_config8(dev, 0x48, 0x0f);
406 /* Enable ISA Address 0xC0000-0xDFFFF decode */
407 pci_write_config8(dev, 0x49, 0xff);
409 /* Enable decode cycles to IO C50, C51, C52 GPM controls. */
410 byte = pci_read_config8(dev, 0x41);
413 pci_write_config8(dev, 0x41, byte);
415 /* Legacy DMA Prefetch Enhancement, CIM masked it. */
416 /* pci_write_config8(dev, 0x43, 0x1); */
418 /* Disabling Legacy USB Fast SMI# */
419 byte = pci_read_config8(dev, 0x62);
421 pci_write_config8(dev, 0x62, byte);
423 /* Features Enable */
424 pci_write_config32(dev, 0x64, 0x829E79BF); /* bit10: Enables the HPET interrupt. */
426 /* SerialIrq Control */
427 pci_write_config8(dev, 0x69, 0x90);
429 /* Test Mode, PCIB_SReset_En Mask is set. */
430 pci_write_config8(dev, 0x6c, 0x20);
432 /* IO Address Enable, CIM set 0x78 only and masked 0x79. */
433 /*pci_write_config8(dev, 0x79, 0x4F); */
434 pci_write_config8(dev, 0x78, 0xFF);
436 /* Set smbus iospace enable, I don't know why write 0x04 into reg5 that is reserved */
437 pci_write_config16(dev, 0x4, 0x0407);
439 /* clear any lingering errors, so the transaction will run */
440 outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
442 /* IDE Device, BDF:0-20-1 */
443 printk(BIOS_INFO, "sb700_devices_por_init(): IDE Device, BDF:0-20-1\n");
444 dev = pci_locate_device(PCI_ID(0x1002, 0x439C), 0);
445 /* Disable prefetch */
446 byte = pci_read_config8(dev, 0x63);
448 pci_write_config8(dev, 0x63, byte);
450 /* LPC Device, BDF:0-20-3 */
451 printk(BIOS_INFO, "sb700_devices_por_init(): LPC Device, BDF:0-20-3\n");
452 dev = pci_locate_device(PCI_ID(0x1002, 0x439D), 0);
454 pci_write_config8(dev, 0x40, 0x04);
456 /* IO Port Decode Enable */
457 pci_write_config8(dev, 0x44, 0xFF);
458 pci_write_config8(dev, 0x45, 0xFF);
459 pci_write_config8(dev, 0x46, 0xC3);
460 pci_write_config8(dev, 0x47, 0xFF);
462 // TODO: This has already been done(?)
463 /* IO/Mem Port Decode Enable, I don't know why CIM disable some ports.
464 * Disable LPC TimeOut counter, enable SuperIO Configuration Port (2e/2f),
465 * Alternate Super I/O Configuration Port (4e/4f), Wide Generic IO Port (64/65). */
466 byte = pci_read_config8(dev, 0x48);
467 byte |= (1 << 1) | (1 << 0); /* enable Super IO config port 2e-2h, 4e-4f */
468 byte |= 1 << 6; /* enable for RTC I/O range */
469 pci_write_config8(dev, 0x48, byte);
470 pci_write_config8(dev, 0x49, 0xFF);
471 /* Enable 0x480-0x4bf, 0x4700-0x470B */
472 byte = pci_read_config8(dev, 0x4A);
473 byte |= ((1 << 1) + (1 << 6)); /*0x42, save the configuraion for port 0x80. */
474 pci_write_config8(dev, 0x4A, byte);
476 /* Enable Tpm12_en and Tpm_legacy. I don't know what is its usage and copied from CIM. */
477 pci_write_config8(dev, 0x7C, 0x05);
479 /* P2P Bridge, BDF:0-20-4, the configuration of the registers in this dev are copied from CIM,
481 printk(BIOS_INFO, "sb700_devices_por_init(): P2P Bridge, BDF:0-20-4\n");
482 dev = pci_locate_device(PCI_ID(0x1002, 0x4384), 0);
484 /* Arbiter enable. */
485 pci_write_config8(dev, 0x43, 0xff);
487 /* Set PCDMA request into hight priority list. */
488 /* pci_write_config8(dev, 0x49, 0x1) */ ;
490 pci_write_config8(dev, 0x40, 0x26);
492 pci_write_config8(dev, 0x0d, 0x40);
493 pci_write_config8(dev, 0x1b, 0x40);
494 /* Enable PCIB_DUAL_EN_UP will fix potential problem with PCI cards. */
495 pci_write_config8(dev, 0x50, 0x01);
497 #if CONFIG_SOUTHBRIDGE_AMD_SP5100
498 /* SP5100 default SATA mode is RAID5 MODE */
499 dev = pci_locate_device(PCI_ID(0x1002, 0x4393), 0);
500 /* Set SATA Operation Mode, Set to IDE mode */
501 byte = pci_read_config8(dev, 0x40);
503 pci_write_config8(dev, 0x40, byte);
506 pci_write_config32(dev, 0x8, dword);
508 /* set SATA Device ID writable */
509 dword = pci_read_config32(dev, 0x40);
511 pci_write_config32(dev, 0x40, dword);
513 /* set Device ID accommodate with IDE emulation mode configuration*/
514 pci_write_config32(dev, 0x0, 0x43901002);
516 /* rpr v2.13 4.17 Reset CPU on Sync Flood */
517 abcfg_reg(0x10050, 1 << 2, 1 << 2);
520 /* SATA Device, BDF:0-17-0, Non-Raid-5 SATA controller */
521 printk(BIOS_INFO, "sb700_devices_por_init(): SATA Device, BDF:0-18-0\n");
522 dev = pci_locate_device(PCI_ID(0x1002, 0x4390), 0);
524 /*PHY Global Control*/
525 pci_write_config16(dev, 0x86, 0x2C00);
528 /* sbPmioPorInitTable, Pre-initializing PMIO register space
529 * The power management (PM) block is resident in the PCI/LPC/ISA bridge.
530 * The PM regs are accessed via IO mapped regs 0xcd6 and 0xcd7.
531 * The index address is first programmed into IO reg 0xcd6.
532 * Read or write values are accessed through IO reg 0xcd7.
534 static void sb700_pmio_por_init(void)
538 printk(BIOS_INFO, "sb700_pmio_por_init()\n");
539 /* K8KbRstEn, KB_RST# control for K8 system. */
540 byte = pmio_read(0x66);
542 pmio_write(0x66, byte);
544 /* RPR2.31 PM_TURN_OFF_MSG during ASF Shutdown. */
545 if (get_sb700_revision(pci_locate_device(PCI_ID(0x1002, 0x4385), 0)) <= 0x12) {
546 byte = pmio_read(0x65);
548 pmio_write(0x65, byte);
550 byte = pmio_read(0x75);
553 pmio_write(0x75, byte);
555 byte = pmio_read(0x52);
558 pmio_write(0x52, byte);
560 byte = pmio_read(0xD7);
562 pmio_write(0xD7, byte);
564 byte = pmio_read(0x65);
566 pmio_write(0x65, byte);
568 byte = pmio_read(0x75);
571 pmio_write(0x75, byte);
573 byte = pmio_read(0x52);
576 pmio_write(0x52, byte);
580 /* Watch Dog Timer Control
581 * Set watchdog time base to 0xfec000f0 to avoid SCSI card boot failure.
582 * But I don't find WDT is enabled in SMBUS 0x41 bit3 in CIM.
584 pmio_write(0x6c, 0xf0);
585 pmio_write(0x6d, 0x00);
586 pmio_write(0x6e, 0xc0);
587 pmio_write(0x6f, 0xfe);
589 /* rpr2.15: Enabling Spread Spectrum */
590 byte = pmio_read(0x42);
592 pmio_write(0x42, byte);
593 /* TODO: Check if it is necessary. IDE reset */
594 byte = pmio_read(0xB2);
596 pmio_write(0xB2, byte);
600 * Add any south bridge setting.
602 static void sb700_pci_cfg(void)
607 /* SMBus Device, BDF:0-20-0 */
608 dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0);
609 /* Enable watchdog decode timer */
610 byte = pci_read_config8(dev, 0x41);
612 pci_write_config8(dev, 0x41, byte);
614 /* Set to 1 to reset USB on the software (such as IO-64 or IO-CF9 cycles)
615 * generated PCIRST#. */
616 byte = pmio_read(0x65);
618 pmio_write(0x65, byte);
620 /* IDE Device, BDF:0-20-1 */
621 dev = pci_locate_device(PCI_ID(0x1002, 0x439C), 0);
622 /* Enable IDE Explicit prefetch, 0x63[0] clear */
623 byte = pci_read_config8(dev, 0x63);
625 pci_write_config8(dev, 0x63, byte);
627 /* LPC Device, BDF:0-20-3 */
628 /* The code below is ported from old chipset. It is not
629 * mentioned in RPR. But I keep them. The registers and the
630 * comments are compatible. */
631 dev = pci_locate_device(PCI_ID(0x1002, 0x439D), 0);
632 /* Enabling LPC DMA function. */
633 byte = pci_read_config8(dev, 0x40);
635 pci_write_config8(dev, 0x40, byte);
636 /* Disabling LPC TimeOut. 0x48[7] clear. */
637 byte = pci_read_config8(dev, 0x48);
639 pci_write_config8(dev, 0x48, byte);
640 /* Disabling LPC MSI Capability, 0x78[1] clear. */
641 byte = pci_read_config8(dev, 0x78);
643 pci_write_config8(dev, 0x78, byte);
645 /* SATA Device, BDF:0-17-0, Non-Raid-5 SATA controller */
646 dev = pci_locate_device(PCI_ID(0x1002, 0x4390), 0);
647 /* rpr7.12 SATA MSI and D3 Power State Capability. */
648 byte = pci_read_config8(dev, 0x40);
650 pci_write_config8(dev, 0x40, byte);
651 if (get_sb700_revision(pci_locate_device(PCI_ID(0x1002, 0x4385), 0)) <= 0x12)
652 pci_write_config8(dev, 0x34, 0x70); /* set 0x61 to 0x70 if S1 is not supported. */
654 pci_write_config8(dev, 0x34, 0x50); /* set 0x61 to 0x50 if S1 is not supported. */
656 pci_write_config8(dev, 0x40, byte);
661 static void sb700_por_init(void)
663 /* sbDevicesPorInitTable + sbK8PorInitTable */
664 sb700_devices_por_init();
666 /* sbPmioPorInitTable + sbK8PmioPorInitTable */
667 sb700_pmio_por_init();
671 * It should be called during early POST after memory detection and BIOS shadowing but before PCI bus enumeration.
673 void sb7xx_51xx_before_pci_init(void)
679 * This function should be called after enable_sb700_smbus().
681 void sb7xx_51xx_early_setup(void)
683 printk(BIOS_INFO, "sb700_early_setup()\n");
688 int s3_save_nvram_early(u32 dword, int size, int nvram_pos)
691 printk(BIOS_DEBUG, "Writing %x of size %d to nvram pos: %d\n", dword, size, nvram_pos);
693 for (i = 0; i<size; i++) {
694 outb(nvram_pos, BIOSRAM_INDEX);
695 outb((dword >>(8 * i)) & 0xff , BIOSRAM_DATA);
702 int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos)
704 u32 data = *old_dword;
706 for (i = 0; i<size; i++) {
707 outb(nvram_pos, BIOSRAM_INDEX);
708 data &= ~(0xff << (i * 8));
709 data |= inb(BIOSRAM_DATA) << (i *8);
713 printk(BIOS_DEBUG, "Loading %x of size %d to nvram pos:%d\n", *old_dword, size,
718 #if CONFIG_HAVE_ACPI_RESUME == 1
719 int acpi_is_wakeup_early(void)
722 tmp = inw(ACPI_PM1_CNT_BLK);
723 printk(BIOS_DEBUG, "IN TEST WAKEUP %x\n", tmp);
724 return (((tmp & (7 << 10)) >> 10) == 3);
728 struct cbmem_entry *get_cbmem_toc(void)
731 int xnvram_pos = 0xfc, xi;
732 for (xi = 0; xi<4; xi++) {
733 outb(xnvram_pos, BIOSRAM_INDEX);
734 xdata &= ~(0xff << (xi * 8));
735 xdata |= inb(BIOSRAM_DATA) << (xi *8);
738 return (struct cbmem_entry *) xdata;