2 * This file is part of the coreboot project.
4 * Copyright (C) 2008 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #include <console/console.h>
21 #include <arch/smp/mpspec.h>
22 #include <device/pci.h>
27 #include <cpu/amd/amdk8_sysconf.h>
29 extern u8 bus_rs690[8];
30 extern u8 bus_sb600[2];
32 extern u32 apicid_sb600;
34 extern u32 sbdn_rs690;
35 extern u32 sbdn_sb600;
37 static void *smp_write_config_table(void *v)
39 struct mp_config_table *mc;
42 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
43 mptable_init(mc, LAPIC_ADDR);
44 smp_write_processors(mc);
47 printk(BIOS_DEBUG, "%s: apic_id=0x%x\n", __func__, apicid_sb600);
49 mptable_write_buses(mc, NULL, &isa_bus);
50 /* I/O APICs: APIC ID Version State Address */
54 dev = dev_find_slot(bus_sb600[0], PCI_DEVFN(sbdn_sb600 + 0x14, 0));
57 res = find_resource(dev, 0x74);
58 smp_write_ioapic(mc, apicid_sb600, 0x20, res->base);
61 mptable_add_isa_interrupts(mc, isa_bus, apicid_sb600, 0);
63 #define PCI_INT(bus, dev, fn, pin) \
64 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb600, (pin))
67 PCI_INT(0x0, 0x13, 0x0, 0x10);
68 PCI_INT(0x0, 0x13, 0x1, 0x11);
69 PCI_INT(0x0, 0x13, 0x2, 0x12);
70 PCI_INT(0x0, 0x13, 0x3, 0x13);
73 PCI_INT(0x0, 0x12, 0x1, 0x16);
76 PCI_INT(0x0, 0x14, 0x0, 0x10);
78 PCI_INT(0x0, 0x14, 0x1, 0x11);
80 PCI_INT(0x0, 0x14, 0x2, 0x12);
82 PCI_INT(0x0, 0x14, 0x3, 0x13);
85 PCI_INT(bus_rs690[1], 0x5, 0x0, 0x12);
86 PCI_INT(bus_rs690[1], 0x5, 0x1, 0x13);
89 PCI_INT(0x2, 0x00, 0x00, 0x10);
90 PCI_INT(0x2, 0x00, 0x01, 0x11);
91 PCI_INT(0x2, 0x00, 0x02, 0x12);
92 PCI_INT(0x2, 0x00, 0x03, 0x13);
95 PCI_INT(0x3, 0x00, 0x00, 0x11);
96 PCI_INT(0x3, 0x00, 0x01, 0x12);
97 PCI_INT(0x3, 0x00, 0x02, 0x13);
98 PCI_INT(0x3, 0x00, 0x03, 0x10);
101 PCI_INT(0x4, 0x00, 0x00, 0x12);
102 PCI_INT(0x4, 0x00, 0x01, 0x13);
103 PCI_INT(0x4, 0x00, 0x02, 0x10);
104 PCI_INT(0x4, 0x00, 0x03, 0x11);
107 PCI_INT(0x5, 0x00, 0x00, 0x13);
108 PCI_INT(0x5, 0x00, 0x01, 0x10);
109 PCI_INT(0x5, 0x00, 0x02, 0x11);
110 PCI_INT(0x5, 0x00, 0x03, 0x12);
113 PCI_INT(bus_sb600[1], 0x7, 0x0, 0x13);
114 PCI_INT(bus_sb600[1], 0x7, 0x1, 0x10);
115 PCI_INT(bus_sb600[1], 0x7, 0x2, 0x11);
116 PCI_INT(bus_sb600[1], 0x7, 0x3, 0x12);
118 /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
119 mptable_lintsrc(mc, isa_bus);
121 /* Compute the checksums */
122 return mptable_finalize(mc);
125 unsigned long write_smp_table(unsigned long addr)
128 v = smp_write_floating_table(addr, 0);
129 return (unsigned long)smp_write_config_table(v);