2 * This file is part of the coreboot project.
4 * Copyright (C) 2010 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #include <console/console.h>
21 #include <device/device.h>
22 #include <device/pci.h>
24 #include <boot/tables.h>
25 #include <cpu/x86/msr.h>
26 #include <cpu/amd/mtrr.h>
27 #include <device/pci_def.h>
28 #include <southbridge/amd/sb700/sb700.h>
29 #include <southbridge/amd/sr5650/cmn.h>
33 void set_pcie_reset(void);
34 void set_pcie_dereset(void);
35 u8 is_dev3_present(void);
37 /* 780 board use this function*/
38 u8 is_dev3_present(void)
44 * TODO: Add the routine info of each PCIE_RESET_L.
45 * TODO: Add the reset of each PCIE_RESET_L.
46 * PCIE_RESET_GPIO1 -> Slot 0
47 * PCIE_RESET_GPIO2 -> On-board NIC Bcm5709
48 * PCIE_RESET_GPIO3 -> TMS
49 * PCIE_RESET_GPIO4 -> Slot 1
50 * PCIE_RESET_GPIO5 -> Slot 2
52 void set_pcie_reset(void)
54 device_t pcie_core_dev;
56 pcie_core_dev = dev_find_slot(0, PCI_DEVFN(0, 0));
57 set_htiu_enable_bits(pcie_core_dev, 0xA8, 0xFFFFFFFF, 0x28282828);
58 set_htiu_enable_bits(pcie_core_dev, 0xA9, 0x000000FF, 0x00000028);
61 void set_pcie_dereset(void)
63 device_t pcie_core_dev;
65 pcie_core_dev = dev_find_slot(0, PCI_DEVFN(0, 0));
66 set_htiu_enable_bits(pcie_core_dev, 0xA8, 0xFFFFFFFF, 0x6F6F6F6F);
67 set_htiu_enable_bits(pcie_core_dev, 0xA9, 0x000000FF, 0x0000006F);
70 /*************************************************
71 * enable the dedicated function in h8scm board.
72 * This function called early than sr5650_enable.
73 *************************************************/
74 static void h8scm_enable(device_t dev)
76 /* Leave it for furture use. */
77 /* struct mainboard_config *mainboard =
78 (struct mainboard_config *)dev->chip_info; */
80 printk(BIOS_INFO, "Mainboard H8SCM Enable. dev=0x%p\n", dev);
84 /* TOP_MEM: the top of DRAM below 4G */
87 (BIOS_INFO, "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n",
88 __func__, msr.lo, msr.hi);
90 /* TOP_MEM2: the top of DRAM above 4G */
91 msr2 = rdmsr(TOP_MEM2);
93 (BIOS_INFO, "%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n",
94 __func__, msr2.lo, msr2.hi);
97 /* get_ide_dma66(); */
100 #if (CONFIG_HAVE_MAINBOARD_RESOURCES == 1)
101 int add_mainboard_resources(struct lb_memory *mem)
107 struct chip_operations mainboard_ops = {
108 CHIP_NAME("AMD H8SCM Mainboard")
109 .enable_dev = h8scm_enable,