2 * This file is part of the coreboot project.
4 * Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me@gmail.com>
6 * This program is free software: you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation, either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
24 * This aims to be a central point for POST codes used throughout coreboot.
25 * All POST codes should be declared here as macros, and post_code() should
26 * be used with the macros instead of hardcoded values. This allows us to
27 * quicly reference POST codes when nothing is working
29 * The format for a POST code macro is
30 * #define POST_WHAT_WE_COMMUNICATE_IS_HAPPENING_WHEN_THIS_CODE_IS_POSTED
31 * Lets's keep it at POST_* instead of POST_CODE_*
33 * This file is also included by early assembly files. Only use #define s;
34 * no function prototypes allowed here
37 * Please document any and all post codes using Doxygen style comments. We
38 * want to be able to generate a verbose enough documentation that is useful
39 * during debugging. Failure to do so will result in your patch being rejected
40 * without any explanation or effort on part of the maintainers.
47 * \brief Entry into 'crt0.s'. reset code jumps to here
49 * First instruction that gets executed after the reset vector jumps.
50 * This indicates that the reset vector points to the correct code segment.
52 #define POST_RESET_VECTOR_CORRECT 0x01
55 * \brief Entry into protected mode
57 * Preparing to enter protected mode. This is POSTed right before changing to
60 #define POST_ENTER_PROTECTED_MODE 0x10
63 * \brief Start copying coreboot to RAM with decompression if compressed
65 * POSTed before ramstage is about to be loaded into memory
67 #define POST_PREPARE_RAMSTAGE 0x11
70 * \brief Copy/decompression finished; jumping to RAM
72 * This is called after ramstage is loaded in memory, and before
73 * the code jumps there. This represents the end of romstage.
75 #define POST_RAMSTAGE_IS_PREPARED 0x12
79 * \brief Entry into c_start
81 * c_start.S is the first code executing in ramstage.
83 #define POST_ENTRY_C_START 0x13
86 * \brief Entry into coreboot in hardwaremain (RAM)
88 * This is the first call in hardwaremain.c. If this code is POSTed, then
89 * ramstage has succesfully loaded and started executing.
91 #define POST_ENTRY_RAMSTAGE 0x80
94 * \brief Console is initialized
96 * The console is initialized and is ready for usage
98 #define POST_CONSOLE_READY 0x39
101 * \brief Console boot message succeeded
103 * First console message has been succesfully sent through the console backend
106 #define POST_CONSOLE_BOOT_MSG 0x40
109 * \brief Devices have been enumerated
111 * Bus scan, and device enumeration has completed.
113 #define POST_DEVICE_ENUMERATION_COMPLETE 0x66
116 * \brief Devices have been configured
118 * Device confgration has completed.
120 #define POST_DEVICE_CONFIGURATION_COMPLETE 0x88
123 * \brief Devices have been enabled
125 * Devices have been enabled.
127 #define POST_DEVICES_ENABLED 0x89
130 * \brief Entry into elf boot
132 * This POST code is called right before invoking jmp_to_elf_entry()
133 * jmp_to_elf_entry() invokes the payload, and should never return
135 #define POST_ENTER_ELF_BOOT 0xf8
138 * \brief Jumping to payload
140 * Called right before jumping to a payload. If the boot sequence stops with
141 * this code, chances are the payload freezes.
143 #define POST_JUMPING_TO_PAYLOAD 0xf3
146 * \brief Not supposed to get here
148 * A function that should not have returned, returned
150 * Check the console output for details.
152 #define POST_DEAD_CODE 0xee
155 * \brief Pre call to hardwaremain()
157 * POSTed right before hardwaremain is called from c_start.S
158 * TODO: Change this code to a lower number
160 #define POST_PRE_HARDWAREMAIN 0xfe
163 * \brief Elfload fail or die() called
165 * Coreboot was not able to load the payload, no payload was detected
166 * or die() was called.
168 * If this code appears before entering ramstage, then most likely
169 * ramstage is corrupted, and reflashing of the ROM chip is needed.
171 * If this code appears after ramstage, there is a problem with the payload
172 * If the payload was built out-of-tree, check that it was compiled as
175 * Check the console output to see exactly where the failure occured.
177 #define POST_DIE 0xff
181 * The following POST codes are taken from src/include/cpu/amd/geode_post_code.h
182 * They overlap with previous codes, and most are not even used
183 * Some maiboards still require them, but they are deprecated. We want to consolidate
184 * our own POST code structure with the codes above.
186 * standard AMD post definitions for the AMD Geode
188 #define POST_Output_Port (0x080) /* port to write post codes to*/
190 #define POST_preSioInit (0x000)
191 #define POST_clockInit (0x001)
192 #define POST_CPURegInit (0x002)
193 #define POST_UNREAL (0x003)
194 #define POST_CPUMemRegInit (0x004)
195 #define POST_CPUTest (0x005)
196 #define POST_memSetup (0x006)
197 #define POST_memSetUpStack (0x007)
198 #define POST_memTest (0x008)
199 #define POST_shadowRom (0x009)
200 #define POST_memRAMoptimize (0x00A)
201 #define POST_cacheInit (0x00B)
202 #define POST_northBridgeInit (0x00C)
203 #define POST_chipsetInit (0x00D)
204 #define POST_sioTest (0x00E)
205 #define POST_pcATjunk (0x00F)
207 #define POST_intTable (0x010)
208 #define POST_memInfo (0x011)
209 #define POST_romCopy (0x012)
210 #define POST_PLLCheck (0x013)
211 #define POST_keyboardInit (0x014)
212 #define POST_cpuCacheOff (0x015)
213 #define POST_BDAInit (0x016)
214 #define POST_pciScan (0x017)
215 #define POST_optionRomInit (0x018)
216 #define POST_ResetLimits (0x019)
217 #define POST_summary_screen (0x01A)
218 #define POST_Boot (0x01B)
219 #define POST_SystemPreInit (0x01C)
220 #define POST_ClearRebootFlag (0x01D)
221 #define POST_GLIUInit (0x01E)
222 #define POST_BootFailed (0x01F)
224 #define POST_CPU_ID (0x020)
225 #define POST_COUNTERBROKEN (0x021)
226 #define POST_DIFF_DIMMS (0x022)
227 #define POST_WIGGLE_MEM_LINES (0x023)
228 #define POST_NO_GLIU_DESC (0x024)
229 #define POST_CPU_LCD_CHECK (0x025)
230 #define POST_CPU_LCD_PASS (0x026)
231 #define POST_CPU_LCD_FAIL (0x027)
232 #define POST_CPU_STEPPING (0x028)
233 #define POST_CPU_DM_BIST_FAILURE (0x029)
234 #define POST_CPU_FLAGS (0x02A)
235 #define POST_CHIPSET_ID (0x02B)
236 #define POST_CHIPSET_ID_PASS (0x02C)
237 #define POST_CHIPSET_ID_FAIL (0x02D)
238 #define POST_CPU_ID_GOOD (0x02E)
239 #define POST_CPU_ID_FAIL (0x02F)
242 #define P80_PCICFG (0x030)
245 #define P80_PCIIO (0x040)
248 #define P80_PCIMEM (0x050)
251 #define P80_SIO (0x060)
254 #define P80_MEM_SETUP (0x070)
255 #define POST_MEM_SETUP (0x070)
256 #define ERROR_32BIT_DIMMS (0x071)
257 #define POST_MEM_SETUP2 (0x072)
258 #define POST_MEM_SETUP3 (0x073)
259 #define POST_MEM_SETUP4 (0x074)
260 #define POST_MEM_SETUP5 (0x075)
261 #define POST_MEM_ENABLE (0x076)
262 #define ERROR_NO_DIMMS (0x077)
263 #define ERROR_DIFF_DIMMS (0x078)
264 #define ERROR_BAD_LATENCY (0x079)
265 #define ERROR_SET_PAGE (0x07A)
266 #define ERROR_DENSITY_DIMM (0x07B)
267 #define ERROR_UNSUPPORTED_DIMM (0x07C)
268 #define ERROR_BANK_SET (0x07D)
269 #define POST_MEM_SETUP_GOOD (0x07E)
270 #define POST_MEM_SETUP_FAIL (0x07F)
272 #define POST_UserPreInit (0x080)
273 #define POST_UserPostInit (0x081)
274 #define POST_Equipment_check (0x082)
275 #define POST_InitNVRAMBX (0x083)
276 #define POST_NoPIRTable (0x084)
277 #define POST_ChipsetFingerPrintPass (0x085)
278 #define POST_ChipsetFingerPrintFail (0x086)
279 #define POST_CPU_IM_TAG_BIST_FAILURE (0x087)
280 #define POST_CPU_IM_DATA_BIST_FAILURE (0x088)
281 #define POST_CPU_FPU_BIST_FAILURE (0x089)
282 #define POST_CPU_BTB_BIST_FAILURE (0x08A)
283 #define POST_CPU_EX_BIST_FAILURE (0x08B)
284 #define POST_Chipset_PI_Test_Fail (0x08C)
285 #define POST_Chipset_SMBus_SDA_Test_Fail (0x08D)
286 #define POST_BIT_CLK_Fail (0x08E)
288 #define POST_STACK_SETUP (0x090)
289 #define POST_CPU_PF_BIST_FAILURE (0x091)
290 #define POST_CPU_L2_BIST_FAILURE (0x092)
291 #define POST_CPU_GLCP_BIST_FAILURE (0x093)
292 #define POST_CPU_DF_BIST_FAILURE (0x094)
293 #define POST_CPU_VG_BIST_FAILURE (0x095)
294 #define POST_CPU_VIP_BIST_FAILURE (0x096)
295 #define POST_STACK_SETUP_PASS (0x09E)
296 #define POST_STACK_SETUP_FAIL (0x09F)
298 #define POST_PLL_INIT (0x0A0)
299 #define POST_PLL_MANUAL (0x0A1)
300 #define POST_PLL_STRAP (0x0A2)
301 #define POST_PLL_RESET_FAIL (0x0A3)
302 #define POST_PLL_PCI_FAIL (0x0A4)
303 #define POST_PLL_MEM_FAIL (0x0A5)
304 #define POST_PLL_CPU_VER_FAIL (0x0A6)
306 #define POST_MEM_TESTMEM (0x0B0)
307 #define POST_MEM_TESTMEM1 (0x0B1)
308 #define POST_MEM_TESTMEM2 (0x0B2)
309 #define POST_MEM_TESTMEM3 (0x0B3)
310 #define POST_MEM_TESTMEM4 (0x0B4)
311 #define POST_MEM_TESTMEM_PASS (0x0BE)
312 #define POST_MEM_TESTMEM_FAIL (0x0BF)
314 #define POST_SECUROM_SECBOOT_START (0x0C0)
315 #define POST_SECUROM_BOOTSRCSETUP (0x0C1)
316 #define POST_SECUROM_REMAP_FAIL (0x0C2)
317 #define POST_SECUROM_BOOTSRCSETUP_FAIL (0x0C3)
318 #define POST_SECUROM_DCACHESETUP (0x0C4)
319 #define POST_SECUROM_DCACHESETUP_FAIL (0x0C5)
320 #define POST_SECUROM_ICACHESETUP (0x0C6)
321 #define POST_SECUROM_DESCRIPTORSETUP (0x0C7)
322 #define POST_SECUROM_DCACHESETUPBIOS (0x0C8)
323 #define POST_SECUROM_PLATFORMSETUP (0x0C9)
324 #define POST_SECUROM_SIGCHECKBIOS (0x0CA)
325 #define POST_SECUROM_ICACHESETUPBIOS (0x0CB)
326 #define POST_SECUROM_PASS (0x0CC)
327 #define POST_SECUROM_FAIL (0x0CD)
329 #define POST_RCONFInitError (0x0CE)
330 #define POST_CacheInitError (0x0CF)
332 #define POST_ROM_PREUNCOMPRESS (0x0D0)
333 #define POST_ROM_UNCOMPRESS (0x0D1)
334 #define POST_ROM_SMM_INIT (0x0D2)
335 #define POST_ROM_VID_BIOS (0x0D3)
336 #define POST_ROM_LCDINIT (0x0D4)
337 #define POST_ROM_SPLASH (0x0D5)
338 #define POST_ROM_HDDINIT (0x0D6)
339 #define POST_ROM_SYS_INIT (0x0D7)
340 #define POST_ROM_DMM_INIT (0x0D8)
341 #define POST_ROM_TVINIT (0x0D9)
342 #define POST_ROM_POSTUNCOMPRESS (0x0DE)
344 #define P80_CHIPSET_INIT (0x0E0)
345 #define POST_PreChipsetInit (0x0E1)
346 #define POST_LateChipsetInit (0x0E2)
347 #define POST_NORTHB_INIT (0x0E8)
349 #define POST_INTR_SEG_JUMP (0x0F0)
351 #endif /* THE_ALMIGHTY_POST_CODES_H */