2 * This file is part of the coreboot project.
4 * Copyright (C) 2007-2009 coresystems GmbH
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; version 2 of
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
25 #include <arch/romcc_io.h>
26 #include <device/pci_def.h>
27 #include <device/pnp_def.h>
28 #include <cpu/x86/lapic.h>
30 #include <pc80/mc146818rtc.h>
31 #include <console/console.h>
32 #include <cpu/x86/bist.h>
33 #include "northbridge/intel/i945/i945.h"
34 #include "northbridge/intel/i945/raminit.h"
35 #include "southbridge/intel/i82801gx/i82801gx.h"
36 #include "option_table.h"
38 void setup_ich7_gpios(void)
42 printk(BIOS_DEBUG, " GPIOS...");
43 /* General Registers */
44 outl(0x1f28f7c2, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */
45 outl(0xe0e809c3, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */
46 // Power On value is eede1fbf, we set: (TODO explain why)
56 // We should probably do this explicitly bitwise, see below.
57 outl(0xeee83f83, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */
58 /* Output Control Registers */
59 outl(0x00000000, DEFAULT_GPIOBASE + 0x18); /* GPO_BLINK */
60 /* Input Control Registers */
61 outl(0x00000180, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */
62 outl(0x000000e6, DEFAULT_GPIOBASE + 0x30); /* GPIO_USE_SEL2 */
63 outl(0x000000d0, DEFAULT_GPIOBASE + 0x34); /* GP_IO_SEL2 */
64 outl(0x00000034, DEFAULT_GPIOBASE + 0x38); /* GP_LVL2 */
66 printk(BIOS_SPEW, "\n Initializing drive bay...\n");
67 gpios = inl(DEFAULT_GPIOBASE + 0x38); // GPIO Level 2
68 gpios |= (1 << 0); // GPIO33 = ODD
69 gpios |= (1 << 1); // GPIO34 = IDE_RST#
70 outl(gpios, DEFAULT_GPIOBASE + 0x38); /* GP_LVL2 */
72 gpios = inl(DEFAULT_GPIOBASE + 0x0c); // GPIO Level
73 gpios &= ~(1 << 13); // ??
74 outl(gpios, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */
76 printk(BIOS_SPEW, "\n Initializing Ethernet NIC...\n");
77 gpios = inl(DEFAULT_GPIOBASE + 0x0c); // GPIO Level
78 gpios &= ~(1 << 24); // Enable LAN Power
79 outl(gpios, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */
82 static void ich7_enable_lpc(void)
85 if (read_option(lpt, 0) != 0) {
86 lpt_en = 1<<2; // enable LPT
89 pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0);
91 pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0007);
93 pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0b | lpt_en);
94 // Enable 0x02e0 - 0x2ff
95 pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x001c02e1);
96 // Enable 0x600 - 0x6ff
97 pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x00fc0601);
99 pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x00040069);
102 /* This box has two superios, so enabling serial becomes slightly excessive.
103 * We disable a lot of stuff to make sure that there are no conflicts between
104 * the two. Also set up the GPIOs from the beginning. This is the "no schematic
105 * but safe anyways" method.
107 static void pnp_enter_ext_func_mode(device_t dev)
109 unsigned int port = dev >> 8;
113 static void pnp_exit_ext_func_mode(device_t dev)
115 unsigned int port = dev >> 8;
119 static void pnp_write_register(device_t dev, int reg, int val)
121 unsigned int port = dev >> 8;
126 static void early_superio_config(void)
130 dev=PNP_DEV(0x4e, 0x00);
132 pnp_enter_ext_func_mode(dev);
133 pnp_write_register(dev, 0x02, 0x0e); // UART power
134 pnp_write_register(dev, 0x1b, (0x3e8 >> 2)); // UART3 base
135 pnp_write_register(dev, 0x1c, (0x2e8 >> 2)); // UART4 base
136 pnp_write_register(dev, 0x1d, (5 << 4) | 11); // UART3,4 IRQ
137 pnp_write_register(dev, 0x1e, 1); // no 32khz clock
138 pnp_write_register(dev, 0x24, (0x3f8 >> 2)); // UART1 base
139 pnp_write_register(dev, 0x28, (4 << 4) | 0); // UART1,2 IRQ
140 pnp_write_register(dev, 0x2c, 0); // DMA0 FIR
141 pnp_write_register(dev, 0x30, (0x600 >> 4)); // Runtime Register Block Base
143 pnp_write_register(dev, 0x31, 0xce); // GPIO1 DIR
144 pnp_write_register(dev, 0x32, 0x00); // GPIO1 POL
145 pnp_write_register(dev, 0x33, 0x0f); // GPIO2 DIR
146 pnp_write_register(dev, 0x34, 0x00); // GPIO2 POL
147 pnp_write_register(dev, 0x35, 0xa8); // GPIO3 DIR
148 pnp_write_register(dev, 0x36, 0x00); // GPIO3 POL
149 pnp_write_register(dev, 0x37, 0xa8); // GPIO4 DIR
150 pnp_write_register(dev, 0x38, 0x00); // GPIO4 POL
152 pnp_write_register(dev, 0x39, 0x00); // GPIO1 OUT
153 pnp_write_register(dev, 0x40, 0x80); // GPIO2/MISC OUT
154 pnp_write_register(dev, 0x41, 0x00); // GPIO5 OUT
155 pnp_write_register(dev, 0x42, 0xa8); // GPIO5 DIR
156 pnp_write_register(dev, 0x43, 0x00); // GPIO5 POL
157 pnp_write_register(dev, 0x44, 0x00); // GPIO ALT1
158 pnp_write_register(dev, 0x45, 0x50); // GPIO ALT2
159 pnp_write_register(dev, 0x46, 0x00); // GPIO ALT3
161 pnp_write_register(dev, 0x48, 0x55); // GPIO ALT5
162 pnp_write_register(dev, 0x49, 0x55); // GPIO ALT6
163 pnp_write_register(dev, 0x4a, 0x55); // GPIO ALT7
164 pnp_write_register(dev, 0x4b, 0x55); // GPIO ALT8
165 pnp_write_register(dev, 0x4c, 0x55); // GPIO ALT9
166 pnp_write_register(dev, 0x4d, 0x55); // GPIO ALT10
168 pnp_exit_ext_func_mode(dev);
171 static void rcba_config(void)
173 /* Set up virtual channel 0 */
174 //RCBA32(0x0014) = 0x80000001;
175 //RCBA32(0x001c) = 0x03128010;
177 /* Device 1f interrupt pin register */
178 RCBA32(0x3100) = 0x00042220;
179 /* Device 1d interrupt pin register */
180 RCBA32(0x310c) = 0x00214321;
182 /* dev irq route register */
183 RCBA16(0x3140) = 0x0232;
184 RCBA16(0x3142) = 0x3246;
185 RCBA16(0x3144) = 0x0237;
186 RCBA16(0x3146) = 0x3201;
187 RCBA16(0x3148) = 0x3216;
190 RCBA8(0x31ff) = 0x03;
192 /* Enable upper 128bytes of CMOS */
193 RCBA32(0x3400) = (1 << 2);
195 /* Disable unused devices */
196 RCBA32(0x3418) = FD_PCIE6 | FD_PCIE5 | FD_INTLAN | FD_ACMOD | FD_ACAUD | FD_PATA;
197 RCBA32(0x3418) |= (1 << 0); // Required.
199 /* Enable PCIe Root Port Clock Gate */
200 // RCBA32(0x341c) = 0x00000001;
203 /* This should probably go into the ACPI enable trap */
204 /* Set up I/O Trap #0 for 0xfe00 (SMIC) */
205 RCBA32(0x1e84) = 0x00020001;
206 RCBA32(0x1e80) = 0x0000fe01;
208 /* Set up I/O Trap #3 for 0x800-0x80c (Trap) */
209 RCBA32(0x1e9c) = 0x000200f0;
210 RCBA32(0x1e98) = 0x000c0801;
213 static void early_ich7_init(void)
218 // program secondary mlt XXX byte?
219 pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20);
221 // reset rtc power status
222 reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4);
224 pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8);
226 // usb transient disconnect
227 reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad);
229 pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8);
231 reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc);
232 reg32 |= (1 << 29) | (1 << 17);
233 pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32);
235 reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc);
236 reg32 |= (1 << 31) | (1 << 27);
237 pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32);
239 RCBA32(0x0088) = 0x0011d000;
240 RCBA16(0x01fc) = 0x060f;
241 RCBA32(0x01f4) = 0x86000040;
242 RCBA32(0x0214) = 0x10030549;
243 RCBA32(0x0218) = 0x00020504;
244 RCBA8(0x0220) = 0xc5;
245 reg32 = RCBA32(0x3410);
247 RCBA32(0x3410) = reg32;
248 reg32 = RCBA32(0x3430);
251 RCBA32(0x3430) = reg32;
252 RCBA32(0x3418) |= (1 << 0);
253 RCBA16(0x0200) = 0x2008;
254 RCBA8(0x2027) = 0x0d;
255 RCBA16(0x3e08) |= (1 << 7);
256 RCBA16(0x3e48) |= (1 << 7);
257 RCBA32(0x3e0e) |= (1 << 7);
258 RCBA32(0x3e4e) |= (1 << 7);
260 // next step only on ich7m b0 and later:
261 reg32 = RCBA32(0x2034);
262 reg32 &= ~(0x0f << 16);
264 RCBA32(0x2034) = reg32;
269 void main(unsigned long bist)
279 pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, SBR);
281 pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, 0);
285 early_superio_config();
287 /* Set up the console */
290 /* Halt if there was a built in self test failure */
291 report_bist_failure(bist);
293 if (MCHBAR16(SSKPD) == 0xCAFE) {
294 printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n");
296 while (1) asm("hlt");
299 /* Perform some early chipset initialization required
300 * before RAM initialization can work
302 i945_early_initialization();
305 reg32 = inl(DEFAULT_PMBASE + 0x04);
306 printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32);
307 if (((reg32 >> 10) & 7) == 5) {
308 #if CONFIG_HAVE_ACPI_RESUME
309 printk(BIOS_DEBUG, "Resume from S3 detected.\n");
311 /* Clear SLP_TYPE. This will break stage2 but
312 * we care for that when we get there.
314 outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04);
317 printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
321 /* Enable SPD ROMs and DDR-II DRAM */
324 #if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
325 dump_spd_registers();
328 sdram_initialize(boot_mode, NULL);
330 /* Perform some initialization that must run before stage2 */
333 /* This should probably go away. Until now it is required
334 * and mainboard specific
338 /* Chipset Errata! */
341 /* Initialize the internal PCIe links before we go into stage2 */
342 i945_late_initialization();
344 #if CONFIG_HAVE_ACPI_RESUME == 0
345 /* When doing resume, we must not overwrite RAM */
346 #if CONFIG_DEBUG_RAM_SETUP
347 sdram_dump_mchbar_registers();
350 /* This will not work if TSEG is in place! */
351 u32 tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c);
353 printk(BIOS_DEBUG, "TOM: 0x%08x\n", tom);
354 ram_check(0x00000000, 0x000a0000);
355 ram_check(0x00100000, tom);
359 MCHBAR16(SSKPD) = 0xCAFE;
361 #if CONFIG_HAVE_ACPI_RESUME
362 /* Start address of high memory tables */
363 unsigned long high_ram_base = get_top_of_ram() - HIGH_MEMORY_SIZE;
365 /* If there is no high memory area, we didn't boot before, so
366 * this is not a resume. In that case we just create the cbmem toc.
368 if ((boot_mode == 2) && cbmem_reinit((u64)high_ram_base)) {
369 void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME);
371 /* copy 1MB - 64K to high tables ram_base to prevent memory corruption
372 * through stage 2. We could keep stuff like stack and heap in high tables
373 * memory completely, but that's a wonderful clean up task for another
376 if (resume_backup_memory)
377 memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE, HIGH_MEMORY_SAVE);
379 /* Magic for S3 resume */
380 pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, SKPAD_ACPI_S3_MAGIC);