2 * This file is part of the coreboot project.
4 * Copyright (C) 2011 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * ACPI - create the Fixed ACPI Description Tables (FADT)
27 #include <console/console.h>
28 #include <arch/acpi.h>
30 #include <device/device.h>
31 #include "southbridge/amd/sb700/sb700.h"
33 u16 pm_base = SB700_ACPI_IO_BASE;
34 /* pm_base should be set in sb acpi */
35 /* pm_base should be got from bar2 of sb700. Here I compact ACPI
36 * registers into 32 bytes limit.
39 void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
41 acpi_header_t *header = &(fadt->header);
44 printk(BIOS_DEBUG, "pm_base: 0x%04x\n", pm_base);
46 /* Prepare the header */
47 memset((void *)fadt, 0, sizeof(acpi_fadt_t));
48 memcpy(header->signature, "FACP", 4);
51 memcpy(header->oem_id, OEM_ID, 6);
52 memcpy(header->oem_table_id, "AMD ", 8);
53 memcpy(header->asl_compiler_id, ASLC, 4);
54 header->asl_compiler_revision = 0;
56 fadt->firmware_ctrl = (u32) facs;
57 fadt->dsdt = (u32) dsdt;
58 /* 3=Workstation,4=Enterprise Server, 7=Performance Server */
59 fadt->preferred_pm_profile = 0x03;
61 /* disable system management mode by setting to 0: */
63 fadt->acpi_enable = 0xf0;
64 fadt->acpi_disable = 0xf1;
65 fadt->s4bios_req = 0x0;
66 fadt->pstate_cnt = 0xe2;
68 pm_iowrite(0x60, ACPI_PM_EVT_BLK & 0xFF);
69 pm_iowrite(0x61, ACPI_PM_EVT_BLK >> 8);
70 pm_iowrite(0x62, ACPI_PM1_CNT_BLK & 0xFF);
71 pm_iowrite(0x63, ACPI_PM1_CNT_BLK >> 8);
72 pm_iowrite(0x64, ACPI_PM_TMR_BLK & 0xFF);
73 pm_iowrite(0x65, ACPI_PM_TMR_BLK >> 8);
74 pm_iowrite(0x68, ACPI_GPE0_BLK & 0xFF);
75 pm_iowrite(0x69, ACPI_GPE0_BLK >> 8);
77 /* CpuControl is in \_PR.CPU0, 6 bytes */
78 pm_iowrite(0x66, ACPI_CPU_CONTROL & 0xFF);
79 pm_iowrite(0x67, ACPI_CPU_CONTROL >> 8);
81 pm_iowrite(0x6A, 0); /* AcpiSmiCmdLo */
82 pm_iowrite(0x6B, 0); /* AcpiSmiCmdHi */
84 pm_iowrite(0x6C, ACPI_PMA_CNT_BLK & 0xFF);
85 pm_iowrite(0x6D, ACPI_PMA_CNT_BLK >> 8);
87 pm_iowrite(0x74, 1<<0 | 1<<1 | 1<<4 | 1<<2); /* AcpiDecodeEnable, When set, SB uses
88 * the contents of the PM registers at
89 * index 60-6B to decode ACPI I/O address.
90 * AcpiSmiEn & SmiCmdEn*/
91 /* RTC_En_En, TMR_En_En, GBL_EN_EN */
92 outl(0x1, ACPI_PM1_CNT_BLK); /* set SCI_EN */
93 fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK;
94 fadt->pm1b_evt_blk = 0x0000;
95 fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK;
96 fadt->pm1b_cnt_blk = 0x0000;
97 fadt->pm2_cnt_blk = ACPI_PMA_CNT_BLK;
98 fadt->pm_tmr_blk = ACPI_PM_TMR_BLK;
99 fadt->gpe0_blk = ACPI_GPE0_BLK;
100 fadt->gpe1_blk = 0x0000; /* we dont have gpe1 block, do we? */
102 fadt->pm1_evt_len = 4;
103 fadt->pm1_cnt_len = 2;
104 fadt->pm2_cnt_len = 1;
105 fadt->pm_tmr_len = 4;
106 fadt->gpe0_blk_len = 8;
107 fadt->gpe1_blk_len = 0;
110 fadt->cst_cnt = 0xe3;
111 fadt->p_lvl2_lat = 101;
112 fadt->p_lvl3_lat = 1001;
113 fadt->flush_size = 0;
114 fadt->flush_stride = 0;
115 fadt->duty_offset = 1;
116 fadt->duty_width = 3;
117 fadt->day_alrm = 0; /* 0x7d these have to be */
118 fadt->mon_alrm = 0; /* 0x7e added to cmos.layout */
119 fadt->century = 0; /* 0x7f to make rtc alrm work */
120 fadt->iapc_boot_arch = 0x3; /* See table 5-11 */
121 fadt->flags = 0x0001c1a5;/* 0x25; */
125 fadt->reset_reg.space_id = 1;
126 fadt->reset_reg.bit_width = 8;
127 fadt->reset_reg.bit_offset = 0;
128 fadt->reset_reg.resv = 0;
129 fadt->reset_reg.addrl = 0xcf9;
130 fadt->reset_reg.addrh = 0x0;
132 fadt->reset_value = 6;
133 fadt->x_firmware_ctl_l = (u32) facs;
134 fadt->x_firmware_ctl_h = 0;
135 fadt->x_dsdt_l = (u32) dsdt;
138 fadt->x_pm1a_evt_blk.space_id = 1;
139 fadt->x_pm1a_evt_blk.bit_width = 32;
140 fadt->x_pm1a_evt_blk.bit_offset = 0;
141 fadt->x_pm1a_evt_blk.resv = 0;
142 fadt->x_pm1a_evt_blk.addrl = ACPI_PM_EVT_BLK;
143 fadt->x_pm1a_evt_blk.addrh = 0x0;
145 fadt->x_pm1b_evt_blk.space_id = 1;
146 fadt->x_pm1b_evt_blk.bit_width = 4;
147 fadt->x_pm1b_evt_blk.bit_offset = 0;
148 fadt->x_pm1b_evt_blk.resv = 0;
149 fadt->x_pm1b_evt_blk.addrl = 0x0;
150 fadt->x_pm1b_evt_blk.addrh = 0x0;
153 fadt->x_pm1a_cnt_blk.space_id = 1;
154 fadt->x_pm1a_cnt_blk.bit_width = 16;
155 fadt->x_pm1a_cnt_blk.bit_offset = 0;
156 fadt->x_pm1a_cnt_blk.resv = 0;
157 fadt->x_pm1a_cnt_blk.addrl = ACPI_PM1_CNT_BLK;
158 fadt->x_pm1a_cnt_blk.addrh = 0x0;
160 fadt->x_pm1b_cnt_blk.space_id = 1;
161 fadt->x_pm1b_cnt_blk.bit_width = 2;
162 fadt->x_pm1b_cnt_blk.bit_offset = 0;
163 fadt->x_pm1b_cnt_blk.resv = 0;
164 fadt->x_pm1b_cnt_blk.addrl = 0x0;
165 fadt->x_pm1b_cnt_blk.addrh = 0x0;
168 fadt->x_pm2_cnt_blk.space_id = 1;
169 fadt->x_pm2_cnt_blk.bit_width = 0;
170 fadt->x_pm2_cnt_blk.bit_offset = 0;
171 fadt->x_pm2_cnt_blk.resv = 0;
172 fadt->x_pm2_cnt_blk.addrl = ACPI_PMA_CNT_BLK;
173 fadt->x_pm2_cnt_blk.addrh = 0x0;
176 fadt->x_pm_tmr_blk.space_id = 1;
177 fadt->x_pm_tmr_blk.bit_width = 32;
178 fadt->x_pm_tmr_blk.bit_offset = 0;
179 fadt->x_pm_tmr_blk.resv = 0;
180 fadt->x_pm_tmr_blk.addrl = ACPI_PM_TMR_BLK;
181 fadt->x_pm_tmr_blk.addrh = 0x0;
184 fadt->x_gpe0_blk.space_id = 1;
185 fadt->x_gpe0_blk.bit_width = 32;
186 fadt->x_gpe0_blk.bit_offset = 0;
187 fadt->x_gpe0_blk.resv = 0;
188 fadt->x_gpe0_blk.addrl = ACPI_GPE0_BLK;
189 fadt->x_gpe0_blk.addrh = 0x0;
192 fadt->x_gpe1_blk.space_id = 1;
193 fadt->x_gpe1_blk.bit_width = 0;
194 fadt->x_gpe1_blk.bit_offset = 0;
195 fadt->x_gpe1_blk.resv = 0;
196 fadt->x_gpe1_blk.addrl = 0;
197 fadt->x_gpe1_blk.addrh = 0x0;
199 header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t));