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Simplify a few code chunks, fix whitespace and indentation.
author
Uwe Hermann
<uwe@hermann-uwe.de>
Sun, 21 Nov 2010 22:47:22 +0000
(22:47 +0000)
committer
Uwe Hermann
<uwe@hermann-uwe.de>
Sun, 21 Nov 2010 22:47:22 +0000
(22:47 +0000)
Also, remove some less useful comments, some dead code / unused functions.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6108
2b7e53f0
-3cfb-0310-b3e9-
8179ed1497e1
106 files changed:
src/mainboard/amd/db800/romstage.c
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src/mainboard/amd/dbm690t/romstage.c
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src/mainboard/amd/mahogany/romstage.c
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src/mainboard/amd/mahogany_fam10/romstage.c
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src/mainboard/amd/norwich/romstage.c
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src/mainboard/amd/pistachio/romstage.c
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src/mainboard/amd/serengeti_cheetah/romstage.c
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src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
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src/mainboard/amd/tilapia_fam10/romstage.c
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src/mainboard/arima/hdama/romstage.c
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src/mainboard/artecgroup/dbe61/romstage.c
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src/mainboard/asi/mb_5blmp/romstage.c
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src/mainboard/asrock/939a785gmh/romstage.c
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src/mainboard/asus/a8n_e/romstage.c
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src/mainboard/asus/a8v-e_deluxe/romstage.c
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src/mainboard/asus/a8v-e_se/romstage.c
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src/mainboard/asus/m2v-mx_se/romstage.c
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src/mainboard/asus/m2v/romstage.c
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src/mainboard/asus/m4a785-m/romstage.c
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src/mainboard/bcom/winnet100/romstage.c
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src/mainboard/bcom/winnetp680/romstage.c
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src/mainboard/broadcom/blast/romstage.c
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src/mainboard/dell/s1850/romstage.c
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src/mainboard/digitallogic/adl855pc/romstage.c
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src/mainboard/digitallogic/msm586seg/romstage.c
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src/mainboard/digitallogic/msm800sev/romstage.c
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src/mainboard/eaglelion/5bcm/romstage.c
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src/mainboard/emulation/qemu-x86/romstage.c
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src/mainboard/getac/p470/romstage.c
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src/mainboard/gigabyte/ga_2761gxdk/romstage.c
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src/mainboard/gigabyte/m57sli/romstage.c
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src/mainboard/gigabyte/ma785gmt/romstage.c
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src/mainboard/gigabyte/ma78gm/romstage.c
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src/mainboard/hp/dl145_g1/romstage.c
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src/mainboard/hp/dl145_g3/romstage.c
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src/mainboard/hp/dl165_g6_fam10/romstage.c
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src/mainboard/ibase/mb899/romstage.c
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src/mainboard/ibm/e325/romstage.c
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src/mainboard/ibm/e326/romstage.c
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src/mainboard/iei/juki-511p/romstage.c
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src/mainboard/iei/kino-780am2-fam10/romstage.c
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src/mainboard/iei/nova4899r/romstage.c
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src/mainboard/iei/pcisa-lx-800-r10/romstage.c
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src/mainboard/intel/d945gclf/romstage.c
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src/mainboard/intel/eagleheights/romstage.c
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src/mainboard/intel/jarrell/romstage.c
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src/mainboard/intel/truxton/romstage.c
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src/mainboard/intel/xe7501devkit/romstage.c
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src/mainboard/iwill/dk8_htx/romstage.c
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src/mainboard/iwill/dk8s2/romstage.c
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src/mainboard/iwill/dk8x/romstage.c
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src/mainboard/jetway/j7f24/romstage.c
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src/mainboard/jetway/pa78vm5/romstage.c
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src/mainboard/kontron/986lcd-m/romstage.c
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src/mainboard/kontron/kt690/romstage.c
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src/mainboard/lanner/em8510/romstage.c
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src/mainboard/lippert/frontrunner/romstage.c
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src/mainboard/msi/ms7135/romstage.c
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src/mainboard/msi/ms7260/romstage.c
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src/mainboard/msi/ms9185/romstage.c
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src/mainboard/msi/ms9282/romstage.c
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src/mainboard/msi/ms9652_fam10/romstage.c
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src/mainboard/newisys/khepri/romstage.c
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src/mainboard/nvidia/l1_2pvv/romstage.c
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src/mainboard/pcengines/alix1c/romstage.c
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src/mainboard/pcengines/alix2d/romstage.c
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src/mainboard/rca/rm4100/romstage.c
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src/mainboard/roda/rk886ex/romstage.c
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src/mainboard/sunw/ultra40/romstage.c
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src/mainboard/supermicro/h8dme/romstage.c
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src/mainboard/supermicro/h8dmr/romstage.c
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src/mainboard/supermicro/h8dmr_fam10/romstage.c
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src/mainboard/supermicro/h8qme_fam10/romstage.c
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src/mainboard/supermicro/x6dai_g/romstage.c
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src/mainboard/supermicro/x6dhe_g/romstage.c
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src/mainboard/supermicro/x6dhe_g2/romstage.c
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src/mainboard/supermicro/x6dhr_ig/romstage.c
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src/mainboard/supermicro/x6dhr_ig2/romstage.c
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src/mainboard/technexion/tim5690/romstage.c
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src/mainboard/technexion/tim8690/romstage.c
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src/mainboard/televideo/tc7020/romstage.c
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src/mainboard/thomson/ip1000/romstage.c
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src/mainboard/traverse/geos/romstage.c
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src/mainboard/tyan/s2735/romstage.c
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src/mainboard/tyan/s2850/romstage.c
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src/mainboard/tyan/s2875/romstage.c
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src/mainboard/tyan/s2880/romstage.c
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src/mainboard/tyan/s2881/romstage.c
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src/mainboard/tyan/s2882/romstage.c
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src/mainboard/tyan/s2885/romstage.c
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src/mainboard/tyan/s2891/romstage.c
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src/mainboard/tyan/s2892/romstage.c
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src/mainboard/tyan/s2895/romstage.c
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src/mainboard/tyan/s2912/romstage.c
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src/mainboard/tyan/s2912_fam10/romstage.c
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src/mainboard/tyan/s4880/romstage.c
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src/mainboard/tyan/s4882/romstage.c
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src/mainboard/via/epia-cn/romstage.c
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src/mainboard/via/epia-m/romstage.c
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src/mainboard/via/epia-m700/romstage.c
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src/mainboard/via/epia-n/romstage.c
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src/mainboard/via/epia/romstage.c
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src/mainboard/via/pc2500e/romstage.c
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src/mainboard/winent/pl6064/romstage.c
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src/mainboard/wyse/s50/romstage.c
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src/northbridge/via/vx800/examples/romstage.c
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diff --git
a/src/mainboard/amd/db800/romstage.c
b/src/mainboard/amd/db800/romstage.c
index 5c04d4f0926cd8bb89739eb3f263a71f0da1413a..a51b64e937de49d614093ddd60e1340a522d21c6 100644
(file)
--- a/
src/mainboard/amd/db800/romstage.c
+++ b/
src/mainboard/amd/db800/romstage.c
@@
-54,11
+54,6
@@
static inline int spd_read_byte(unsigned int device, unsigned int address)
#include "cpu/amd/model_lx/syspreinit.c"
#include "cpu/amd/model_lx/msrinit.c"
#include "cpu/amd/model_lx/syspreinit.c"
#include "cpu/amd/model_lx/msrinit.c"
-static void mb_gpio_init(void)
-{
- /* Early mainboard specific GPIO setup. */
-}
-
void main(unsigned long bist)
{
post_code(0x01);
void main(unsigned long bist)
{
post_code(0x01);
@@
-76,7
+71,6
@@
void main(unsigned long bist)
* early MSR setup for CS5536.
*/
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
* early MSR setup for CS5536.
*/
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
- mb_gpio_init();
uart_init();
console_init();
uart_init();
console_init();
diff --git
a/src/mainboard/amd/dbm690t/romstage.c
b/src/mainboard/amd/dbm690t/romstage.c
index 81926b60faf636784a8b746b98f59569c7570eec..88ecd941efa738700e926c3581380fac72293237 100644
(file)
--- a/
src/mainboard/amd/dbm690t/romstage.c
+++ b/
src/mainboard/amd/dbm690t/romstage.c
@@
-47,17
+47,9
@@
#include "southbridge/amd/sb600/sb600_early_setup.c"
#include "northbridge/amd/amdk8/debug.c" /* After sb600_early_setup.c! */
#include "southbridge/amd/sb600/sb600_early_setup.c"
#include "northbridge/amd/amdk8/debug.c" /* After sb600_early_setup.c! */
-/* CAN'T BE REMOVED! crt0.S will use it. I don't know WHY!*/
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-}
-
-/* called in raminit_f.c */
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
-}
+static void memreset(int controllers, const struct mem_controller *ctrl) { }
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
-/*called in raminit_f.c */
static inline int spd_read_byte(u32 device, u32 address)
{
return smbus_read_byte(device, address);
static inline int spd_read_byte(u32 device, u32 address)
{
return smbus_read_byte(device, address);
@@
-88,14
+80,12
@@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
-
/* sb600_lpc_port80(); */
sb600_pci_port80();
}
/* sb600_lpc_port80(); */
sb600_pci_port80();
}
- if (bist == 0)
{
+ if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
- }
enable_rs690_dev8();
sb600_lpc_init();
enable_rs690_dev8();
sb600_lpc_init();
@@
-135,8
+125,7
@@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Check to see if processor is capable of changing FIDVID */
/* otherwise it will throw a GP# when reading FIDVID_STATUS */
cpuid1 = cpuid(0x80000007);
/* Check to see if processor is capable of changing FIDVID */
/* otherwise it will throw a GP# when reading FIDVID_STATUS */
cpuid1 = cpuid(0x80000007);
- if( (cpuid1.edx & 0x6) == 0x6 ) {
-
+ if ((cpuid1.edx & 0x6) == 0x6) {
/* Read FIDVID_STATUS */
msr=rdmsr(0xc0010042);
printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
/* Read FIDVID_STATUS */
msr=rdmsr(0xc0010042);
printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
@@
-148,7
+137,6
@@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* show final fid and vid */
msr=rdmsr(0xc0010042);
printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
/* show final fid and vid */
msr=rdmsr(0xc0010042);
printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
-
} else {
printk(BIOS_DEBUG, "Changing FIDVID not supported\n");
}
} else {
printk(BIOS_DEBUG, "Changing FIDVID not supported\n");
}
diff --git
a/src/mainboard/amd/mahogany/romstage.c
b/src/mainboard/amd/mahogany/romstage.c
index 97a7aceeb2cad1e55683ee5d36a3d95a85b2a66a..c20c0a6f7be84e4ab548ce00aa20ac092d9a3862 100644
(file)
--- a/
src/mainboard/amd/mahogany/romstage.c
+++ b/
src/mainboard/amd/mahogany/romstage.c
@@
-47,17
+47,9
@@
#include "southbridge/amd/sb700/sb700_early_setup.c"
#include "northbridge/amd/amdk8/debug.c" /* After sb700_early_setup.c! */
#include "southbridge/amd/sb700/sb700_early_setup.c"
#include "northbridge/amd/amdk8/debug.c" /* After sb700_early_setup.c! */
-/* CAN'T BE REMOVED! crt0.S will use it. I don't know WHY!*/
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-}
-
-/* called in raminit_f.c */
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
-}
+static void memreset(int controllers, const struct mem_controller *ctrl) { }
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
-/*called in raminit_f.c */
static inline int spd_read_byte(u32 device, u32 address)
{
return smbus_read_byte(device, address);
static inline int spd_read_byte(u32 device, u32 address)
{
return smbus_read_byte(device, address);
@@
-88,14
+80,12
@@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
-
/* sb700_lpc_port80(); */
sb700_pci_port80();
}
/* sb700_lpc_port80(); */
sb700_pci_port80();
}
- if (bist == 0)
{
+ if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
- }
enable_rs780_dev8();
sb700_lpc_init();
enable_rs780_dev8();
sb700_lpc_init();
@@
-134,8
+124,7
@@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Check to see if processor is capable of changing FIDVID */
/* otherwise it will throw a GP# when reading FIDVID_STATUS */
cpuid1 = cpuid(0x80000007);
/* Check to see if processor is capable of changing FIDVID */
/* otherwise it will throw a GP# when reading FIDVID_STATUS */
cpuid1 = cpuid(0x80000007);
- if( (cpuid1.edx & 0x6) == 0x6 ) {
-
+ if ((cpuid1.edx & 0x6) == 0x6) {
/* Read FIDVID_STATUS */
msr=rdmsr(0xc0010042);
printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
/* Read FIDVID_STATUS */
msr=rdmsr(0xc0010042);
printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
@@
-147,7
+136,6
@@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* show final fid and vid */
msr=rdmsr(0xc0010042);
printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
/* show final fid and vid */
msr=rdmsr(0xc0010042);
printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
-
} else {
printk(BIOS_DEBUG, "Changing FIDVID not supported\n");
}
} else {
printk(BIOS_DEBUG, "Changing FIDVID not supported\n");
}
diff --git
a/src/mainboard/amd/mahogany_fam10/romstage.c
b/src/mainboard/amd/mahogany_fam10/romstage.c
index 616154853569e14f174a95286ff835b1b38fd286..ce4cd1b920f24d0bf46bc85db68dfea912d05197 100644
(file)
--- a/
src/mainboard/amd/mahogany_fam10/romstage.c
+++ b/
src/mainboard/amd/mahogany_fam10/romstage.c
@@
-53,15
+53,11
@@
static int smbus_read_byte(u32 device, u32 address);
#include "northbridge/amd/amdfam10/debug.c"
#include <spd.h>
#include "northbridge/amd/amdfam10/debug.c"
#include <spd.h>
-static void activate_spd_rom(const struct mem_controller *ctrl)
-{
-}
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
static int spd_read_byte(u32 device, u32 address)
{
static int spd_read_byte(u32 device, u32 address)
{
- int result;
- result = smbus_read_byte(device, address);
- return result;
+ return smbus_read_byte(device, address);
}
#include "northbridge/amd/amdfam10/amdfam10.h"
}
#include "northbridge/amd/amdfam10/amdfam10.h"
@@
-78,11
+74,9
@@
static int spd_read_byte(u32 device, u32 address)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
-
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, };
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, };
- u32 bsp_apicid = 0;
- u32 val;
+ u32 bsp_apicid = 0, val;
msr_t msr;
if (!cpu_init_detectedx && boot_cpu()) {
msr_t msr;
if (!cpu_init_detectedx && boot_cpu()) {
@@
-91,7
+85,6
@@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* mov bsp to bus 0xff when > 8 nodes */
set_bsp_node_CHtExtNodeCfgEn();
enumerate_ht_chain();
/* mov bsp to bus 0xff when > 8 nodes */
set_bsp_node_CHtExtNodeCfgEn();
enumerate_ht_chain();
-
sb700_pci_port80();
}
sb700_pci_port80();
}
diff --git
a/src/mainboard/amd/norwich/romstage.c
b/src/mainboard/amd/norwich/romstage.c
index a9510d7543f3af2041ed7a99a06b196b12c8d962..8d108b3d89dc312d9e6b815523272ba4f7609cd5 100644
(file)
--- a/
src/mainboard/amd/norwich/romstage.c
+++ b/
src/mainboard/amd/norwich/romstage.c
@@
-51,11
+51,6
@@
static inline int spd_read_byte(unsigned int device, unsigned int address)
#include "cpu/amd/model_lx/syspreinit.c"
#include "cpu/amd/model_lx/msrinit.c"
#include "cpu/amd/model_lx/syspreinit.c"
#include "cpu/amd/model_lx/msrinit.c"
-static void mb_gpio_init(void)
-{
- /* Early mainboard specific GPIO setup. */
-}
-
void main(unsigned long bist)
{
post_code(0x01);
void main(unsigned long bist)
{
post_code(0x01);
@@
-77,7
+72,6
@@
void main(unsigned long bist)
*/
/* If debug. real setup done in chipset init via devicetree.cb. */
cs5536_setup_onchipuart(1);
*/
/* If debug. real setup done in chipset init via devicetree.cb. */
cs5536_setup_onchipuart(1);
- mb_gpio_init();
uart_init();
console_init();
uart_init();
console_init();
diff --git
a/src/mainboard/amd/pistachio/romstage.c
b/src/mainboard/amd/pistachio/romstage.c
index 18a4d263bf6a2c3b674dfff6c2b6330ce6a5ef9d..187eb207c214d1bc77a7a34e1f65e5cb89c03b44 100644
(file)
--- a/
src/mainboard/amd/pistachio/romstage.c
+++ b/
src/mainboard/amd/pistachio/romstage.c
@@
-42,17
+42,9
@@
#include "southbridge/amd/sb600/sb600_early_setup.c"
#include "northbridge/amd/amdk8/debug.c" /* After sb600_early_setup.c! */
#include "southbridge/amd/sb600/sb600_early_setup.c"
#include "northbridge/amd/amdk8/debug.c" /* After sb600_early_setup.c! */
-/* CAN'T BE REMOVED! memory bus reset hook for some broken amd k8 boards. */
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-}
-
-/* called in raminit_f.c */
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
-}
+static void memreset(int controllers, const struct mem_controller *ctrl) { }
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
-/*called in raminit_f.c */
static inline int spd_read_byte(u32 device, u32 address)
{
return smbus_read_byte(device, address);
static inline int spd_read_byte(u32 device, u32 address)
{
return smbus_read_byte(device, address);
@@
-85,14
+77,12
@@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
-
sb600_lpc_port80();
/* sb600_pci_port80(); */
}
sb600_lpc_port80();
/* sb600_pci_port80(); */
}
- if (bist == 0)
{
+ if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
- }
enable_rs690_dev8();
sb600_lpc_init();
enable_rs690_dev8();
sb600_lpc_init();
@@
-138,8
+128,7
@@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Check to see if processor is capable of changing FIDVID */
/* otherwise it will throw a GP# when reading FIDVID_STATUS */
cpuid1 = cpuid(0x80000007);
/* Check to see if processor is capable of changing FIDVID */
/* otherwise it will throw a GP# when reading FIDVID_STATUS */
cpuid1 = cpuid(0x80000007);
- if( (cpuid1.edx & 0x6) == 0x6 ) {
-
+ if ((cpuid1.edx & 0x6) == 0x6) {
/* Read FIDVID_STATUS */
msr=rdmsr(0xc0010042);
printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
/* Read FIDVID_STATUS */
msr=rdmsr(0xc0010042);
printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
@@
-151,7
+140,6
@@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* show final fid and vid */
msr=rdmsr(0xc0010042);
printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
/* show final fid and vid */
msr=rdmsr(0xc0010042);
printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
-
} else {
printk(BIOS_DEBUG, "Changing FIDVID not supported\n");
}
} else {
printk(BIOS_DEBUG, "Changing FIDVID not supported\n");
}
diff --git
a/src/mainboard/amd/serengeti_cheetah/romstage.c
b/src/mainboard/amd/serengeti_cheetah/romstage.c
index d545d6bbf56d6bdb172648a2e84352266c7fc56f..24a6525e58eeb415d3c8459bf1c75c1ccd80ab66 100644
(file)
--- a/
src/mainboard/amd/serengeti_cheetah/romstage.c
+++ b/
src/mainboard/amd/serengeti_cheetah/romstage.c
@@
-33,13
+33,11
@@
static void memreset_setup(void)
{
//GPIO on amd8111 to enable MEMRST ????
static void memreset_setup(void)
{
//GPIO on amd8111 to enable MEMRST ????
- outb((
0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(
1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1
- outb((
0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(
1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
+ outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1
+ outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
}
}
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-}
+static void memreset(int controllers, const struct mem_controller *ctrl) { }
static inline void activate_spd_rom(const struct mem_controller *ctrl)
{
static inline void activate_spd_rom(const struct mem_controller *ctrl)
{
@@
-54,6
+52,7
@@
static inline void activate_spd_rom(const struct mem_controller *ctrl)
smbus_write_byte(SMBUS_HUB, 0x03, 0);
}
smbus_write_byte(SMBUS_HUB, 0x03, 0);
}
+
#if 0
static inline void change_i2c_mux(unsigned device)
{
#if 0
static inline void change_i2c_mux(unsigned device)
{
@@
-80,7
+79,7
@@
static inline int spd_read_byte(unsigned device, unsigned address)
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/raminit_f.c"
#include "lib/generic_sdram.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/raminit_f.c"
#include "lib/generic_sdram.c"
-#include "resourcemap.c"
/* tyan does not want the default */
+#include "resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c"
#include <spd.h>
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/dualcore/dualcore.c"
#include <spd.h>
#include "cpu/amd/car/post_cache_as_ram.c"
@@
-117,7
+116,6
@@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
};
struct sys_info *sysinfo = (void*)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
};
struct sys_info *sysinfo = (void*)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
-
int needs_reset;
unsigned bsp_apicid = 0;
#if CONFIG_SET_FIDVID
int needs_reset;
unsigned bsp_apicid = 0;
#if CONFIG_SET_FIDVID
@@
-127,18
+125,12
@@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
-
enumerate_ht_chain();
enumerate_ht_chain();
-
- /* Setup the rom access for 4M */
amd8111_enable_rom();
}
amd8111_enable_rom();
}
- if (bist == 0)
{
+ if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
- }
-
-// post_code(0x32);
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
@@
-188,20
+180,17
@@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Check to see if processor is capable of changing FIDVID */
/* otherwise it will throw a GP# when reading FIDVID_STATUS */
cpuid1 = cpuid(0x80000007);
/* Check to see if processor is capable of changing FIDVID */
/* otherwise it will throw a GP# when reading FIDVID_STATUS */
cpuid1 = cpuid(0x80000007);
- if
( (cpuid1.edx & 0x6) == 0x6
) {
+ if
((cpuid1.edx & 0x6) == 0x6
) {
{
/* Read FIDVID_STATUS */
msr_t msr;
msr=rdmsr(0xc0010042);
print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
{
/* Read FIDVID_STATUS */
msr_t msr;
msr=rdmsr(0xc0010042);
print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
-
}
enable_fid_change();
}
enable_fid_change();
-
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
-
init_fidvid_bsp(bsp_apicid);
// show final fid and vid
init_fidvid_bsp(bsp_apicid);
// show final fid and vid
@@
-209,13
+198,11
@@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
msr_t msr;
msr=rdmsr(0xc0010042);
print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
msr_t msr;
msr=rdmsr(0xc0010042);
print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
-
}
} else {
print_debug("Changing FIDVID not supported\n");
}
}
} else {
print_debug("Changing FIDVID not supported\n");
}
-
#endif
#if 1
#endif
#if 1
diff --git
a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
index 4b509b0e746f4c8627d3a36ca2ffb7c8907f1d5b..f7f194a7bef25010002b0b46e362763e60cb5994 100644
(file)
--- a/
src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
+++ b/
src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
@@
-55,8
+55,8
@@
static void memreset_setup(void)
{
//GPIO on amd8111 to enable MEMRST ????
static void memreset_setup(void)
{
//GPIO on amd8111 to enable MEMRST ????
- outb((
0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(
1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); // REVC_MEMRST_EN=1
- outb((
0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(
1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
+ outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); // REVC_MEMRST_EN=1
+ outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
}
static void activate_spd_rom(const struct mem_controller *ctrl)
}
static void activate_spd_rom(const struct mem_controller *ctrl)
@@
-77,9
+77,7
@@
static void activate_spd_rom(const struct mem_controller *ctrl)
static int spd_read_byte(u32 device, u32 address)
{
static int spd_read_byte(u32 device, u32 address)
{
- int result;
- result = smbus_read_byte(device, address);
- return result;
+ return smbus_read_byte(device, address);
}
#include "northbridge/amd/amdfam10/amdfam10.h"
}
#include "northbridge/amd/amdfam10/amdfam10.h"
@@
-190,8
+188,7
@@
static const u8 spd_addr[] = {
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
- u32 bsp_apicid = 0;
- u32 val;
+ u32 bsp_apicid = 0, val;
msr_t msr;
if (!cpu_init_detectedx && boot_cpu()) {
msr_t msr;
if (!cpu_init_detectedx && boot_cpu()) {
diff --git
a/src/mainboard/amd/tilapia_fam10/romstage.c
b/src/mainboard/amd/tilapia_fam10/romstage.c
index 2f6df2831df2beb047ee93584f6a53edb0ec0f9b..e58fa1203692187ca3b83a4f998c3f000888b630 100644
(file)
--- a/
src/mainboard/amd/tilapia_fam10/romstage.c
+++ b/
src/mainboard/amd/tilapia_fam10/romstage.c
@@
-52,15
+52,11
@@
static int smbus_read_byte(u32 device, u32 address);
#include "southbridge/amd/sb700/sb700_early_setup.c"
#include "northbridge/amd/amdfam10/debug.c"
#include "southbridge/amd/sb700/sb700_early_setup.c"
#include "northbridge/amd/amdfam10/debug.c"
-static void activate_spd_rom(const struct mem_controller *ctrl)
-{
-}
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
static int spd_read_byte(u32 device, u32 address)
{
static int spd_read_byte(u32 device, u32 address)
{
- int result;
- result = smbus_read_byte(device, address);
- return result;
+ return smbus_read_byte(device, address);
}
#include "northbridge/amd/amdfam10/amdfam10.h"
}
#include "northbridge/amd/amdfam10/amdfam10.h"
@@
-78,11
+74,9
@@
static int spd_read_byte(u32 device, u32 address)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
-
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, };
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, };
- u32 bsp_apicid = 0;
- u32 val;
+ u32 bsp_apicid = 0, val;
msr_t msr;
if (!cpu_init_detectedx && boot_cpu()) {
msr_t msr;
if (!cpu_init_detectedx && boot_cpu()) {
@@
-91,7
+85,6
@@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* mov bsp to bus 0xff when > 8 nodes */
set_bsp_node_CHtExtNodeCfgEn();
enumerate_ht_chain();
/* mov bsp to bus 0xff when > 8 nodes */
set_bsp_node_CHtExtNodeCfgEn();
enumerate_ht_chain();
-
sb700_pci_port80();
}
sb700_pci_port80();
}
@@
-157,13
+150,13
@@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
*/
wait_all_core0_started();
*/
wait_all_core0_started();
-
#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS==1
/* Core0 on each node is configured. Now setup any additional cores. */
printk(BIOS_DEBUG, "start_other_cores()\n");
start_other_cores();
post_code(0x37);
wait_all_other_cores_started(bsp_apicid);
/* Core0 on each node is configured. Now setup any additional cores. */
printk(BIOS_DEBUG, "start_other_cores()\n");
start_other_cores();
post_code(0x37);
wait_all_other_cores_started(bsp_apicid);
-
#endif
+#endif
post_code(0x38);
post_code(0x38);
@@
-171,7
+164,7
@@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
rs780_early_setup();
sb700_early_setup();
rs780_early_setup();
sb700_early_setup();
-
#if CONFIG_SET_FIDVID
+#if CONFIG_SET_FIDVID
msr = rdmsr(0xc0010071);
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
msr = rdmsr(0xc0010071);
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
@@
-192,7
+185,7
@@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* show final fid and vid */
msr=rdmsr(0xc0010071);
printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
/* show final fid and vid */
msr=rdmsr(0xc0010071);
printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
-
#endif
+#endif
rs780_htinit();
rs780_htinit();
diff --git
a/src/mainboard/arima/hdama/romstage.c
b/src/mainboard/arima/hdama/romstage.c
index 599d4fb83c6d6fc0b90c30d0c06032dbbbc8fe10..5bcc2492492af3f04302e13d054baf5f49303ea5 100644
(file)
--- a/
src/mainboard/arima/hdama/romstage.c
+++ b/
src/mainboard/arima/hdama/romstage.c
@@
-32,14
+32,13
@@
static void memreset_setup(void)
{
if (is_cpu_pre_c0()) {
static void memreset_setup(void)
{
if (is_cpu_pre_c0()) {
- /* Set the memreset low */
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
- /* Ensure the BIOS has control of the memory lines */
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
- }
- else {
- /* Ensure the CPU has controll of the memory lines */
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
+ /* Set the memreset low. */
+ outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
+ /* Ensure the BIOS has control of the memory lines. */
+ outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
+ } else {
+ /* Ensure the CPU has control of the memory lines. */
+ outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
}
}
}
}
@@
-47,16
+46,13
@@
static void memreset(int controllers, const struct mem_controller *ctrl)
{
if (is_cpu_pre_c0()) {
udelay(800);
{
if (is_cpu_pre_c0()) {
udelay(800);
- /* Set memreset
_high
*/
- outb((
0<<7)|(0<<6)|(0<<5)|(0<<4)|(
1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
+ /* Set memreset
high.
*/
+ outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
udelay(90);
}
}
udelay(90);
}
}
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
- /* nothing to do */
-}
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address)
{
static inline int spd_read_byte(unsigned device, unsigned address)
{
@@
-85,22
+81,18
@@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
};
int needs_reset;
};
int needs_reset;
- unsigned bsp_apicid = 0;
+ unsigned bsp_apicid = 0
, nodes
;
struct mem_controller ctrl[8];
struct mem_controller ctrl[8];
- unsigned nodes;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
-
enumerate_ht_chain();
enumerate_ht_chain();
-
amd8111_enable_rom();
}
amd8111_enable_rom();
}
- if (bist == 0)
{
+ if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx);
bsp_apicid = init_cpus(cpu_init_detectedx);
- }
pc87360_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
pc87360_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
diff --git
a/src/mainboard/artecgroup/dbe61/romstage.c
b/src/mainboard/artecgroup/dbe61/romstage.c
index 1cff578f1b0835f0f56aefa4c001bfd4b2d0b1d9..a8dc6cde59337daf140f0cf9115bb7aa8d5bb9f6 100644
(file)
--- a/
src/mainboard/artecgroup/dbe61/romstage.c
+++ b/
src/mainboard/artecgroup/dbe61/romstage.c
@@
-66,11
+66,6
@@
static int spd_read_byte(unsigned device, unsigned address)
#include "cpu/amd/model_lx/syspreinit.c"
#include "cpu/amd/model_lx/msrinit.c"
#include "cpu/amd/model_lx/syspreinit.c"
#include "cpu/amd/model_lx/msrinit.c"
-static void mb_gpio_init(void)
-{
- /* Early mainboard specific GPIO setup */
-}
-
void main(unsigned long bist)
{
post_code(0x01);
void main(unsigned long bist)
{
post_code(0x01);
@@
-96,7
+91,6
@@
void main(unsigned long bist)
msr.lo |= 0x7 << 20;
wrmsr(MDD_LEG_IO, msr);
msr.lo |= 0x7 << 20;
wrmsr(MDD_LEG_IO, msr);
- mb_gpio_init();
uart_init();
console_init();
uart_init();
console_init();
@@
-109,7
+103,7
@@
void main(unsigned long bist)
sdram_initialize(1, memctrl);
sdram_initialize(1, memctrl);
- /* Dump memory configurat
ation
*/
+ /* Dump memory configurat
ion.
*/
#if 0
msr = rdmsr(MC_CF07_DATA);
print_debug("MC_CF07_DATA: ");
#if 0
msr = rdmsr(MC_CF07_DATA);
print_debug("MC_CF07_DATA: ");
diff --git
a/src/mainboard/asi/mb_5blmp/romstage.c
b/src/mainboard/asi/mb_5blmp/romstage.c
index e013fe3a6cf7102c4676607e487c6e51778e8684..118ded48a33c73ed9d9ce2bfda8b171b921422de 100644
(file)
--- a/
src/mainboard/asi/mb_5blmp/romstage.c
+++ b/
src/mainboard/asi/mb_5blmp/romstage.c
@@
-35,20
+35,11
@@
static void main(unsigned long bist)
{
static void main(unsigned long bist)
{
- /* Initialize the serial console. */
pc87351_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
console_init();
pc87351_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
console_init();
-
- /* Halt if there was a built in self test failure. */
report_bist_failure(bist);
report_bist_failure(bist);
-
cs5530_enable_rom();
cs5530_enable_rom();
-
- /* Initialize RAM. */
sdram_init();
sdram_init();
-
- /* Check whether RAM works. */
/* ram_check(0x00000000, 0x4000); */
}
/* ram_check(0x00000000, 0x4000); */
}
-
diff --git
a/src/mainboard/asrock/939a785gmh/romstage.c
b/src/mainboard/asrock/939a785gmh/romstage.c
index 0bf20b654455409f91027fb28d1f2e70568845c8..6ab8c83156914bbd7e93d1ca6e1bc249f036ad5d 100644
(file)
--- a/
src/mainboard/asrock/939a785gmh/romstage.c
+++ b/
src/mainboard/asrock/939a785gmh/romstage.c
@@
-52,17
+52,9
@@
#define GPIO6_DEV PNP_DEV(0x2e, W83627DHG_GPIO6)
#define GPIO2345_DEV PNP_DEV(0x2e, W83627DHG_GPIO2345)
#define GPIO6_DEV PNP_DEV(0x2e, W83627DHG_GPIO6)
#define GPIO2345_DEV PNP_DEV(0x2e, W83627DHG_GPIO2345)
-/* CAN'T BE REMOVED! crt0.S will use it. I don't know WHY!*/
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-}
-
-/* called in raminit_f.c */
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
-}
+static void memreset(int controllers, const struct mem_controller *ctrl) { }
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
-/*called in raminit_f.c */
static inline int spd_read_byte(u32 device, u32 address)
{
return smbus_read_byte(device, address);
static inline int spd_read_byte(u32 device, u32 address)
{
return smbus_read_byte(device, address);
@@
-140,14
+132,12
@@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
-
/* sb700_lpc_port80(); */
sb700_pci_port80();
}
/* sb700_lpc_port80(); */
sb700_pci_port80();
}
- if (bist == 0)
{
+ if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
- }
enable_rs780_dev8();
sb700_lpc_init();
enable_rs780_dev8();
sb700_lpc_init();
@@
-187,8
+177,7
@@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Check to see if processor is capable of changing FIDVID */
/* otherwise it will throw a GP# when reading FIDVID_STATUS */
cpuid1 = cpuid(0x80000007);
/* Check to see if processor is capable of changing FIDVID */
/* otherwise it will throw a GP# when reading FIDVID_STATUS */
cpuid1 = cpuid(0x80000007);
- if( (cpuid1.edx & 0x6) == 0x6 ) {
-
+ if ((cpuid1.edx & 0x6) == 0x6) {
/* Read FIDVID_STATUS */
msr=rdmsr(0xc0010042);
printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
/* Read FIDVID_STATUS */
msr=rdmsr(0xc0010042);
printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
@@
-200,7
+189,6
@@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* show final fid and vid */
msr=rdmsr(0xc0010042);
printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
/* show final fid and vid */
msr=rdmsr(0xc0010042);
printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
-
} else {
printk(BIOS_DEBUG, "Changing FIDVID not supported\n");
}
} else {
printk(BIOS_DEBUG, "Changing FIDVID not supported\n");
}
diff --git
a/src/mainboard/asus/a8n_e/romstage.c
b/src/mainboard/asus/a8n_e/romstage.c
index f911a9bebad949b5a62ddc645b070352f4839115..9558d055b14853ac1044c60f623547419b7513b1 100644
(file)
--- a/
src/mainboard/asus/a8n_e/romstage.c
+++ b/
src/mainboard/asus/a8n_e/romstage.c
@@
-50,15
+50,8
@@
#include "cpu/amd/dualcore/dualcore.c"
#include <spd.h>
#include "cpu/amd/dualcore/dualcore.c"
#include <spd.h>
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
- /* Nothing to do. */
-}
-
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
- /* Nothing to do. */
-}
+static void memreset(int controllers, const struct mem_controller *ctrl) { }
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address)
{
static inline int spd_read_byte(unsigned device, unsigned address)
{
@@
-108,7
+101,6
@@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
-
sio_setup();
}
sio_setup();
}
@@
-138,7
+130,6
@@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
needs_reset |= ht_setup_chains_x();
needs_reset |= ck804_early_setup_x();
needs_reset |= ht_setup_chains_x();
needs_reset |= ck804_early_setup_x();
-
if (needs_reset) {
print_info("ht reset -\n");
soft_reset();
if (needs_reset) {
print_info("ht reset -\n");
soft_reset();
diff --git
a/src/mainboard/asus/a8v-e_deluxe/romstage.c
b/src/mainboard/asus/a8v-e_deluxe/romstage.c
index 393e560be504ac0bae0779bfbf4ad54d42122631..bf096e1033ea86e835a8df1d1c848cea38f0271e 100644
(file)
--- a/
src/mainboard/asus/a8v-e_deluxe/romstage.c
+++ b/
src/mainboard/asus/a8v-e_deluxe/romstage.c
@@
-52,19
+52,14
@@
unsigned int get_sbdn(unsigned bus);
#define GPIO_DEV PNP_DEV(0x2e, W83627EHG_GPIO_SUSLED)
#define ACPI_DEV PNP_DEV(0x2e, W83627EHG_ACPI)
#define GPIO_DEV PNP_DEV(0x2e, W83627EHG_GPIO_SUSLED)
#define ACPI_DEV PNP_DEV(0x2e, W83627EHG_ACPI)
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-}
+static void memreset(int controllers, const struct mem_controller *ctrl) { }
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address)
{
return smbus_read_byte(device, address);
}
static inline int spd_read_byte(unsigned device, unsigned address)
{
return smbus_read_byte(device, address);
}
-static void activate_spd_rom(const struct mem_controller *ctrl)
-{
-}
-
#include <reset.h>
void soft_reset(void)
{
#include <reset.h>
void soft_reset(void)
{
diff --git
a/src/mainboard/asus/a8v-e_se/romstage.c
b/src/mainboard/asus/a8v-e_se/romstage.c
index 393e560be504ac0bae0779bfbf4ad54d42122631..bf096e1033ea86e835a8df1d1c848cea38f0271e 100644
(file)
--- a/
src/mainboard/asus/a8v-e_se/romstage.c
+++ b/
src/mainboard/asus/a8v-e_se/romstage.c
@@
-52,19
+52,14
@@
unsigned int get_sbdn(unsigned bus);
#define GPIO_DEV PNP_DEV(0x2e, W83627EHG_GPIO_SUSLED)
#define ACPI_DEV PNP_DEV(0x2e, W83627EHG_ACPI)
#define GPIO_DEV PNP_DEV(0x2e, W83627EHG_GPIO_SUSLED)
#define ACPI_DEV PNP_DEV(0x2e, W83627EHG_ACPI)
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-}
+static void memreset(int controllers, const struct mem_controller *ctrl) { }
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address)
{
return smbus_read_byte(device, address);
}
static inline int spd_read_byte(unsigned device, unsigned address)
{
return smbus_read_byte(device, address);
}
-static void activate_spd_rom(const struct mem_controller *ctrl)
-{
-}
-
#include <reset.h>
void soft_reset(void)
{
#include <reset.h>
void soft_reset(void)
{
diff --git
a/src/mainboard/asus/m2v-mx_se/romstage.c
b/src/mainboard/asus/m2v-mx_se/romstage.c
index a9cc6686cb7c4f0fc4fbcaff8999a8858672741c..0849c862ba0f9ebf479a29e4ff287e6d00b23e93 100644
(file)
--- a/
src/mainboard/asus/m2v-mx_se/romstage.c
+++ b/
src/mainboard/asus/m2v-mx_se/romstage.c
@@
-54,19
+54,14
@@
unsigned int get_sbdn(unsigned bus);
#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
#define WATCHDOG_DEV PNP_DEV(0x2e, IT8712F_GPIO)
#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
#define WATCHDOG_DEV PNP_DEV(0x2e, IT8712F_GPIO)
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-}
+static void memreset(int controllers, const struct mem_controller *ctrl) { }
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address)
{
return smbus_read_byte(device, address);
}
static inline int spd_read_byte(unsigned device, unsigned address)
{
return smbus_read_byte(device, address);
}
-static void activate_spd_rom(const struct mem_controller *ctrl)
-{
-}
-
// defines S3_NVRAM_EARLY:
#include "southbridge/via/k8t890/k8t890_early_car.c"
#include "northbridge/amd/amdk8/amdk8.h"
// defines S3_NVRAM_EARLY:
#include "southbridge/via/k8t890/k8t890_early_car.c"
#include "northbridge/amd/amdk8/amdk8.h"
diff --git
a/src/mainboard/asus/m2v/romstage.c
b/src/mainboard/asus/m2v/romstage.c
index 59b6c45bfc484b3d84f9263ef2fc2db8deac06d0..d56ca9ce11f062f6f2647f7c7f7078d4883f42dd 100644
(file)
--- a/
src/mainboard/asus/m2v/romstage.c
+++ b/
src/mainboard/asus/m2v/romstage.c
@@
-56,19
+56,14
@@
unsigned int get_sbdn(unsigned bus);
#define IT8712F_GPIO_BASE 0x0a20
#define IT8712F_GPIO_BASE 0x0a20
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-}
+static void memreset(int controllers, const struct mem_controller *ctrl) { }
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address)
{
return smbus_read_byte(device, address);
}
static inline int spd_read_byte(unsigned device, unsigned address)
{
return smbus_read_byte(device, address);
}
-static void activate_spd_rom(const struct mem_controller *ctrl)
-{
-}
-
// defines S3_NVRAM_EARLY:
#include "southbridge/via/k8t890/k8t890_early_car.c"
#include "northbridge/amd/amdk8/amdk8.h"
// defines S3_NVRAM_EARLY:
#include "southbridge/via/k8t890/k8t890_early_car.c"
#include "northbridge/amd/amdk8/amdk8.h"
diff --git
a/src/mainboard/asus/m4a785-m/romstage.c
b/src/mainboard/asus/m4a785-m/romstage.c
index d59a468e353f13436fe76b24bcd538bcf81f0b4c..ea93eee4121921b17628077664eff9f1fd675be4 100644
(file)
--- a/
src/mainboard/asus/m4a785-m/romstage.c
+++ b/
src/mainboard/asus/m4a785-m/romstage.c
@@
-52,15
+52,11
@@
static int smbus_read_byte(u32 device, u32 address);
#include "southbridge/amd/sb700/sb700_early_setup.c"
#include "northbridge/amd/amdfam10/debug.c"
#include "southbridge/amd/sb700/sb700_early_setup.c"
#include "northbridge/amd/amdfam10/debug.c"
-static void activate_spd_rom(const struct mem_controller *ctrl)
-{
-}
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
static int spd_read_byte(u32 device, u32 address)
{
static int spd_read_byte(u32 device, u32 address)
{
- int result;
- result = smbus_read_byte(device, address);
- return result;
+ return smbus_read_byte(device, address);
}
#include "northbridge/amd/amdfam10/amdfam10.h"
}
#include "northbridge/amd/amdfam10/amdfam10.h"
@@
-78,11
+74,9
@@
static int spd_read_byte(u32 device, u32 address)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
-
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, };
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, };
- u32 bsp_apicid = 0;
- u32 val;
+ u32 bsp_apicid = 0, val;
msr_t msr;
if (!cpu_init_detectedx && boot_cpu()) {
msr_t msr;
if (!cpu_init_detectedx && boot_cpu()) {
@@
-91,7
+85,6
@@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* mov bsp to bus 0xff when > 8 nodes */
set_bsp_node_CHtExtNodeCfgEn();
enumerate_ht_chain();
/* mov bsp to bus 0xff when > 8 nodes */
set_bsp_node_CHtExtNodeCfgEn();
enumerate_ht_chain();
-
sb700_pci_port80();
}
sb700_pci_port80();
}
@@
-108,7
+101,7
@@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
sb700_lpc_init();
it8712f_enable_serial(0, CONFIG_TTYS0_BASE);
sb700_lpc_init();
it8712f_enable_serial(0, CONFIG_TTYS0_BASE);
- it8712f_kill_watchdog();
/* disable watchdog, so it does not reset while still booting */
+ it8712f_kill_watchdog();
uart_init();
#if CONFIG_USBDEBUG
uart_init();
#if CONFIG_USBDEBUG
diff --git
a/src/mainboard/bcom/winnet100/romstage.c
b/src/mainboard/bcom/winnet100/romstage.c
index 177c44739fdcffcc18d936a14d8cc3279cf8e9ab..8074c874e14f732ee55864469a001635cc0a34b6 100644
(file)
--- a/
src/mainboard/bcom/winnet100/romstage.c
+++ b/
src/mainboard/bcom/winnet100/romstage.c
@@
-35,20
+35,11
@@
static void main(unsigned long bist)
{
static void main(unsigned long bist)
{
- /* Initialize the serial console. */
pc97317_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
console_init();
pc97317_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
console_init();
-
- /* Halt if there was a built in self test failure. */
report_bist_failure(bist);
report_bist_failure(bist);
-
cs5530_enable_rom();
cs5530_enable_rom();
-
- /* Initialize RAM. */
sdram_init();
sdram_init();
-
- /* Check whether RAM works. */
/* ram_check(0, 640 * 1024); */
}
/* ram_check(0, 640 * 1024); */
}
-
diff --git
a/src/mainboard/bcom/winnetp680/romstage.c
b/src/mainboard/bcom/winnetp680/romstage.c
index 32654d8ab3ebbe1a6c4d3a791727902c47198f6b..802645365ab5d6745104f3037d4e0f71ea0d295e 100644
(file)
--- a/
src/mainboard/bcom/winnetp680/romstage.c
+++ b/
src/mainboard/bcom/winnetp680/romstage.c
@@
-47,7
+47,8
@@
static inline int spd_read_byte(unsigned device, unsigned address)
static void enable_mainboard_devices(void)
{
device_t dev;
static void enable_mainboard_devices(void)
{
device_t dev;
- dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
+ dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
+ PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
if (dev == PCI_DEV_INVALID)
die("Southbridge not found!!!\n");
if (dev == PCI_DEV_INVALID)
die("Southbridge not found!!!\n");
@@
-85,26
+86,19
@@
void main(unsigned long bist)
pci_write_config8(ctrl.d0f0, 0x4f, 0x01);
w83697hf_set_clksel_48(SERIAL_DEV);
pci_write_config8(ctrl.d0f0, 0x4f, 0x01);
w83697hf_set_clksel_48(SERIAL_DEV);
-
w83697hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
console_init();
w83697hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
console_init();
- print_spew("In romstage.c:main()\n");
-
enable_smbus();
smbus_fixup(&ctrl);
/* Halt if there was a built-in self test failure. */
report_bist_failure(bist);
enable_smbus();
smbus_fixup(&ctrl);
/* Halt if there was a built-in self test failure. */
report_bist_failure(bist);
- print_debug("Enabling mainboard devices\n");
enable_mainboard_devices();
ddr_ram_setup(&ctrl);
/* ram_check(0, 640 * 1024); */
enable_mainboard_devices();
ddr_ram_setup(&ctrl);
/* ram_check(0, 640 * 1024); */
-
- print_spew("Leaving romstage.c:main()\n");
}
}
-
diff --git
a/src/mainboard/broadcom/blast/romstage.c
b/src/mainboard/broadcom/blast/romstage.c
index ff65f3bd54f2292b70e889a41d62947715ec5c9b..b6cbc2f21ce707e5425bec92071c7a92af36d315 100644
(file)
--- a/
src/mainboard/broadcom/blast/romstage.c
+++ b/
src/mainboard/broadcom/blast/romstage.c
@@
-26,13
+26,8
@@
#define SERIAL_DEV PNP_DEV(0x2e, PC87417_SP1)
#define RTC_DEV PNP_DEV(0x2e, PC87417_RTC)
#define SERIAL_DEV PNP_DEV(0x2e, PC87417_SP1)
#define RTC_DEV PNP_DEV(0x2e, PC87417_RTC)
-static void memreset_setup(void)
-{
-}
-
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-}
+static void memreset_setup(void) { }
+static void memreset(int controllers, const struct mem_controller *ctrl) { }
static inline void activate_spd_rom(const struct mem_controller *ctrl)
{
static inline void activate_spd_rom(const struct mem_controller *ctrl)
{
@@
-60,7
+55,7
@@
static inline int spd_read_byte(unsigned device, unsigned address)
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "lib/generic_sdram.c"
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "lib/generic_sdram.c"
-#include "resourcemap.c"
/* tyan does not want the default */
+#include "resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c"
#include <spd.h>
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/dualcore/dualcore.c"
#include <spd.h>
#include "cpu/amd/car/post_cache_as_ram.c"
@@
-80,36
+75,23
@@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
};
int needs_reset;
};
int needs_reset;
- unsigned bsp_apicid = 0;
-
+ unsigned bsp_apicid = 0, nodes;
struct mem_controller ctrl[8];
struct mem_controller ctrl[8];
- unsigned nodes;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
-
enumerate_ht_chain();
enumerate_ht_chain();
-
bcm5785_enable_rom();
bcm5785_enable_rom();
-
bcm5785_enable_lpc();
bcm5785_enable_lpc();
-
- //enable RTC
- pc87417_enable_dev(RTC_DEV);
+ pc87417_enable_dev(RTC_DEV); /* Enable RTC */
}
}
- if (bist == 0)
{
+ if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx);
bsp_apicid = init_cpus(cpu_init_detectedx);
- }
-// post_code(0x32);
pc87417_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
pc87417_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-// post_code(0x33);
-
uart_init();
uart_init();
-// post_code(0x34);
-
console_init();
/* Halt if there was a built in self test failure */
console_init();
/* Halt if there was a built in self test failure */
@@
-166,9
+148,6
@@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
#if 0
print_pci_devices();
#if 0
print_pci_devices();
-#endif
-
-#if 0
dump_pci_devices();
#endif
dump_pci_devices();
#endif
diff --git
a/src/mainboard/dell/s1850/romstage.c
b/src/mainboard/dell/s1850/romstage.c
index c8f8e0f66ce66b70c6edeff5d73951f05f76c14e..04a7cf3f46657409a14849a0bb5e9348b1760c33 100644
(file)
--- a/
src/mainboard/dell/s1850/romstage.c
+++ b/
src/mainboard/dell/s1850/romstage.c
@@
-67,6
+67,7
@@
static inline void waitobf(void)
while((inb(ipmicsr) & (1<<OBF)) == 0)
;
}
while((inb(ipmicsr) & (1<<OBF)) == 0)
;
}
+
/* quite possibly the stupidest interface ever designed. */
static inline void first_cmd_byte(unsigned char byte)
{
/* quite possibly the stupidest interface ever designed. */
static inline void first_cmd_byte(unsigned char byte)
{
@@
-154,12
+155,6
@@
static void main(unsigned long bist)
static const struct mem_controller mch[] = {
{
.node_id = 0,
static const struct mem_controller mch[] = {
{
.node_id = 0,
- /*
- .f0 = PCI_DEV(0, 0x00, 0),
- .f1 = PCI_DEV(0, 0x00, 1),
- .f2 = PCI_DEV(0, 0x00, 2),
- .f3 = PCI_DEV(0, 0x00, 3),
- */
/* the wiring on this part is really messed up */
/* this is my best guess so far */
.channel0 = {DIMM0, DIMM1, DIMM2, DIMM3, },
/* the wiring on this part is really messed up */
/* this is my best guess so far */
.channel0 = {DIMM0, DIMM1, DIMM2, DIMM3, },
@@
-260,9
+255,8
@@
static void main(unsigned long bist)
if (bist == 0) {
/* Skip this if there was a built in self test failure */
early_mtrr_init();
if (bist == 0) {
/* Skip this if there was a built in self test failure */
early_mtrr_init();
- if (memory_initialized())
{
+ if (memory_initialized())
skip_romstage();
skip_romstage();
- }
}
/* Setup the console */
mainboard_set_ich5();
}
/* Setup the console */
mainboard_set_ich5();
@@
-311,9
+305,8
@@
static void main(unsigned long bist)
#if 0
// dump_spd_registers(&cpu[0]);
int i;
#if 0
// dump_spd_registers(&cpu[0]);
int i;
- for(i = 0; i < 1; i++)
{
+ for(i = 0; i < 1; i++)
dump_spd_registers();
dump_spd_registers();
- }
#endif
#if 1
show_dram_slots();
#endif
#if 1
show_dram_slots();
diff --git
a/src/mainboard/digitallogic/adl855pc/romstage.c
b/src/mainboard/digitallogic/adl855pc/romstage.c
index 54f0a271e9d8b598da6637a896f28c3de21b61c8..aec7d2ab015849e1bf4a6310fcb8c28984dc4b78 100644
(file)
--- a/
src/mainboard/digitallogic/adl855pc/romstage.c
+++ b/
src/mainboard/digitallogic/adl855pc/romstage.c
@@
-55,13
+55,12
@@
void main(unsigned long bist)
print_pci_devices();
#endif
print_pci_devices();
#endif
- if(!bios_reset_detected()) {
+ if
(!bios_reset_detected()) {
enable_smbus();
#if 0
dump_spd_registers(&memctrl[0]);
dump_smbus_registers();
#endif
enable_smbus();
#if 0
dump_spd_registers(&memctrl[0]);
dump_smbus_registers();
#endif
-
sdram_initialize(ARRAY_SIZE(memctrl), memctrl);
}
sdram_initialize(ARRAY_SIZE(memctrl), memctrl);
}
diff --git
a/src/mainboard/digitallogic/msm586seg/romstage.c
b/src/mainboard/digitallogic/msm586seg/romstage.c
index d54f1463b4ab0aaf3652899907cfa2eeda6c2d13..4e6462d1e4b0efca2d7052082f314cdb252ed2d8 100644
(file)
--- a/
src/mainboard/digitallogic/msm586seg/romstage.c
+++ b/
src/mainboard/digitallogic/msm586seg/romstage.c
@@
-42,10
+42,7
@@
struct mem_controller {
int i;
};
int i;
};
-static inline int spd_read_byte(unsigned device, unsigned address)
-{
-// return smbus_read_byte(device, address);
-}
+static int spd_read_byte(unsigned device, unsigned address) { }
static inline void dumpmem(void){
int i, j;
static inline void dumpmem(void){
int i, j;
diff --git
a/src/mainboard/digitallogic/msm800sev/romstage.c
b/src/mainboard/digitallogic/msm800sev/romstage.c
index c5a8da45648166521b14f9faecc85f56ac4323eb..14f04941f79104300f6bbeae1495ef3f99268862 100644
(file)
--- a/
src/mainboard/digitallogic/msm800sev/romstage.c
+++ b/
src/mainboard/digitallogic/msm800sev/romstage.c
@@
-20,7
+20,7
@@
static inline int spd_read_byte(unsigned device, unsigned address)
{
static inline int spd_read_byte(unsigned device, unsigned address)
{
-
return smbus_read_byte(device, address);
+ return smbus_read_byte(device, address);
}
#define ManualConf 0 /* Do automatic strapped PLL config */
}
#define ManualConf 0 /* Do automatic strapped PLL config */
@@
-35,11
+35,6
@@
static inline int spd_read_byte(unsigned device, unsigned address)
#include "cpu/amd/model_lx/syspreinit.c"
#include "cpu/amd/model_lx/msrinit.c"
#include "cpu/amd/model_lx/syspreinit.c"
#include "cpu/amd/model_lx/msrinit.c"
-static void mb_gpio_init(void)
-{
- /* Early mainboard specific GPIO setup */
-}
-
void main(unsigned long bist)
{
post_code(0x01);
void main(unsigned long bist)
{
post_code(0x01);
@@
-59,7
+54,6
@@
void main(unsigned long bist)
*/
cs5536_disable_internal_uart();
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
*/
cs5536_disable_internal_uart();
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
- mb_gpio_init();
uart_init();
console_init();
uart_init();
console_init();
diff --git
a/src/mainboard/eaglelion/5bcm/romstage.c
b/src/mainboard/eaglelion/5bcm/romstage.c
index 9caf82ec77db82752d8b2a53e489297402c5deb4..3d99873bc9f9aa997b8028ffb3833ad75dba34c9 100644
(file)
--- a/
src/mainboard/eaglelion/5bcm/romstage.c
+++ b/
src/mainboard/eaglelion/5bcm/romstage.c
@@
-19,32
+19,7
@@
static void main(unsigned long bist)
pc97317_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
console_init();
pc97317_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
console_init();
-
- /* Halt if there was a built in self test failure */
report_bist_failure(bist);
report_bist_failure(bist);
-
cs5530_enable_rom();
cs5530_enable_rom();
-
sdram_init();
sdram_init();
-
- /* Check all of memory */
-#if 0
- ram_check(0x00000000, msr.lo);
-#endif
-#if 0
- static const struct {
- unsigned long lo, hi;
- } check_addrs[] = {
- /* Check 16MB of memory @ 0*/
- { 0x00000000, 0x01000000 },
-#if TOTAL_CPUS > 1
- /* Check 16MB of memory @ 2GB */
- { 0x80000000, 0x81000000 },
-#endif
- };
- int i;
- for(i = 0; i < ARRAY_SIZE(check_addrs); i++) {
- ram_check(check_addrs[i].lo, check_addrs[i].hi);
- }
-#endif
}
}
diff --git
a/src/mainboard/emulation/qemu-x86/romstage.c
b/src/mainboard/emulation/qemu-x86/romstage.c
index 6f78dea9685fdffdeb2bb533b4aebf840ac8bcfe..f559c2afcc3006964508022d125a9929439b57f5 100644
(file)
--- a/
src/mainboard/emulation/qemu-x86/romstage.c
+++ b/
src/mainboard/emulation/qemu-x86/romstage.c
@@
-13,7
+13,7
@@
static void main(void)
{
static void main(void)
{
- /*
init_timer();
*/
+ /*
init_timer();
*/
post_code(0x05);
uart_init();
post_code(0x05);
uart_init();
@@
-22,4
+22,3
@@
static void main(void)
//print_pci_devices();
//dump_pci_devices();
}
//print_pci_devices();
//dump_pci_devices();
}
-
diff --git
a/src/mainboard/getac/p470/romstage.c
b/src/mainboard/getac/p470/romstage.c
index 788f42cb35c8a55ded18dfbd7246103a85c22982..c8753309999f279d2f3fe7632bbe9b20cdf8cf36 100644
(file)
--- a/
src/mainboard/getac/p470/romstage.c
+++ b/
src/mainboard/getac/p470/romstage.c
@@
-277,9
+277,8
@@
void main(unsigned long bist)
u32 reg32;
int boot_mode = 0;
u32 reg32;
int boot_mode = 0;
- if (bist == 0)
{
+ if (bist == 0)
enable_lapic();
enable_lapic();
- }
#if 0
/* Force PCIRST# */
#if 0
/* Force PCIRST# */
diff --git
a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
index 70e3f96cca06d0c63ecb794854934862eb80a843..4b31b545afd59253435f4ce33dd4783267e1b164 100644
(file)
--- a/
src/mainboard/gigabyte/ga_2761gxdk/romstage.c
+++ b/
src/mainboard/gigabyte/ga_2761gxdk/romstage.c
@@
-56,14
+56,8
@@
#define SERIAL_DEV PNP_DEV(0x2e, IT8716F_SP1)
#define SERIAL_DEV PNP_DEV(0x2e, IT8716F_SP1)
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-}
-
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
- /* nothing to do */
-}
+static void memreset(int controllers, const struct mem_controller *ctrl) { }
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address)
{
static inline int spd_read_byte(unsigned device, unsigned address)
{
@@
-119,35
+113,29
@@
static void sio_setup(void)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr [] = {
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr [] = {
-
// Node 0
-
DIMM0, DIMM2, 0, 0,
-
DIMM1, DIMM3, 0, 0,
-
// Node 1
-
DIMM4, DIMM6, 0, 0,
-
DIMM5, DIMM7, 0, 0,
+ // Node 0
+ DIMM0, DIMM2, 0, 0,
+ DIMM1, DIMM3, 0, 0,
+ // Node 1
+ DIMM4, DIMM6, 0, 0,
+ DIMM5, DIMM7, 0, 0,
};
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE +
CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
};
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE +
CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
-
int needs_reset = 0;
unsigned bsp_apicid = 0;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
int needs_reset = 0;
unsigned bsp_apicid = 0;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
-
enumerate_ht_chain();
enumerate_ht_chain();
-
sio_setup();
sio_setup();
-
- /* Setup the sis966 */
sis966_enable_rom();
}
sis966_enable_rom();
}
- if (bist == 0)
{
+ if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
- }
pnp_enter_ext_func_mode(SERIAL_DEV);
pnp_write_config(SERIAL_DEV, 0x23, 0);
pnp_enter_ext_func_mode(SERIAL_DEV);
pnp_write_config(SERIAL_DEV, 0x23, 0);
@@
-194,21
+182,15
@@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
msr_t msr;
msr=rdmsr(0xc0010042);
print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
msr_t msr;
msr=rdmsr(0xc0010042);
print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
-
}
}
-
enable_fid_change();
enable_fid_change();
-
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
-
init_fidvid_bsp(bsp_apicid);
init_fidvid_bsp(bsp_apicid);
-
// show final fid and vid
{
msr_t msr;
msr=rdmsr(0xc0010042);
print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
// show final fid and vid
{
msr_t msr;
msr=rdmsr(0xc0010042);
print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
-
}
#endif
}
#endif
diff --git
a/src/mainboard/gigabyte/m57sli/romstage.c
b/src/mainboard/gigabyte/m57sli/romstage.c
index c9599094abdd69a5d6686b329a85ebd19eff3a27..968e384021666f853fc742236a5f14e83f50f309 100644
(file)
--- a/
src/mainboard/gigabyte/m57sli/romstage.c
+++ b/
src/mainboard/gigabyte/m57sli/romstage.c
@@
-53,14
+53,8
@@
#define SERIAL_DEV PNP_DEV(0x2e, IT8716F_SP1)
#define GPIO_DEV PNP_DEV(0x2e, IT8716F_GPIO)
#define SERIAL_DEV PNP_DEV(0x2e, IT8716F_SP1)
#define GPIO_DEV PNP_DEV(0x2e, IT8716F_GPIO)
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-}
-
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
- /* nothing to do */
-}
+static void memreset(int controllers, const struct mem_controller *ctrl) { }
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address)
{
static inline int spd_read_byte(unsigned device, unsigned address)
{
@@
-111,17
+105,16
@@
static void sio_setup(void)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr [] = {
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr [] = {
-
// Node 0
-
DIMM0, DIMM2, 0, 0,
-
DIMM1, DIMM3, 0, 0,
-
// Node 1
-
DIMM4, DIMM6, 0, 0,
-
DIMM5, DIMM7, 0, 0,
+ // Node 0
+ DIMM0, DIMM2, 0, 0,
+ DIMM1, DIMM3, 0, 0,
+ // Node 1
+ DIMM4, DIMM6, 0, 0,
+ DIMM5, DIMM7, 0, 0,
};
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
+ CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
};
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
+ CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
-
int needs_reset = 0;
unsigned bsp_apicid = 0;
uint8_t tmp = 0;
int needs_reset = 0;
unsigned bsp_apicid = 0;
uint8_t tmp = 0;
@@
-129,18
+122,13
@@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
-
enumerate_ht_chain();
enumerate_ht_chain();
-
sio_setup();
sio_setup();
-
- /* Setup the mcp55 */
mcp55_enable_rom();
}
mcp55_enable_rom();
}
- if (bist == 0)
{
+ if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
- }
pnp_enter_ext_func_mode(SERIAL_DEV);
/* The following line will set CLKIN to 24 MHz, external */
pnp_enter_ext_func_mode(SERIAL_DEV);
/* The following line will set CLKIN to 24 MHz, external */
@@
-153,9
+141,6
@@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Set Serial Flash interface to 0x0820 */
pnp_write_config(GPIO_DEV, 0x64, 0x08);
pnp_write_config(GPIO_DEV, 0x65, 0x20);
/* Set Serial Flash interface to 0x0820 */
pnp_write_config(GPIO_DEV, 0x64, 0x08);
pnp_write_config(GPIO_DEV, 0x65, 0x20);
- /* We can get away with not resetting the logical device because
- * it8716f_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE) will do that.
- */
}
it8716f_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE);
pnp_exit_ext_func_mode(SERIAL_DEV);
}
it8716f_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE);
pnp_exit_ext_func_mode(SERIAL_DEV);
@@
-200,21
+185,15
@@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
msr_t msr;
msr=rdmsr(0xc0010042);
print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
msr_t msr;
msr=rdmsr(0xc0010042);
print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
-
}
}
-
enable_fid_change();
enable_fid_change();
-
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
-
init_fidvid_bsp(bsp_apicid);
init_fidvid_bsp(bsp_apicid);
-
// show final fid and vid
{
msr_t msr;
msr=rdmsr(0xc0010042);
print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
// show final fid and vid
{
msr_t msr;
msr=rdmsr(0xc0010042);
print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
-
}
#endif
}
#endif
diff --git
a/src/mainboard/gigabyte/ma785gmt/romstage.c
b/src/mainboard/gigabyte/ma785gmt/romstage.c
index b784474ff9f8d4f05b94671a8ce89df88d2e613b..7b7f239d0e003e977f01cf8221d3024d5f403b11 100644
(file)
--- a/
src/mainboard/gigabyte/ma785gmt/romstage.c
+++ b/
src/mainboard/gigabyte/ma785gmt/romstage.c
@@
-48,15
+48,11
@@
static int smbus_read_byte(u32 device, u32 address);
#include "southbridge/amd/sb700/sb700_early_setup.c"
#include "northbridge/amd/amdfam10/debug.c"
#include "southbridge/amd/sb700/sb700_early_setup.c"
#include "northbridge/amd/amdfam10/debug.c"
-static void activate_spd_rom(const struct mem_controller *ctrl)
-{
-}
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
static int spd_read_byte(u32 device, u32 address)
{
static int spd_read_byte(u32 device, u32 address)
{
- int result;
- result = smbus_read_byte(device, address);
- return result;
+ return smbus_read_byte(device, address);
}
#include "northbridge/amd/amdfam10/amdfam10.h"
}
#include "northbridge/amd/amdfam10/amdfam10.h"
@@
-76,8
+72,7
@@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, };
{
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, };
- u32 bsp_apicid = 0;
- u32 val;
+ u32 bsp_apicid = 0, val;
msr_t msr;
if (!cpu_init_detectedx && boot_cpu()) {
msr_t msr;
if (!cpu_init_detectedx && boot_cpu()) {
@@
-86,7
+81,6
@@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* mov bsp to bus 0xff when > 8 nodes */
set_bsp_node_CHtExtNodeCfgEn();
enumerate_ht_chain();
/* mov bsp to bus 0xff when > 8 nodes */
set_bsp_node_CHtExtNodeCfgEn();
enumerate_ht_chain();
-
sb700_pci_port80();
}
sb700_pci_port80();
}
@@
-153,13
+147,13
@@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
*/
wait_all_core0_started();
*/
wait_all_core0_started();
-
#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS==1
/* Core0 on each node is configured. Now setup any additional cores. */
printk(BIOS_DEBUG, "start_other_cores()\n");
start_other_cores();
post_code(0x37);
wait_all_other_cores_started(bsp_apicid);
/* Core0 on each node is configured. Now setup any additional cores. */
printk(BIOS_DEBUG, "start_other_cores()\n");
start_other_cores();
post_code(0x37);
wait_all_other_cores_started(bsp_apicid);
-
#endif
+#endif
post_code(0x38);
post_code(0x38);
@@
-167,7
+161,7
@@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
rs780_early_setup();
sb700_early_setup();
rs780_early_setup();
sb700_early_setup();
-
#if CONFIG_SET_FIDVID
+#if CONFIG_SET_FIDVID
msr = rdmsr(0xc0010071);
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
msr = rdmsr(0xc0010071);
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
@@
-188,7
+182,7
@@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* show final fid and vid */
msr=rdmsr(0xc0010071);
printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
/* show final fid and vid */
msr=rdmsr(0xc0010071);
printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
-
#endif
+#endif
rs780_htinit();
rs780_htinit();
diff --git
a/src/mainboard/gigabyte/ma78gm/romstage.c
b/src/mainboard/gigabyte/ma78gm/romstage.c
index 116229605e258d4f03d74292bdd769ca24512866..9a753b9201314e0072381d7d943504c8534ad9cf 100644
(file)
--- a/
src/mainboard/gigabyte/ma78gm/romstage.c
+++ b/
src/mainboard/gigabyte/ma78gm/romstage.c
@@
-52,15
+52,11
@@
static int smbus_read_byte(u32 device, u32 address);
#include "southbridge/amd/sb700/sb700_early_setup.c"
#include "northbridge/amd/amdfam10/debug.c"
#include "southbridge/amd/sb700/sb700_early_setup.c"
#include "northbridge/amd/amdfam10/debug.c"
-static void activate_spd_rom(const struct mem_controller *ctrl)
-{
-}
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
static int spd_read_byte(u32 device, u32 address)
{
static int spd_read_byte(u32 device, u32 address)
{
- int result;
- result = smbus_read_byte(device, address);
- return result;
+ return smbus_read_byte(device, address);
}
#include "northbridge/amd/amdfam10/amdfam10.h"
}
#include "northbridge/amd/amdfam10/amdfam10.h"
@@
-80,8
+76,7
@@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, };
{
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, };
- u32 bsp_apicid = 0;
- u32 val;
+ u32 bsp_apicid = 0, val;
msr_t msr;
if (!cpu_init_detectedx && boot_cpu()) {
msr_t msr;
if (!cpu_init_detectedx && boot_cpu()) {
@@
-90,7
+85,6
@@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* mov bsp to bus 0xff when > 8 nodes */
set_bsp_node_CHtExtNodeCfgEn();
enumerate_ht_chain();
/* mov bsp to bus 0xff when > 8 nodes */
set_bsp_node_CHtExtNodeCfgEn();
enumerate_ht_chain();
-
sb700_pci_port80();
}
sb700_pci_port80();
}
@@
-155,13
+149,13
@@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
*/
wait_all_core0_started();
*/
wait_all_core0_started();
-
#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS==1
/* Core0 on each node is configured. Now setup any additional cores. */
printk(BIOS_DEBUG, "start_other_cores()\n");
start_other_cores();
post_code(0x37);
wait_all_other_cores_started(bsp_apicid);
/* Core0 on each node is configured. Now setup any additional cores. */
printk(BIOS_DEBUG, "start_other_cores()\n");
start_other_cores();
post_code(0x37);
wait_all_other_cores_started(bsp_apicid);
-
#endif
+#endif
post_code(0x38);
post_code(0x38);
@@
-169,7
+163,7
@@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
rs780_early_setup();
sb700_early_setup();
rs780_early_setup();
sb700_early_setup();
-
#if CONFIG_SET_FIDVID
+#if CONFIG_SET_FIDVID
msr = rdmsr(0xc0010071);
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
msr = rdmsr(0xc0010071);
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
@@
-190,7
+184,7
@@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* show final fid and vid */
msr=rdmsr(0xc0010071);
printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
/* show final fid and vid */
msr=rdmsr(0xc0010071);
printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
-
#endif
+#endif
rs780_htinit();
rs780_htinit();
diff --git
a/src/mainboard/hp/dl145_g1/romstage.c
b/src/mainboard/hp/dl145_g1/romstage.c
index bce716cb1ac5dbb19354ccb4da26a1dd7935eb4b..5352ccc48cb74496c5f7d714a7d1375d41ca8729 100644
(file)
--- a/
src/mainboard/hp/dl145_g1/romstage.c
+++ b/
src/mainboard/hp/dl145_g1/romstage.c
@@
-27,13
+27,13
@@
static void memreset_setup(void)
{
if (is_cpu_pre_c0()) {
static void memreset_setup(void)
{
if (is_cpu_pre_c0()) {
- /* Set the memreset low */
- outb((
0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(
1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);
- /* Ensure the BIOS has control of the memory lines */
- outb((
0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(
1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
+ /* Set the memreset low
.
*/
+ outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);
+ /* Ensure the BIOS has control of the memory lines
.
*/
+ outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
} else {
} else {
- /* Ensure the CPU has control
l of the memory lines
*/
- outb((
0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(
1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17);
+ /* Ensure the CPU has control
of the memory lines.
*/
+ outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17);
}
}
}
}
@@
-41,8
+41,8
@@
static void memreset(int controllers, const struct mem_controller *ctrl)
{
if (is_cpu_pre_c0()) {
udelay(800);
{
if (is_cpu_pre_c0()) {
udelay(800);
- /* Set memreset
_high
*/
- outb((
0<<7)|(0<<6)|(0<<5)|(0<<4)|(
1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);
+ /* Set memreset
high.
*/
+ outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);
udelay(90);
}
}
udelay(90);
}
}
@@
-97,37
+97,29
@@
static inline int spd_read_byte(unsigned device, unsigned address)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr [] = {
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr [] = {
-
//first node
-
RC0|DIMM0, RC0|DIMM2, 0, 0,
-
RC0|DIMM1, RC0|DIMM3, 0, 0,
+ //first node
+ RC0|DIMM0, RC0|DIMM2, 0, 0,
+ RC0|DIMM1, RC0|DIMM3, 0, 0,
#if CONFIG_MAX_PHYSICAL_CPUS > 1
#if CONFIG_MAX_PHYSICAL_CPUS > 1
-
//second node
-
RC1|DIMM0, RC1|DIMM2, 0, 0,
-
RC1|DIMM1, RC1|DIMM3, 0, 0,
+ //second node
+ RC1|DIMM0, RC1|DIMM2, 0, 0,
+ RC1|DIMM1, RC1|DIMM3, 0, 0,
#endif
};
int needs_reset;
#endif
};
int needs_reset;
- unsigned bsp_apicid = 0;
-
+ unsigned bsp_apicid = 0, nodes;
struct mem_controller ctrl[8];
struct mem_controller ctrl[8];
- unsigned nodes;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
-
enumerate_ht_chain();
enumerate_ht_chain();
-
- /* Setup the amd8111 */
amd8111_enable_rom();
}
amd8111_enable_rom();
}
- if (bist == 0)
{
+ if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx);
bsp_apicid = init_cpus(cpu_init_detectedx);
- }
-
-// post_code(0x32);
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
diff --git
a/src/mainboard/hp/dl145_g3/romstage.c
b/src/mainboard/hp/dl145_g3/romstage.c
index ce6fd54f8ff6ea5f2ff0320278597535ac5b1dd7..ff16b3f8bb29068f43daf5f06acf0919b041f7f8 100644
(file)
--- a/
src/mainboard/hp/dl145_g3/romstage.c
+++ b/
src/mainboard/hp/dl145_g3/romstage.c
@@
-59,9
+59,7
@@
#define SERIAL_DEV PNP_DEV(0x2e, PILOT_SP1)
#define RTC_DEV PNP_DEV(0x4e, PC87417_RTC)
#define SERIAL_DEV PNP_DEV(0x2e, PILOT_SP1)
#define RTC_DEV PNP_DEV(0x4e, PC87417_RTC)
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-}
+static void memreset(int controllers, const struct mem_controller *ctrl) { }
static inline void activate_spd_rom(const struct mem_controller *ctrl)
{
static inline void activate_spd_rom(const struct mem_controller *ctrl)
{
@@
-133,7
+131,6
@@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// first node
DIMM0, DIMM2, 0, 0,
DIMM1, DIMM3, 0, 0,
// first node
DIMM0, DIMM2, 0, 0,
DIMM1, DIMM3, 0, 0,
-
// second node
DIMM4, DIMM6, 0, 0,
DIMM5, DIMM7, 0, 0,
// second node
DIMM4, DIMM6, 0, 0,
DIMM5, DIMM7, 0, 0,
@@
-141,24
+138,20
@@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
+ CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
+ CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
-
int needs_reset;
unsigned bsp_apicid = 0;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
int needs_reset;
unsigned bsp_apicid = 0;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
-
enumerate_ht_chain();
bcm5785_enable_rom();
bcm5785_enable_lpc();
enumerate_ht_chain();
bcm5785_enable_rom();
bcm5785_enable_lpc();
- //enable RTC
- pc87417_enable_dev(RTC_DEV);
+ pc87417_enable_dev(RTC_DEV); /* Enable RTC */
}
}
- if (bist == 0)
{
+ if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
- }
pilot_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
pilot_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
diff --git
a/src/mainboard/hp/dl165_g6_fam10/romstage.c
b/src/mainboard/hp/dl165_g6_fam10/romstage.c
index d629a7743db0f4a6d49ed03aaf48ae030ae8b58d..f167b925acbcc339ace4a086d136d5742ae3c24a 100644
(file)
--- a/
src/mainboard/hp/dl165_g6_fam10/romstage.c
+++ b/
src/mainboard/hp/dl165_g6_fam10/romstage.c
@@
-100,30
+100,24
@@
static const u8 spd_addr[] = {
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
-
- u32 bsp_apicid = 0;
- u32 val;
+ u32 bsp_apicid = 0, val;
msr_t msr;
if (!cpu_init_detectedx && boot_cpu()) {
msr_t msr;
if (!cpu_init_detectedx && boot_cpu()) {
- /* Nothing special needs to be done to find bus 0 */
+
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
/* mov bsp to bus 0xff when > 8 nodes */
set_bsp_node_CHtExtNodeCfgEn();
enumerate_ht_chain();
/* Allow the HT devices to be found */
/* mov bsp to bus 0xff when > 8 nodes */
set_bsp_node_CHtExtNodeCfgEn();
enumerate_ht_chain();
-
- /* Setup the rom access for 4M */
bcm5785_enable_rom();
bcm5785_enable_lpc();
bcm5785_enable_rom();
bcm5785_enable_lpc();
- //enable RTC
- pc87417_enable_dev(RTC_DEV);
+ pc87417_enable_dev(RTC_DEV); /* Enable RTC */
}
post_code(0x30);
}
post_code(0x30);
- if (bist == 0)
{
+ if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
- }
pilot_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
pilot_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
diff --git
a/src/mainboard/ibase/mb899/romstage.c
b/src/mainboard/ibase/mb899/romstage.c
index cc82c4ed4ea9fede11dc2ee90ef547f794835d0d..b9d2f99f62fd0496eb6731482b8b5eb874a8eed3 100644
(file)
--- a/
src/mainboard/ibase/mb899/romstage.c
+++ b/
src/mainboard/ibase/mb899/romstage.c
@@
-239,9
+239,8
@@
void main(unsigned long bist)
u32 reg32;
int boot_mode = 0;
u32 reg32;
int boot_mode = 0;
- if (bist == 0)
{
+ if (bist == 0)
enable_lapic();
enable_lapic();
- }
ich7_enable_lpc();
early_superio_config_w83627ehg();
ich7_enable_lpc();
early_superio_config_w83627ehg();
diff --git
a/src/mainboard/ibm/e325/romstage.c
b/src/mainboard/ibm/e325/romstage.c
index 56777e627492a7e86b55160479adc7173972696f..49dce1412b5717ae23cfda400444165584497521 100644
(file)
--- a/
src/mainboard/ibm/e325/romstage.c
+++ b/
src/mainboard/ibm/e325/romstage.c
@@
-29,13
+29,13
@@
static void memreset_setup(void)
{
if (is_cpu_pre_c0()) {
static void memreset_setup(void)
{
if (is_cpu_pre_c0()) {
- /* Set the memreset low */
- outb((
0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(
1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);
- /* Ensure the BIOS has control of the memory lines */
- outb((
0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(
1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
+ /* Set the memreset low
.
*/
+ outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);
+ /* Ensure the BIOS has control of the memory lines
.
*/
+ outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
} else {
} else {
- /* Ensure the CPU has control
l of the memory lines
*/
- outb((
0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(
1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17);
+ /* Ensure the CPU has control
of the memory lines.
*/
+ outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17);
}
}
}
}
@@
-43,16
+43,13
@@
static void memreset(int controllers, const struct mem_controller *ctrl)
{
if (is_cpu_pre_c0()) {
udelay(800);
{
if (is_cpu_pre_c0()) {
udelay(800);
- /* Set memreset
_high
*/
- outb((
0<<7)|(0<<6)|(0<<5)|(0<<4)|(
1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);
+ /* Set memreset
high.
*/
+ outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);
udelay(90);
}
}
udelay(90);
}
}
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
- /* nothing to do */
-}
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address)
{
static inline int spd_read_byte(unsigned device, unsigned address)
{
@@
-99,15
+96,12
@@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
-
enumerate_ht_chain();
enumerate_ht_chain();
-
amd8111_enable_rom();
}
amd8111_enable_rom();
}
- if (bist == 0)
{
+ if (bist == 0)
init_cpus(cpu_init_detectedx);
init_cpus(cpu_init_detectedx);
- }
pc87366_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
pc87366_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
diff --git
a/src/mainboard/ibm/e326/romstage.c
b/src/mainboard/ibm/e326/romstage.c
index f9a706d718c945f281f4bd29fc0f58772877b5d9..48bfcc5f83e237e9bb912eaa1c6c3cf492676fa8 100644
(file)
--- a/
src/mainboard/ibm/e326/romstage.c
+++ b/
src/mainboard/ibm/e326/romstage.c
@@
-29,13
+29,13
@@
static void memreset_setup(void)
{
if (is_cpu_pre_c0()) {
static void memreset_setup(void)
{
if (is_cpu_pre_c0()) {
- /* Set the memreset low */
- outb((
0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(
1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);
- /* Ensure the BIOS has control of the memory lines */
- outb((
0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(
1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
+ /* Set the memreset low
.
*/
+ outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);
+ /* Ensure the BIOS has control of the memory lines
.
*/
+ outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
} else {
} else {
- /* Ensure the CPU has control
l of the memory lines
*/
- outb((
0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(
1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17);
+ /* Ensure the CPU has control
of the memory lines.
*/
+ outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17);
}
}
}
}
@@
-43,16
+43,13
@@
static void memreset(int controllers, const struct mem_controller *ctrl)
{
if (is_cpu_pre_c0()) {
udelay(800);
{
if (is_cpu_pre_c0()) {
udelay(800);
- /* Set memreset
_high
*/
- outb((
0<<7)|(0<<6)|(0<<5)|(0<<4)|(
1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);
+ /* Set memreset
high.
*/
+ outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);
udelay(90);
}
}
udelay(90);
}
}
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
- /* nothing to do */
-}
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address)
{
static inline int spd_read_byte(unsigned device, unsigned address)
{
@@
-99,15
+96,12
@@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
-
enumerate_ht_chain();
enumerate_ht_chain();
-
amd8111_enable_rom();
}
amd8111_enable_rom();
}
- if (bist == 0)
{
+ if (bist == 0)
init_cpus(cpu_init_detectedx);
init_cpus(cpu_init_detectedx);
- }
pc87366_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
pc87366_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
diff --git
a/src/mainboard/iei/juki-511p/romstage.c
b/src/mainboard/iei/juki-511p/romstage.c
index 96e027872aa4c027226e22fef6cba4d3731fa632..6bde6756c4db541557d8597d3364ec4169043221 100644
(file)
--- a/
src/mainboard/iei/juki-511p/romstage.c
+++ b/
src/mainboard/iei/juki-511p/romstage.c
@@
-36,12
+36,9
@@
static void main(unsigned long bist)
{
static void main(unsigned long bist)
{
- /* Initialize the serial console. */
w83977f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
console_init();
w83977f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
console_init();
-
- /* Halt if there was a built in self test failure. */
report_bist_failure(bist);
/* Disable Watchdog Timer. */
report_bist_failure(bist);
/* Disable Watchdog Timer. */
@@
-49,10
+46,6
@@
static void main(unsigned long bist)
inb(0x843);
cs5530_enable_rom();
inb(0x843);
cs5530_enable_rom();
-
- /* Initialize RAM. */
sdram_init();
sdram_init();
-
- /* Check RAM. */
/* ram_check(0x00000000, 640 * 1024); */
}
/* ram_check(0x00000000, 640 * 1024); */
}
diff --git
a/src/mainboard/iei/kino-780am2-fam10/romstage.c
b/src/mainboard/iei/kino-780am2-fam10/romstage.c
index eb886473845b009043a6b6df9353b821cf1cc4f0..5afa651e058fe168c3f43c8f2bc66186312f1922 100644
(file)
--- a/
src/mainboard/iei/kino-780am2-fam10/romstage.c
+++ b/
src/mainboard/iei/kino-780am2-fam10/romstage.c
@@
-25,9
+25,6
@@
#define FAM10_SCAN_PCI_BUS 0
#define FAM10_ALLOCATE_IO_RANGE 0
#define FAM10_SCAN_PCI_BUS 0
#define FAM10_ALLOCATE_IO_RANGE 0
-/* UART address and device number */
-#define SERIAL_DEV PNP_DEV(0x2e, F71859_SP1)
-
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
@@
-55,15
+52,13
@@
static int smbus_read_byte(u32 device, u32 address);
#include "southbridge/amd/sb700/sb700_early_setup.c"
#include "northbridge/amd/amdfam10/debug.c"
#include "southbridge/amd/sb700/sb700_early_setup.c"
#include "northbridge/amd/amdfam10/debug.c"
-
static void activate_spd_rom(const struct mem_controller *ctrl
)
-{
-}
+
#define SERIAL_DEV PNP_DEV(0x2e, F71859_SP1
)
+
+
static void activate_spd_rom(const struct mem_controller *ctrl) {
}
static int spd_read_byte(u32 device, u32 address)
{
static int spd_read_byte(u32 device, u32 address)
{
- int result;
- result = smbus_read_byte(device, address);
- return result;
+ return smbus_read_byte(device, address);
}
#include "northbridge/amd/amdfam10/amdfam10.h"
}
#include "northbridge/amd/amdfam10/amdfam10.h"
@@
-81,11
+76,9
@@
static int spd_read_byte(u32 device, u32 address)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
-
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, };
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, };
- u32 bsp_apicid = 0;
- u32 val;
+ u32 bsp_apicid = 0, val;
msr_t msr;
if (!cpu_init_detectedx && boot_cpu()) {
msr_t msr;
if (!cpu_init_detectedx && boot_cpu()) {
@@
-94,7
+87,6
@@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* mov bsp to bus 0xff when > 8 nodes */
set_bsp_node_CHtExtNodeCfgEn();
enumerate_ht_chain();
/* mov bsp to bus 0xff when > 8 nodes */
set_bsp_node_CHtExtNodeCfgEn();
enumerate_ht_chain();
-
sb700_pci_port80();
}
sb700_pci_port80();
}
diff --git
a/src/mainboard/iei/nova4899r/romstage.c
b/src/mainboard/iei/nova4899r/romstage.c
index 72f35aae3f1abe20042eb7b87b1170139e9a88ee..0900f4ba3eef1e61ce7df632a593ae5e76fdfc55 100644
(file)
--- a/
src/mainboard/iei/nova4899r/romstage.c
+++ b/
src/mainboard/iei/nova4899r/romstage.c
@@
-36,19
+36,11
@@
static void main(unsigned long bist)
{
static void main(unsigned long bist)
{
- /* Initialize the serial console. */
w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
console_init();
w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
console_init();
-
- /* Halt if there was a built in self test failure. */
report_bist_failure(bist);
report_bist_failure(bist);
-
cs5530_enable_rom();
cs5530_enable_rom();
-
- /* Initialize RAM. */
sdram_init();
sdram_init();
-
- /* Check RAM. */
/* ram_check(0x00000000, 640 * 1024); */
}
/* ram_check(0x00000000, 640 * 1024); */
}
diff --git
a/src/mainboard/iei/pcisa-lx-800-r10/romstage.c
b/src/mainboard/iei/pcisa-lx-800-r10/romstage.c
index e889eed09ce27ad5853de455a59d61dcde72a506..4e27f9bbbd00e21589d6133f2c45e86ec9bbd730 100644
(file)
--- a/
src/mainboard/iei/pcisa-lx-800-r10/romstage.c
+++ b/
src/mainboard/iei/pcisa-lx-800-r10/romstage.c
@@
-58,11
+58,6
@@
static inline int spd_read_byte(unsigned int device, unsigned int address)
#include "cpu/amd/model_lx/syspreinit.c"
#include "cpu/amd/model_lx/msrinit.c"
#include "cpu/amd/model_lx/syspreinit.c"
#include "cpu/amd/model_lx/msrinit.c"
-static void mb_gpio_init(void)
-{
- /* Early mainboard specific GPIO setup. */
-}
-
void main(unsigned long bist)
{
post_code(0x01);
void main(unsigned long bist)
{
post_code(0x01);
@@
-80,7
+75,6
@@
void main(unsigned long bist)
* early MSR setup for CS5536.
*/
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
* early MSR setup for CS5536.
*/
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
- mb_gpio_init();
uart_init();
console_init();
uart_init();
console_init();
diff --git
a/src/mainboard/intel/d945gclf/romstage.c
b/src/mainboard/intel/d945gclf/romstage.c
index 8d155d1662a58263bb2c9cd7d3079e5790b6cbc3..8b79f2dc571de7f6a93a22a3a5dfe4c106189de0 100644
(file)
--- a/
src/mainboard/intel/d945gclf/romstage.c
+++ b/
src/mainboard/intel/d945gclf/romstage.c
@@
-201,9
+201,8
@@
void main(unsigned long bist)
u32 reg32;
int boot_mode = 0;
u32 reg32;
int boot_mode = 0;
- if (bist == 0)
{
+ if (bist == 0)
enable_lapic();
enable_lapic();
- }
ich7_enable_lpc();
early_superio_config_lpc47m15x();
ich7_enable_lpc();
early_superio_config_lpc47m15x();
diff --git
a/src/mainboard/intel/eagleheights/romstage.c
b/src/mainboard/intel/eagleheights/romstage.c
index 82064a418c0164884ce40bafd37536341d36ea36..8f8cd0f00fce34b7665e09f32a9f43f2360524ed 100644
(file)
--- a/
src/mainboard/intel/eagleheights/romstage.c
+++ b/
src/mainboard/intel/eagleheights/romstage.c
@@
-138,9
+138,8
@@
void main(unsigned long bist)
}
};
}
};
- if (bist == 0)
{
+ if (bist == 0)
enable_lapic();
enable_lapic();
- }
/* Setup the console */
i3100_enable_superio();
/* Setup the console */
i3100_enable_superio();
diff --git
a/src/mainboard/intel/jarrell/romstage.c
b/src/mainboard/intel/jarrell/romstage.c
index 8b39ce58435ed755e8c2aac56c132777222886c3..5d33b10633841b5b8aa0c7831a1310b04fda2775 100644
(file)
--- a/
src/mainboard/intel/jarrell/romstage.c
+++ b/
src/mainboard/intel/jarrell/romstage.c
@@
-45,12
+45,6
@@
static void main(unsigned long bist)
static const struct mem_controller mch[] = {
{
.node_id = 0,
static const struct mem_controller mch[] = {
{
.node_id = 0,
- /*
- .f0 = PCI_DEV(0, 0x00, 0),
- .f1 = PCI_DEV(0, 0x00, 1),
- .f2 = PCI_DEV(0, 0x00, 2),
- .f3 = PCI_DEV(0, 0x00, 3),
- */
.channel0 = { DIMM2, DIMM1, DIMM0, 0 },
.channel1 = { DIMM6, DIMM5, DIMM4, 0 },
}
.channel0 = { DIMM2, DIMM1, DIMM0, 0 },
.channel1 = { DIMM6, DIMM5, DIMM4, 0 },
}
@@
-59,9
+53,8
@@
static void main(unsigned long bist)
if (bist == 0) {
/* Skip this if there was a built in self test failure */
early_mtrr_init();
if (bist == 0) {
/* Skip this if there was a built in self test failure */
early_mtrr_init();
- if (memory_initialized())
{
+ if (memory_initialized())
skip_romstage();
skip_romstage();
- }
}
/* Setup the console */
}
/* Setup the console */
@@
-86,9
+79,8
@@
static void main(unsigned long bist)
/* config LPC decode for flash memory access */
device_t dev;
dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0);
/* config LPC decode for flash memory access */
device_t dev;
dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0);
- if (dev == PCI_DEV_INVALID)
{
+ if (dev == PCI_DEV_INVALID)
die("Missing ich5?");
die("Missing ich5?");
- }
pci_write_config32(dev, 0xe8, 0x00000000);
pci_write_config8(dev, 0xf0, 0x00);
pci_write_config32(dev, 0xe8, 0x00000000);
pci_write_config8(dev, 0xf0, 0x00);
@@
-99,9
+91,8
@@
static void main(unsigned long bist)
#if 0
// dump_spd_registers(&cpu[0]);
int i;
#if 0
// dump_spd_registers(&cpu[0]);
int i;
- for(i = 0; i < 1; i++)
{
+ for(i = 0; i < 1; i++)
dump_spd_registers();
dump_spd_registers();
- }
#endif
disable_watchdogs();
power_down_reset_check();
#endif
disable_watchdogs();
power_down_reset_check();
@@
-111,8
+102,6
@@
static void main(unsigned long bist)
ich5_watchdog_on();
#if 0
dump_pci_devices();
ich5_watchdog_on();
#if 0
dump_pci_devices();
-#endif
-#if 0
dump_pci_device(PCI_DEV(0, 0x00, 0));
dump_bar14(PCI_DEV(0, 0x00, 0));
#endif
dump_pci_device(PCI_DEV(0, 0x00, 0));
dump_bar14(PCI_DEV(0, 0x00, 0));
#endif
diff --git
a/src/mainboard/intel/truxton/romstage.c
b/src/mainboard/intel/truxton/romstage.c
index cd7d38de0e6fa864c179d5c784d7c7059129d09b..c75ce3e732af7c6f423621d63ca6ddb80230461f 100644
(file)
--- a/
src/mainboard/intel/truxton/romstage.c
+++ b/
src/mainboard/intel/truxton/romstage.c
@@
-68,9
+68,8
@@
static void main(unsigned long bist)
if (bist == 0) {
/* Skip this if there was a built in self test failure */
early_mtrr_init();
if (bist == 0) {
/* Skip this if there was a built in self test failure */
early_mtrr_init();
- if (memory_initialized())
{
+ if (memory_initialized())
skip_romstage();
skip_romstage();
- }
}
/* Set up the console */
}
/* Set up the console */
diff --git
a/src/mainboard/intel/xe7501devkit/romstage.c
b/src/mainboard/intel/xe7501devkit/romstage.c
index f270427175d2aee3e5509267d148d7c86cbce652..f393c301a36a3937f5984145c2bf98540a528615 100644
(file)
--- a/
src/mainboard/intel/xe7501devkit/romstage.c
+++ b/
src/mainboard/intel/xe7501devkit/romstage.c
@@
-46,15
+46,13
@@
static void main(unsigned long bist)
},
};
},
};
- if (bist == 0)
- {
+ if (bist == 0) {
// Skip this if there was a built in self test failure
early_mtrr_init();
enable_lapic();
}
// Get the serial port running and print a welcome banner
// Skip this if there was a built in self test failure
early_mtrr_init();
enable_lapic();
}
// Get the serial port running and print a welcome banner
-
lpc47b272_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
console_init();
lpc47b272_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
console_init();
diff --git
a/src/mainboard/iwill/dk8_htx/romstage.c
b/src/mainboard/iwill/dk8_htx/romstage.c
index fdc7199c70323d2f90deef887d188131666184c0..75584f3090f24bbce28ee10bacd95ceef910c191 100644
(file)
--- a/
src/mainboard/iwill/dk8_htx/romstage.c
+++ b/
src/mainboard/iwill/dk8_htx/romstage.c
@@
-35,13
+35,13
@@
static void memreset_setup(void)
{
if (is_cpu_pre_c0()) {
static void memreset_setup(void)
{
if (is_cpu_pre_c0()) {
- /* Set the memreset low */
- outb((
0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(
1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
- /* Ensure the BIOS has control of the memory lines */
- outb((
0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(
1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
+ /* Set the memreset low
.
*/
+ outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
+ /* Ensure the BIOS has control of the memory lines
.
*/
+ outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
} else {
} else {
- /* Ensure the CPU has control
l of the memory lines
*/
- outb((
0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(
1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
+ /* Ensure the CPU has control
of the memory lines.
*/
+ outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
}
}
}
}
@@
-50,14
+50,12
@@
static void memreset(int controllers, const struct mem_controller *ctrl)
if (is_cpu_pre_c0()) {
udelay(800);
/* Set memreset_high */
if (is_cpu_pre_c0()) {
udelay(800);
/* Set memreset_high */
- outb((
0<<7)|(0<<6)|(0<<5)|(0<<4)|(
1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
+ outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
udelay(90);
}
}
udelay(90);
}
}
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
-}
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address)
{
static inline int spd_read_byte(unsigned device, unsigned address)
{
@@
-69,7
+67,7
@@
static inline int spd_read_byte(unsigned device, unsigned address)
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/raminit.c"
#include "lib/generic_sdram.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/raminit.c"
#include "lib/generic_sdram.c"
-#include "resourcemap.c"
/* tyan does not want the default */
+#include "resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c"
#include <spd.h>
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/dualcore/dualcore.c"
#include <spd.h>
#include "cpu/amd/car/post_cache_as_ram.c"
@@
-81,34
+79,28
@@
static inline int spd_read_byte(unsigned device, unsigned address)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr[] = {
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr[] = {
- // first node
- DIMM0, DIMM2, 0, 0,
- DIMM1, DIMM3, 0, 0,
-
- // second node
- DIMM4, DIMM6, 0, 0,
- DIMM5, DIMM7, 0, 0,
+ // first node
+ DIMM0, DIMM2, 0, 0,
+ DIMM1, DIMM3, 0, 0,
+ // second node
+ DIMM4, DIMM6, 0, 0,
+ DIMM5, DIMM7, 0, 0,
};
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
+ CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
};
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
+ CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
-
int needs_reset;
unsigned bsp_apicid = 0;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
int needs_reset;
unsigned bsp_apicid = 0;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
-
enumerate_ht_chain();
enumerate_ht_chain();
-
- /* Setup the rom access for 4M */
amd8111_enable_rom();
}
amd8111_enable_rom();
}
- if (bist == 0)
{
+ if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
- }
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
@@
-143,26
+135,19
@@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
#if CONFIG_SET_FIDVID
ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
#if CONFIG_SET_FIDVID
-
{
msr_t msr;
msr=rdmsr(0xc0010042);
print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
{
msr_t msr;
msr=rdmsr(0xc0010042);
print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
-
}
}
-
enable_fid_change();
enable_fid_change();
-
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
-
init_fidvid_bsp(bsp_apicid);
init_fidvid_bsp(bsp_apicid);
-
// show final fid and vid
{
msr_t msr;
msr=rdmsr(0xc0010042);
print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
// show final fid and vid
{
msr_t msr;
msr=rdmsr(0xc0010042);
print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
-
}
#endif
}
#endif
diff --git
a/src/mainboard/iwill/dk8s2/romstage.c
b/src/mainboard/iwill/dk8s2/romstage.c
index 45d2e6c10dc246517cf888daf3cf46a5d2344896..70339e82bee66d2a6a5bd69c8253c86d3329ad4a 100644
(file)
--- a/
src/mainboard/iwill/dk8s2/romstage.c
+++ b/
src/mainboard/iwill/dk8s2/romstage.c
@@
-35,13
+35,13
@@
static void memreset_setup(void)
{
if (is_cpu_pre_c0()) {
static void memreset_setup(void)
{
if (is_cpu_pre_c0()) {
- /* Set the memreset low */
- outb((
0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(
1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
- /* Ensure the BIOS has control of the memory lines */
- outb((
0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(
1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
+ /* Set the memreset low
.
*/
+ outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
+ /* Ensure the BIOS has control of the memory lines
.
*/
+ outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
} else {
} else {
- /* Ensure the CPU has control
l of the memory lines
*/
- outb((
0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(
1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
+ /* Ensure the CPU has control
of the memory lines.
*/
+ outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
}
}
}
}
@@
-49,15
+49,13
@@
static void memreset(int controllers, const struct mem_controller *ctrl)
{
if (is_cpu_pre_c0()) {
udelay(800);
{
if (is_cpu_pre_c0()) {
udelay(800);
- /* Set memreset
_high
*/
- outb((
0<<7)|(0<<6)|(0<<5)|(0<<4)|(
1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
+ /* Set memreset
high.
*/
+ outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
udelay(90);
}
}
udelay(90);
}
}
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
-}
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address)
{
static inline int spd_read_byte(unsigned device, unsigned address)
{
@@
-69,7
+67,7
@@
static inline int spd_read_byte(unsigned device, unsigned address)
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/raminit.c"
#include "lib/generic_sdram.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/raminit.c"
#include "lib/generic_sdram.c"
-#include "northbridge/amd/amdk8/resourcemap.c"
/* tyan does not want the default */
+#include "northbridge/amd/amdk8/resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c"
#include <spd.h>
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/dualcore/dualcore.c"
#include <spd.h>
#include "cpu/amd/car/post_cache_as_ram.c"
@@
-92,23
+90,18
@@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
+ CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
+ CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
-
int needs_reset;
unsigned bsp_apicid = 0;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
int needs_reset;
unsigned bsp_apicid = 0;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
-
enumerate_ht_chain();
enumerate_ht_chain();
-
- /* Setup the rom access for 4M */
amd8111_enable_rom();
}
amd8111_enable_rom();
}
- if (bist == 0)
{
+ if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
- }
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
@@
-143,26
+136,19
@@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
#if CONFIG_SET_FIDVID
ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
#if CONFIG_SET_FIDVID
-
{
msr_t msr;
msr=rdmsr(0xc0010042);
print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
{
msr_t msr;
msr=rdmsr(0xc0010042);
print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
-
}
}
-
enable_fid_change();
enable_fid_change();
-
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
-
init_fidvid_bsp(bsp_apicid);
init_fidvid_bsp(bsp_apicid);
-
// show final fid and vid
{
msr_t msr;
msr=rdmsr(0xc0010042);
print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
// show final fid and vid
{
msr_t msr;
msr=rdmsr(0xc0010042);
print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
-
}
#endif
}
#endif
diff --git
a/src/mainboard/iwill/dk8x/romstage.c
b/src/mainboard/iwill/dk8x/romstage.c
index 45d2e6c10dc246517cf888daf3cf46a5d2344896..b8169b2b945af27002a2aa4a433696a72b45e91b 100644
(file)
--- a/
src/mainboard/iwill/dk8x/romstage.c
+++ b/
src/mainboard/iwill/dk8x/romstage.c
@@
-35,13
+35,13
@@
static void memreset_setup(void)
{
if (is_cpu_pre_c0()) {
static void memreset_setup(void)
{
if (is_cpu_pre_c0()) {
- /* Set the memreset low */
- outb((
0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(
1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
- /* Ensure the BIOS has control of the memory lines */
- outb((
0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(
1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
+ /* Set the memreset low
.
*/
+ outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
+ /* Ensure the BIOS has control of the memory lines
.
*/
+ outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
} else {
} else {
- /* Ensure the CPU has control
l of the memory lines
*/
- outb((
0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(
1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
+ /* Ensure the CPU has control
of the memory lines.
*/
+ outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
}
}
}
}
@@
-49,15
+49,13
@@
static void memreset(int controllers, const struct mem_controller *ctrl)
{
if (is_cpu_pre_c0()) {
udelay(800);
{
if (is_cpu_pre_c0()) {
udelay(800);
- /* Set memreset
_high
*/
- outb((
0<<7)|(0<<6)|(0<<5)|(0<<4)|(
1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
+ /* Set memreset
high.
*/
+ outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
udelay(90);
}
}
udelay(90);
}
}
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
-}
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address)
{
static inline int spd_read_byte(unsigned device, unsigned address)
{
@@
-69,7
+67,7
@@
static inline int spd_read_byte(unsigned device, unsigned address)
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/raminit.c"
#include "lib/generic_sdram.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/raminit.c"
#include "lib/generic_sdram.c"
-#include "northbridge/amd/amdk8/resourcemap.c"
/* tyan does not want the default */
+#include "northbridge/amd/amdk8/resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c"
#include <spd.h>
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/dualcore/dualcore.c"
#include <spd.h>
#include "cpu/amd/car/post_cache_as_ram.c"
@@
-81,34
+79,29
@@
static inline int spd_read_byte(unsigned device, unsigned address)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr[] = {
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr[] = {
-
// first node
-
DIMM0, DIMM2, 0, 0,
-
DIMM1, DIMM3, 0, 0,
+ // first node
+ DIMM0, DIMM2, 0, 0,
+ DIMM1, DIMM3, 0, 0,
// second node
// second node
-
DIMM4, DIMM6, 0, 0,
-
DIMM5, DIMM7, 0, 0,
+ DIMM4, DIMM6, 0, 0,
+ DIMM5, DIMM7, 0, 0,
};
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
+ CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
};
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
+ CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
-
int needs_reset;
unsigned bsp_apicid = 0;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
int needs_reset;
unsigned bsp_apicid = 0;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
-
enumerate_ht_chain();
enumerate_ht_chain();
-
- /* Setup the rom access for 4M */
amd8111_enable_rom();
}
amd8111_enable_rom();
}
- if (bist == 0)
{
+ if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
- }
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
@@
-143,26
+136,19
@@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
#if CONFIG_SET_FIDVID
ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
#if CONFIG_SET_FIDVID
-
{
msr_t msr;
msr=rdmsr(0xc0010042);
print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
{
msr_t msr;
msr=rdmsr(0xc0010042);
print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
-
}
}
-
enable_fid_change();
enable_fid_change();
-
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
-
init_fidvid_bsp(bsp_apicid);
init_fidvid_bsp(bsp_apicid);
-
// show final fid and vid
{
msr_t msr;
msr=rdmsr(0xc0010042);
print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
// show final fid and vid
{
msr_t msr;
msr=rdmsr(0xc0010042);
print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
-
}
#endif
}
#endif
diff --git
a/src/mainboard/jetway/j7f24/romstage.c
b/src/mainboard/jetway/j7f24/romstage.c
index 6cfaaa4173e1b1d596bd3afee1c5443bbbb42803..daacd1bebd62fbe8474264df647d947443ee062e 100644
(file)
--- a/
src/mainboard/jetway/j7f24/romstage.c
+++ b/
src/mainboard/jetway/j7f24/romstage.c
@@
-53,7
+53,8
@@
static void enable_mainboard_devices(void)
{
device_t dev;
{
device_t dev;
- dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
+ dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
+ PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
if (dev == PCI_DEV_INVALID)
die("Southbridge not found!!!\n");
if (dev == PCI_DEV_INVALID)
die("Southbridge not found!!!\n");
@@
-94,20
+95,15
@@
void main(unsigned long bist)
uart_init();
console_init();
uart_init();
console_init();
- print_spew("In romstage.c:main()\n");
-
enable_smbus();
smbus_fixup(&ctrl);
/* Halt if there was a built-in self test failure. */
report_bist_failure(bist);
enable_smbus();
smbus_fixup(&ctrl);
/* Halt if there was a built-in self test failure. */
report_bist_failure(bist);
- print_debug("Enabling mainboard devices\n");
enable_mainboard_devices();
ddr_ram_setup(&ctrl);
/* ram_check(0, 640 * 1024); */
enable_mainboard_devices();
ddr_ram_setup(&ctrl);
/* ram_check(0, 640 * 1024); */
-
- print_spew("Leaving romstage.c:main()\n");
}
}
diff --git
a/src/mainboard/jetway/pa78vm5/romstage.c
b/src/mainboard/jetway/pa78vm5/romstage.c
index a3706ef7fe228dc343a263feec5f61b045532842..990c87898761fe6a48ceee284ed7639bb4c2d89b 100644
(file)
--- a/
src/mainboard/jetway/pa78vm5/romstage.c
+++ b/
src/mainboard/jetway/pa78vm5/romstage.c
@@
-59,9
+59,7
@@
static int smbus_read_byte(u32 device, u32 address);
#define SERIAL_DEV PNP_DEV(0x2e, F71863FG_SP1)
#endif
#define SERIAL_DEV PNP_DEV(0x2e, F71863FG_SP1)
#endif
-static void activate_spd_rom(const struct mem_controller *ctrl)
-{
-}
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
static int spd_read_byte(u32 device, u32 address)
{
static int spd_read_byte(u32 device, u32 address)
{
@@
-85,8
+83,7
@@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, };
{
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, };
- u32 bsp_apicid = 0;
- u32 val;
+ u32 bsp_apicid = 0, val;
msr_t msr;
if (!cpu_init_detectedx && boot_cpu()) {
msr_t msr;
if (!cpu_init_detectedx && boot_cpu()) {
@@
-95,7
+92,6
@@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* mov bsp to bus 0xff when > 8 nodes */
set_bsp_node_CHtExtNodeCfgEn();
enumerate_ht_chain();
/* mov bsp to bus 0xff when > 8 nodes */
set_bsp_node_CHtExtNodeCfgEn();
enumerate_ht_chain();
-
sb700_pci_port80();
}
sb700_pci_port80();
}
@@
-175,7
+171,7
@@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
rs780_early_setup();
sb700_early_setup();
rs780_early_setup();
sb700_early_setup();
-
#if CONFIG_SET_FIDVID
+#if CONFIG_SET_FIDVID
msr = rdmsr(0xc0010071);
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
msr = rdmsr(0xc0010071);
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
@@
-196,7
+192,7
@@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* show final fid and vid */
msr=rdmsr(0xc0010071);
printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
/* show final fid and vid */
msr=rdmsr(0xc0010071);
printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
-
#endif
+#endif
rs780_htinit();
rs780_htinit();
diff --git
a/src/mainboard/kontron/986lcd-m/romstage.c
b/src/mainboard/kontron/986lcd-m/romstage.c
index 20d80ee648a206529dc542120b1819bb5f74d790..59d54d260f991e56267cbc4facbe398511dc9f31 100644
(file)
--- a/
src/mainboard/kontron/986lcd-m/romstage.c
+++ b/
src/mainboard/kontron/986lcd-m/romstage.c
@@
-328,9
+328,8
@@
void main(unsigned long bist)
u32 reg32;
int boot_mode = 0;
u32 reg32;
int boot_mode = 0;
- if (bist == 0)
{
+ if (bist == 0)
enable_lapic();
enable_lapic();
- }
/* Force PCIRST# */
pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, SBR);
/* Force PCIRST# */
pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, SBR);
diff --git
a/src/mainboard/kontron/kt690/romstage.c
b/src/mainboard/kontron/kt690/romstage.c
index d3586f225d0537f3e8a0634061cc9a6b38c6d2b5..16c8b0b45567bd2f2124071fcf57b83dc3dba653 100644
(file)
--- a/
src/mainboard/kontron/kt690/romstage.c
+++ b/
src/mainboard/kontron/kt690/romstage.c
@@
-48,17
+48,9
@@
#include "southbridge/amd/rs690/rs690_early_setup.c"
#include "southbridge/amd/sb600/sb600_early_setup.c"
#include "southbridge/amd/rs690/rs690_early_setup.c"
#include "southbridge/amd/sb600/sb600_early_setup.c"
-/* CAN'T BE REMOVED! crt0.S will use it. I don't know WHY!*/
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-}
-
-/* called in raminit_f.c */
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
-}
+static void memreset(int controllers, const struct mem_controller *ctrl) { }
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
-/*called in raminit_f.c */
static inline int spd_read_byte(u32 device, u32 address)
{
return smbus_read_byte(device, address);
static inline int spd_read_byte(u32 device, u32 address)
{
return smbus_read_byte(device, address);
@@
-76,9
+68,10
@@
static inline int spd_read_byte(u32 device, u32 address)
#include "cpu/amd/model_fxx/fidvid.c"
#include "northbridge/amd/amdk8/early_ht.c"
#include "cpu/amd/model_fxx/fidvid.c"
#include "northbridge/amd/amdk8/early_ht.c"
+#define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1)
+
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
- device_t dev;
static const u16 spd_addr[] = { DIMM0, 0, 0, 0, DIMM1, 0, 0, 0, };
int needs_reset = 0;
u32 bsp_apicid = 0;
static const u16 spd_addr[] = { DIMM0, 0, 0, 0, DIMM1, 0, 0, 0, };
int needs_reset = 0;
u32 bsp_apicid = 0;
@@
-90,20
+83,17
@@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
-
/* sb600_lpc_port80(); */
sb600_pci_port80();
}
/* sb600_lpc_port80(); */
sb600_pci_port80();
}
- if (bist == 0)
{
+ if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
- }
enable_rs690_dev8();
sb600_lpc_init();
enable_rs690_dev8();
sb600_lpc_init();
- dev=PNP_DEV(0x2e, W83627DHG_SP1);
- w83627dhg_enable_serial(dev, CONFIG_TTYS0_BASE);
+ w83627dhg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
#if CONFIG_USBDEBUG
uart_init();
#if CONFIG_USBDEBUG
@@
-137,8
+127,7
@@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Check to see if processor is capable of changing FIDVID */
/* otherwise it will throw a GP# when reading FIDVID_STATUS */
cpuid1 = cpuid(0x80000007);
/* Check to see if processor is capable of changing FIDVID */
/* otherwise it will throw a GP# when reading FIDVID_STATUS */
cpuid1 = cpuid(0x80000007);
- if( (cpuid1.edx & 0x6) == 0x6 ) {
-
+ if ((cpuid1.edx & 0x6) == 0x6) {
/* Read FIDVID_STATUS */
msr=rdmsr(0xc0010042);
printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
/* Read FIDVID_STATUS */
msr=rdmsr(0xc0010042);
printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
@@
-150,7
+139,6
@@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* show final fid and vid */
msr=rdmsr(0xc0010042);
printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
/* show final fid and vid */
msr=rdmsr(0xc0010042);
printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
-
} else {
printk(BIOS_DEBUG, "Changing FIDVID not supported\n");
printk(BIOS_SPEW, "... because cpuid returned %08x\n", cpuid1.edx);
} else {
printk(BIOS_DEBUG, "Changing FIDVID not supported\n");
printk(BIOS_SPEW, "... because cpuid returned %08x\n", cpuid1.edx);
diff --git
a/src/mainboard/lanner/em8510/romstage.c
b/src/mainboard/lanner/em8510/romstage.c
index d763a87bc7a2be6925adbaf63a828bb87c2ee75b..d3e288a661f8e2d9e363b2622d3fcca79ed864c4 100644
(file)
--- a/
src/mainboard/lanner/em8510/romstage.c
+++ b/
src/mainboard/lanner/em8510/romstage.c
@@
-77,15
+77,13
@@
void main(unsigned long bist)
print_pci_devices();
#endif
print_pci_devices();
#endif
- if(!bios_reset_detected()) {
+ if
(!bios_reset_detected()) {
enable_smbus();
#if 1
dump_spd_registers(&memctrl[0]);
dump_smbus_registers();
#endif
enable_smbus();
#if 1
dump_spd_registers(&memctrl[0]);
dump_smbus_registers();
#endif
-
sdram_initialize(ARRAY_SIZE(memctrl), memctrl);
sdram_initialize(ARRAY_SIZE(memctrl), memctrl);
-
}
#if 0
}
#if 0
@@
-100,4
+98,3
@@
void main(unsigned long bist)
ram_check(0x80000000, 0x81000000);
#endif
}
ram_check(0x80000000, 0x81000000);
#endif
}
-
diff --git
a/src/mainboard/lippert/frontrunner/romstage.c
b/src/mainboard/lippert/frontrunner/romstage.c
index 5578fd253a8e217ce5645e099db9da44e23fd833..1d63e492434b664a8f16e67d66824b969847a632 100644
(file)
--- a/
src/mainboard/lippert/frontrunner/romstage.c
+++ b/
src/mainboard/lippert/frontrunner/romstage.c
@@
-77,6
+77,7
@@
void main(unsigned long bist)
{.channel0 = {DIMM0, DIMM1}}
};
unsigned char temp;
{.channel0 = {DIMM0, DIMM1}}
};
unsigned char temp;
+
SystemPreInit();
msr_init();
SystemPreInit();
msr_init();
diff --git
a/src/mainboard/msi/ms7135/romstage.c
b/src/mainboard/msi/ms7135/romstage.c
index 74e966d1484742af6b4e7b2229bbc38ca9c224d7..c804b6c9fe3ae0a8bd98ce9b041f9b7ff72eb2c9 100644
(file)
--- a/
src/mainboard/msi/ms7135/romstage.c
+++ b/
src/mainboard/msi/ms7135/romstage.c
@@
-50,15
+50,8
@@
#define SERIAL_DEV PNP_DEV(0x4e, W83627THG_SP1)
#define SERIAL_DEV PNP_DEV(0x4e, W83627THG_SP1)
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
- /* FIXME: Nothing to do? */
-}
-
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
- /* FIXME: Nothing to do? */
-}
+static void memreset(int controllers, const struct mem_controller *ctrl) { }
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address)
{
static inline int spd_read_byte(unsigned device, unsigned address)
{
@@
-100,22
+93,18
@@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
};
int needs_reset;
};
int needs_reset;
- unsigned bsp_apicid = 0;
-
+ unsigned bsp_apicid = 0, nodes;
struct mem_controller ctrl[8];
struct mem_controller ctrl[8];
- unsigned nodes;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
-
sio_setup();
}
sio_setup();
}
- if (bist == 0)
{
+ if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx);
bsp_apicid = init_cpus(cpu_init_detectedx);
- }
w83627thg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
w83627thg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
@@
-138,9
+127,7
@@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
#endif
needs_reset |= ht_setup_chains_x();
#endif
needs_reset |= ht_setup_chains_x();
-
needs_reset |= ck804_early_setup_x();
needs_reset |= ck804_early_setup_x();
-
if (needs_reset) {
print_info("ht reset -\n");
soft_reset();
if (needs_reset) {
print_info("ht reset -\n");
soft_reset();
diff --git
a/src/mainboard/msi/ms7260/romstage.c
b/src/mainboard/msi/ms7260/romstage.c
index 329c679dee89ff26e30ca03729c705af9bc8da96..a3ea7d7f9f1629ce29a3ae6fdeec0c57f19832e5 100644
(file)
--- a/
src/mainboard/msi/ms7260/romstage.c
+++ b/
src/mainboard/msi/ms7260/romstage.c
@@
-117,7
+117,6
@@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
+ CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
+ CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
-
int needs_reset = 0;
unsigned bsp_apicid = 0;
int needs_reset = 0;
unsigned bsp_apicid = 0;
@@
-125,10
+124,7
@@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Nothing special needs to be done to find bus 0. */
/* Allow the HT devices to be found. */
enumerate_ht_chain();
/* Nothing special needs to be done to find bus 0. */
/* Allow the HT devices to be found. */
enumerate_ht_chain();
-
sio_setup();
sio_setup();
-
- /* Setup the MCP55. */
mcp55_enable_rom();
}
mcp55_enable_rom();
}
@@
-186,11
+182,9
@@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
print_debug_hex32(msr.lo);
print_debug("\n");
}
print_debug_hex32(msr.lo);
print_debug("\n");
}
-
enable_fid_change();
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
init_fidvid_bsp(bsp_apicid);
enable_fid_change();
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
init_fidvid_bsp(bsp_apicid);
-
{
msr_t msr = rdmsr(0xc0010042);
print_debug("end msr fid, vid ");
{
msr_t msr = rdmsr(0xc0010042);
print_debug("end msr fid, vid ");
diff --git
a/src/mainboard/msi/ms9185/romstage.c
b/src/mainboard/msi/ms9185/romstage.c
index 5c52dd29ddfe5d5a083f92d88374dc101a6aa507..ffe728d3e5756e1a45403d09d1edc002df5d5deb 100644
(file)
--- a/
src/mainboard/msi/ms9185/romstage.c
+++ b/
src/mainboard/msi/ms9185/romstage.c
@@
-52,9
+52,7
@@
#define SERIAL_DEV PNP_DEV(0x2e, PC87417_SP1)
#define RTC_DEV PNP_DEV(0x2e, PC87417_RTC)
#define SERIAL_DEV PNP_DEV(0x2e, PC87417_SP1)
#define RTC_DEV PNP_DEV(0x2e, PC87417_RTC)
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-}
+static void memreset(int controllers, const struct mem_controller *ctrl) { }
static inline void activate_spd_rom(const struct mem_controller *ctrl)
{
static inline void activate_spd_rom(const struct mem_controller *ctrl)
{
@@
-85,7
+83,7
@@
static inline int spd_read_byte(unsigned device, unsigned address)
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/raminit_f.c"
#include "lib/generic_sdram.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/raminit_f.c"
#include "lib/generic_sdram.c"
-#include "resourcemap.c"
/* msi does not want the default */
+#include "resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c"
#include <spd.h>
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/dualcore/dualcore.c"
#include <spd.h>
#include "cpu/amd/car/post_cache_as_ram.c"
@@
-116,24
+114,17
@@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
-
enumerate_ht_chain();
enumerate_ht_chain();
-
bcm5785_enable_rom();
bcm5785_enable_rom();
-
bcm5785_enable_lpc();
bcm5785_enable_lpc();
-
//enable RTC
pc87417_enable_dev(RTC_DEV);
}
//enable RTC
pc87417_enable_dev(RTC_DEV);
}
- if (bist == 0)
{
+ if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
- }
-
-// post_code(0x32);
- pc87417_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+
pc87417_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
console_init();
uart_init();
console_init();
@@
-142,11
+133,11
@@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
- printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
+ printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
setup_ms9185_resource_map();
#if 0
setup_ms9185_resource_map();
#if 0
-
dump_pci_device(PCI_DEV(0, 0x18, 0));
+ dump_pci_device(PCI_DEV(0, 0x18, 0));
dump_pci_device(PCI_DEV(0, 0x19, 0));
#endif
dump_pci_device(PCI_DEV(0, 0x19, 0));
#endif
@@
-166,7
+157,7
@@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
#endif
/* it will set up chains and store link pair for optimization later */
#endif
/* it will set up chains and store link pair for optimization later */
-
ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
+ ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
bcm5785_early_setup();
bcm5785_early_setup();
@@
-177,26
+168,19
@@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
#endif
#if CONFIG_SET_FIDVID
#endif
#if CONFIG_SET_FIDVID
-
{
msr_t msr;
msr=rdmsr(0xc0010042);
print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
{
msr_t msr;
msr=rdmsr(0xc0010042);
print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
-
}
}
-
- enable_fid_change();
-
- enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
-
+ enable_fid_change();
+ enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
init_fidvid_bsp(bsp_apicid);
init_fidvid_bsp(bsp_apicid);
-
// show final fid and vid
{
msr_t msr;
msr=rdmsr(0xc0010042);
print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
// show final fid and vid
{
msr_t msr;
msr=rdmsr(0xc0010042);
print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
-
}
#endif
}
#endif
diff --git
a/src/mainboard/msi/ms9282/romstage.c
b/src/mainboard/msi/ms9282/romstage.c
index dc9d946aed36943af5d6b6a98705078d9a58c47c..5036f177078282e52876cdf0d7b64b68960eeb8a 100644
(file)
--- a/
src/mainboard/msi/ms9282/romstage.c
+++ b/
src/mainboard/msi/ms9282/romstage.c
@@
-49,9
+49,7
@@
#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-}
+static void memreset(int controllers, const struct mem_controller *ctrl) { }
static inline void activate_spd_rom(const struct mem_controller *ctrl)
{
static inline void activate_spd_rom(const struct mem_controller *ctrl)
{
@@
-59,7
+57,7
@@
static inline void activate_spd_rom(const struct mem_controller *ctrl)
#define SMBUS_SWITCH2 0x72
unsigned device=(ctrl->channel0[0])>>8;
smbus_send_byte(SMBUS_SWITCH1, device);
#define SMBUS_SWITCH2 0x72
unsigned device=(ctrl->channel0[0])>>8;
smbus_send_byte(SMBUS_SWITCH1, device);
- smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f);
+
smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f);
}
#if 0
}
#if 0
@@
-68,7
+66,7
@@
static inline void change_i2c_mux(unsigned device)
#define SMBUS_SWITCH1 0x70
#define SMBUS_SWITHC2 0x72
smbus_send_byte(SMBUS_SWITCH1, device & 0x0f);
#define SMBUS_SWITCH1 0x70
#define SMBUS_SWITHC2 0x72
smbus_send_byte(SMBUS_SWITCH1, device & 0x0f);
- smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f);
+
smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f);
}
#endif
}
#endif
@@
-82,7
+80,7
@@
static inline int spd_read_byte(unsigned device, unsigned address)
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/raminit_f.c"
#include "lib/generic_sdram.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/raminit_f.c"
#include "lib/generic_sdram.c"
-#include "resourcemap.c"
/* msi does not want the default */
+#include "resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c"
#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
#include "cpu/amd/dualcore/dualcore.c"
#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
@@
-138,12
+136,8
@@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
-
enumerate_ht_chain();
enumerate_ht_chain();
-
sio_setup();
sio_setup();
-
- /* Setup the mcp55 */
mcp55_enable_rom();
}
mcp55_enable_rom();
}
@@
-177,7
+171,6
@@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
needs_reset = optimize_link_coherent_ht();
needs_reset |= optimize_link_incoherent_ht(sysinfo);
needs_reset |= mcp55_early_setup_x();
needs_reset = optimize_link_coherent_ht();
needs_reset |= optimize_link_incoherent_ht(sysinfo);
needs_reset |= mcp55_early_setup_x();
-
if (needs_reset) {
print_info("ht reset -\n");
soft_reset();
if (needs_reset) {
print_info("ht reset -\n");
soft_reset();
diff --git
a/src/mainboard/msi/ms9652_fam10/romstage.c
b/src/mainboard/msi/ms9652_fam10/romstage.c
index 8b297e085666f3d3df9dc928aea31aae82321851..49b3e177c375878719289321a09fff5074c5a120 100644
(file)
--- a/
src/mainboard/msi/ms9652_fam10/romstage.c
+++ b/
src/mainboard/msi/ms9652_fam10/romstage.c
@@
-51,10
+51,7
@@
#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
- /* nothing to do */
-}
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address)
{
static inline int spd_read_byte(unsigned device, unsigned address)
{
@@
-110,31
+107,23
@@
static const u8 spd_addr[] = {
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
-
- u32 bsp_apicid = 0;
- u32 val;
+ u32 bsp_apicid = 0, val, wants_reset;
u8 reg;
u8 reg;
- u32 wants_reset;
msr_t msr;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
msr_t msr;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
-
set_bsp_node_CHtExtNodeCfgEn();
enumerate_ht_chain();
set_bsp_node_CHtExtNodeCfgEn();
enumerate_ht_chain();
-
sio_setup();
sio_setup();
-
- /* Setup the mcp55 */
mcp55_enable_rom();
}
post_code(0x30);
mcp55_enable_rom();
}
post_code(0x30);
- if (bist == 0)
{
+ if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
- }
post_code(0x32);
post_code(0x32);
diff --git
a/src/mainboard/newisys/khepri/romstage.c
b/src/mainboard/newisys/khepri/romstage.c
index 11e1ecfe3ebf43bf0fffa11958e1cddbf4e42645..bd62cad9cc9c6411c18d687892c2c4601efdfe36 100644
(file)
--- a/
src/mainboard/newisys/khepri/romstage.c
+++ b/
src/mainboard/newisys/khepri/romstage.c
@@
-35,14
+35,13
@@
static void memreset_setup(void)
{
if (is_cpu_pre_c0()) {
static void memreset_setup(void)
{
if (is_cpu_pre_c0()) {
- /* Set the memreset low */
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
- /* Ensure the BIOS has control of the memory lines */
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
- }
- else {
- /* Ensure the CPU has controll of the memory lines */
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
+ /* Set the memreset low. */
+ outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
+ /* Ensure the BIOS has control of the memory lines. */
+ outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
+ } else {
+ /* Ensure the CPU has control of the memory lines. */
+ outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
}
}
}
}
@@
-50,16
+49,13
@@
static void memreset(int controllers, const struct mem_controller *ctrl)
{
if (is_cpu_pre_c0()) {
udelay(800);
{
if (is_cpu_pre_c0()) {
udelay(800);
- /* Set memreset
_high
*/
- outb((
0<<7)|(0<<6)|(0<<5)|(0<<4)|(
1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
+ /* Set memreset
high.
*/
+ outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
udelay(90);
}
}
udelay(90);
}
}
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
- /* nothing to do */
-}
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address)
{
static inline int spd_read_byte(unsigned device, unsigned address)
{
@@
-69,7
+65,7
@@
static inline int spd_read_byte(unsigned device, unsigned address)
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "lib/generic_sdram.c"
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "lib/generic_sdram.c"
-#include "resourcemap.c"
/* newisys khepri does not want the default */
+#include "resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c"
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/model_fxx/init_cpus.c"
#include "cpu/amd/dualcore/dualcore.c"
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/model_fxx/init_cpus.c"
@@
-79,35
+75,27
@@
static inline int spd_read_byte(unsigned device, unsigned address)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr [] = {
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr [] = {
-
DIMM0, DIMM2, 0, 0,
-
DIMM1, DIMM3, 0, 0,
+ DIMM0, DIMM2, 0, 0,
+ DIMM1, DIMM3, 0, 0,
#if CONFIG_MAX_PHYSICAL_CPUS > 1
#if CONFIG_MAX_PHYSICAL_CPUS > 1
-
DIMM4, DIMM6, 0, 0,
-
DIMM5, DIMM7, 0, 0,
+ DIMM4, DIMM6, 0, 0,
+ DIMM5, DIMM7, 0, 0,
#endif
};
int needs_reset;
#endif
};
int needs_reset;
- unsigned bsp_apicid = 0;
-
+ unsigned bsp_apicid = 0, nodes;
struct mem_controller ctrl[8];
struct mem_controller ctrl[8];
- unsigned nodes;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
-
enumerate_ht_chain();
enumerate_ht_chain();
-
- /* Setup the amd8111 */
amd8111_enable_rom();
}
amd8111_enable_rom();
}
- if (bist == 0)
{
+ if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx);
bsp_apicid = init_cpus(cpu_init_detectedx);
- }
-
-// post_code(0x32);
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
diff --git
a/src/mainboard/nvidia/l1_2pvv/romstage.c
b/src/mainboard/nvidia/l1_2pvv/romstage.c
index 8741071c9773ecbb30ce29a6347dcecf6c3234ed..69f3eb1fe92803c0fbcba26b77b9e78a0fbf56fe 100644
(file)
--- a/
src/mainboard/nvidia/l1_2pvv/romstage.c
+++ b/
src/mainboard/nvidia/l1_2pvv/romstage.c
@@
-53,14
+53,8
@@
#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-}
-
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
- /* nothing to do */
-}
+static void memreset(int controllers, const struct mem_controller *ctrl) { }
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address)
{
static inline int spd_read_byte(unsigned device, unsigned address)
{
@@
-112,35
+106,29
@@
static void sio_setup(void)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr [] = {
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr [] = {
-
// Node 0
-
DIMM0, DIMM2, 0, 0,
-
DIMM1, DIMM3, 0, 0,
-
// Node 1
-
DIMM4, DIMM6, 0, 0,
-
DIMM5, DIMM7, 0, 0,
+ // Node 0
+ DIMM0, DIMM2, 0, 0,
+ DIMM1, DIMM3, 0, 0,
+ // Node 1
+ DIMM4, DIMM6, 0, 0,
+ DIMM5, DIMM7, 0, 0,
};
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
+ CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
};
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
+ CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
-
int needs_reset = 0;
unsigned bsp_apicid = 0;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
int needs_reset = 0;
unsigned bsp_apicid = 0;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
-
enumerate_ht_chain();
enumerate_ht_chain();
-
sio_setup();
sio_setup();
-
- /* Setup the mcp55 */
mcp55_enable_rom();
}
mcp55_enable_rom();
}
- if (bist == 0)
{
+ if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
- }
pnp_enter_ext_func_mode(SERIAL_DEV);
pnp_write_config(SERIAL_DEV, 0x24, 0);
pnp_enter_ext_func_mode(SERIAL_DEV);
pnp_write_config(SERIAL_DEV, 0x24, 0);
@@
-183,28
+171,22
@@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
#if CONFIG_SET_FIDVID
ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
#if CONFIG_SET_FIDVID
-
{
msr_t msr;
msr=rdmsr(0xc0010042);
print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
{
msr_t msr;
msr=rdmsr(0xc0010042);
print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
-
}
}
-
enable_fid_change();
enable_fid_change();
-
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
-
init_fidvid_bsp(bsp_apicid);
init_fidvid_bsp(bsp_apicid);
-
// show final fid and vid
{
msr_t msr;
msr=rdmsr(0xc0010042);
print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
// show final fid and vid
{
msr_t msr;
msr=rdmsr(0xc0010042);
print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
-
}
#endif
}
#endif
+
init_timer(); /* Need to use TMICT to synconize FID/VID. */
needs_reset |= optimize_link_coherent_ht();
init_timer(); /* Need to use TMICT to synconize FID/VID. */
needs_reset |= optimize_link_coherent_ht();
diff --git
a/src/mainboard/pcengines/alix1c/romstage.c
b/src/mainboard/pcengines/alix1c/romstage.c
index ca87afb73cc2aa02574804de38be012a507fa8d8..209485ec64085e4f719c219276133594420c6e40 100644
(file)
--- a/
src/mainboard/pcengines/alix1c/romstage.c
+++ b/
src/mainboard/pcengines/alix1c/romstage.c
@@
-36,9
+36,7
@@
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
/* The ALIX1.C has no SMBus; the setup is hard-wired. */
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
/* The ALIX1.C has no SMBus; the setup is hard-wired. */
-static void cs5536_enable_smbus(void)
-{
-}
+static void cs5536_enable_smbus(void) { }
#include "southbridge/amd/cs5536/cs5536_early_setup.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
#include "southbridge/amd/cs5536/cs5536_early_setup.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
@@
-114,11
+112,6
@@
static u8 spd_read_byte(u8 device, u8 address)
#include "cpu/amd/model_lx/syspreinit.c"
#include "cpu/amd/model_lx/msrinit.c"
#include "cpu/amd/model_lx/syspreinit.c"
#include "cpu/amd/model_lx/msrinit.c"
-/** Early mainboard specific GPIO setup. */
-static void mb_gpio_init(void)
-{
-}
-
void main(unsigned long bist)
{
static const struct mem_controller memctrl[] = {
void main(unsigned long bist)
{
static const struct mem_controller memctrl[] = {
@@
-137,7
+130,6
@@
void main(unsigned long bist)
*/
cs5536_disable_internal_uart();
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
*/
cs5536_disable_internal_uart();
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
- mb_gpio_init();
uart_init();
console_init();
uart_init();
console_init();
diff --git
a/src/mainboard/pcengines/alix2d/romstage.c
b/src/mainboard/pcengines/alix2d/romstage.c
index fd2298ce88f9f9970f608ff5b0aae1f94af52efd..9fd001ca17320442d47ffa40ff53b70c090161a2 100644
(file)
--- a/
src/mainboard/pcengines/alix2d/romstage.c
+++ b/
src/mainboard/pcengines/alix2d/romstage.c
@@
-36,9
+36,7
@@
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
/* The ALIX.2D has no SMBus; the setup is hard-wired. */
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
/* The ALIX.2D has no SMBus; the setup is hard-wired. */
-static void cs5536_enable_smbus(void)
-{
-}
+static void cs5536_enable_smbus(void) { }
#include "southbridge/amd/cs5536/cs5536_early_setup.c"
#include "southbridge/amd/cs5536/cs5536_early_setup.c"
@@
-128,13
+126,13
@@
static void mb_gpio_init(void)
* Ugly workaround: $ wrmsr 0x5140000C 0xf00100006100
* This resets the GPIO I/O space to 0x6100.
* This may break other things, though.
* Ugly workaround: $ wrmsr 0x5140000C 0xf00100006100
* This resets the GPIO I/O space to 0x6100.
* This may break other things, though.
- */
+
*/
outl(1 << 6, GPIO_IO_BASE + GPIOL_OUTPUT_ENABLE);
outl(1 << 9, GPIO_IO_BASE + GPIOH_OUTPUT_ENABLE);
outl(1 << 11, GPIO_IO_BASE + GPIOH_OUTPUT_ENABLE);
/* outl(1 << 6, GPIO_IO_BASE + GPIOL_OUTPUT_VALUE); */ /* Led 1 enabled */
outl(1 << 6, GPIO_IO_BASE + GPIOL_OUTPUT_ENABLE);
outl(1 << 9, GPIO_IO_BASE + GPIOH_OUTPUT_ENABLE);
outl(1 << 11, GPIO_IO_BASE + GPIOH_OUTPUT_ENABLE);
/* outl(1 << 6, GPIO_IO_BASE + GPIOL_OUTPUT_VALUE); */ /* Led 1 enabled */
- outl(1 << 9, GPIO_IO_BASE + GPIOH_OUTPUT_VALUE); /* Led 2 disabled */
+
outl(1 << 9, GPIO_IO_BASE + GPIOH_OUTPUT_VALUE); /* Led 2 disabled */
outl(1 << 11, GPIO_IO_BASE + GPIOH_OUTPUT_VALUE); /* Led 3 disabled */
}
outl(1 << 11, GPIO_IO_BASE + GPIOH_OUTPUT_VALUE); /* Led 3 disabled */
}
diff --git
a/src/mainboard/rca/rm4100/romstage.c
b/src/mainboard/rca/rm4100/romstage.c
index c974ebeeddddf2643773bd538c7c4689b12b32b2..65d6bdea69d9343452dd23ae2985a69de3e76467 100644
(file)
--- a/
src/mainboard/rca/rm4100/romstage.c
+++ b/
src/mainboard/rca/rm4100/romstage.c
@@
-99,9
+99,8
@@
static void mb_early_setup(void)
void main(unsigned long bist)
{
if (bist == 0) {
void main(unsigned long bist)
{
if (bist == 0) {
- if (memory_initialized())
{
+ if (memory_initialized())
hard_reset();
hard_reset();
- }
}
/* Set southbridge and superio gpios */
}
/* Set southbridge and superio gpios */
diff --git
a/src/mainboard/roda/rk886ex/romstage.c
b/src/mainboard/roda/rk886ex/romstage.c
index aef61671dabdf1f8bbdef1d86cfd7c8c3c6c3614..109d2e81020666b5d65f28dbc5b93b6a8a04c8db 100644
(file)
--- a/
src/mainboard/roda/rk886ex/romstage.c
+++ b/
src/mainboard/roda/rk886ex/romstage.c
@@
-250,9
+250,8
@@
void main(unsigned long bist)
u32 reg32;
int boot_mode = 0;
u32 reg32;
int boot_mode = 0;
- if (bist == 0)
{
+ if (bist == 0)
enable_lapic();
enable_lapic();
- }
/* Force PCIRST# */
pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, SBR);
/* Force PCIRST# */
pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, SBR);
diff --git
a/src/mainboard/sunw/ultra40/romstage.c
b/src/mainboard/sunw/ultra40/romstage.c
index 2fa3392927bee954a72b767a137a0969a8752ac8..ceac91ddfb1af5b8e6712661ef32a961b7fbe4d7 100644
(file)
--- a/
src/mainboard/sunw/ultra40/romstage.c
+++ b/
src/mainboard/sunw/ultra40/romstage.c
@@
-28,9
+28,7
@@
#define SUPERIO_GPIO_DEV PNP_DEV(0x2e, LPC47B397_RT)
#define SUPERIO_GPIO_IO_BASE 0x400
#define SUPERIO_GPIO_DEV PNP_DEV(0x2e, LPC47B397_RT)
#define SUPERIO_GPIO_IO_BASE 0x400
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-}
+static void memreset(int controllers, const struct mem_controller *ctrl) { }
#ifdef ENABLE_ONBOARD_SCSI
static void sio_gpio_setup(void)
#ifdef ENABLE_ONBOARD_SCSI
static void sio_gpio_setup(void)
@@
-44,10
+42,7
@@
static void sio_gpio_setup(void)
}
#endif
}
#endif
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
- /* nothing to do */
-}
+static inline void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address)
{
static inline int spd_read_byte(unsigned device, unsigned address)
{
@@
-57,7
+52,7
@@
static inline int spd_read_byte(unsigned device, unsigned address)
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "lib/generic_sdram.c"
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "lib/generic_sdram.c"
-#include "resourcemap.c"
/* tyan does not want the default */
+#include "resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c"
#include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
#include "cpu/amd/dualcore/dualcore.c"
#include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
@@
-101,32
+96,27
@@
static void sio_setup(void)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr [] = {
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr [] = {
-
// Node 0
-
DIMM0, DIMM2, 0, 0,
-
DIMM1, DIMM3, 0, 0,
-
// Node 1
-
DIMM4, DIMM6, 0, 0,
-
DIMM5, DIMM7, 0, 0,
+ // Node 0
+ DIMM0, DIMM2, 0, 0,
+ DIMM1, DIMM3, 0, 0,
+ // Node 1
+ DIMM4, DIMM6, 0, 0,
+ DIMM5, DIMM7, 0, 0,
};
int needs_reset;
};
int needs_reset;
- unsigned bsp_apicid = 0;
-
+ unsigned bsp_apicid = 0, nodes;
struct mem_controller ctrl[8];
struct mem_controller ctrl[8];
- unsigned nodes;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
-
enumerate_ht_chain();
enumerate_ht_chain();
-
sio_setup();
}
sio_setup();
}
- if (bist == 0)
{
+ if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx);
bsp_apicid = init_cpus(cpu_init_detectedx);
- }
lpc47b397_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
lpc47b397_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
@@
-147,9
+137,7
@@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
#endif
needs_reset |= ht_setup_chains_x();
#endif
needs_reset |= ht_setup_chains_x();
-
needs_reset |= ck804_early_setup_x();
needs_reset |= ck804_early_setup_x();
-
if (needs_reset) {
print_info("ht reset -\n");
soft_reset();
if (needs_reset) {
print_info("ht reset -\n");
soft_reset();
diff --git
a/src/mainboard/supermicro/h8dme/romstage.c
b/src/mainboard/supermicro/h8dme/romstage.c
index de3bc2c35f8d704222731d922fe4182e21bc7414..ac3ee68857cd3b04e0fd6a0d70bfd39693c5aa86 100644
(file)
--- a/
src/mainboard/supermicro/h8dme/romstage.c
+++ b/
src/mainboard/supermicro/h8dme/romstage.c
@@
-49,9
+49,7
@@
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-}
+static void memreset(int controllers, const struct mem_controller *ctrl) { }
static inline void dump_smbus_registers(void)
{
static inline void dump_smbus_registers(void)
{
@@
-183,25
+181,19
@@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
+ CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
+ CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
-
int needs_reset = 0;
unsigned bsp_apicid = 0;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
int needs_reset = 0;
unsigned bsp_apicid = 0;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
-
enumerate_ht_chain();
enumerate_ht_chain();
-
sio_setup();
sio_setup();
-
- /* Setup the mcp55 */
mcp55_enable_rom();
}
mcp55_enable_rom();
}
- if (bist == 0)
{
+ if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
- }
pnp_enter_ext_func_mode(SERIAL_DEV);
pnp_write_config(SERIAL_DEV, 0x24, 0x84 | (1 << 6));
pnp_enter_ext_func_mode(SERIAL_DEV);
pnp_write_config(SERIAL_DEV, 0x24, 0x84 | (1 << 6));
@@
-243,7
+235,6
@@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
#if CONFIG_SET_FIDVID
ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
#if CONFIG_SET_FIDVID
-
{
msr_t msr;
msr = rdmsr(0xc0010042);
{
msr_t msr;
msr = rdmsr(0xc0010042);
@@
-251,15
+242,10
@@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
print_debug_hex32(msr.hi);
print_debug_hex32(msr.lo);
print_debug("\n");
print_debug_hex32(msr.hi);
print_debug_hex32(msr.lo);
print_debug("\n");
-
}
}
-
enable_fid_change();
enable_fid_change();
-
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
-
init_fidvid_bsp(bsp_apicid);
init_fidvid_bsp(bsp_apicid);
-
// show final fid and vid
{
msr_t msr;
// show final fid and vid
{
msr_t msr;
@@
-268,7
+254,6
@@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
print_debug_hex32(msr.hi);
print_debug_hex32(msr.lo);
print_debug("\n");
print_debug_hex32(msr.hi);
print_debug_hex32(msr.lo);
print_debug("\n");
-
}
#endif
}
#endif
diff --git
a/src/mainboard/supermicro/h8dmr/romstage.c
b/src/mainboard/supermicro/h8dmr/romstage.c
index 573f69eb30ffe375d26ede20cf88d78fdbdc12e2..d41067a2d2a4e2e422846d84b04db52a484f14bf 100644
(file)
--- a/
src/mainboard/supermicro/h8dmr/romstage.c
+++ b/
src/mainboard/supermicro/h8dmr/romstage.c
@@
-52,14
+52,8
@@
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-}
-
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
- /* nothing to do */
-}
+static void memreset(int controllers, const struct mem_controller *ctrl) { }
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address)
{
static inline int spd_read_byte(unsigned device, unsigned address)
{
@@
-85,6
+79,7
@@
static void sio_setup(void)
{
uint32_t dword;
uint8_t byte;
{
uint32_t dword;
uint8_t byte;
+
enable_smbus();
// smbusx_write_byte(1, (0x58>>1), 0, 0x80); /* select bank0 */
smbusx_write_byte(1, (0x58>>1), 0xb1, 0xff); /* set FAN ctrl to DC mode */
enable_smbus();
// smbusx_write_byte(1, (0x58>>1), 0, 0x80); /* select bank0 */
smbusx_write_byte(1, (0x58>>1), 0xb1, 0xff); /* set FAN ctrl to DC mode */
@@
-105,35
+100,29
@@
static void sio_setup(void)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr [] = {
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr [] = {
-
// Node 0
-
DIMM0, DIMM2, 0, 0,
-
DIMM1, DIMM3, 0, 0,
-
// Node 1
-
DIMM4, DIMM6, 0, 0,
-
DIMM5, DIMM7, 0, 0,
+ // Node 0
+ DIMM0, DIMM2, 0, 0,
+ DIMM1, DIMM3, 0, 0,
+ // Node 1
+ DIMM4, DIMM6, 0, 0,
+ DIMM5, DIMM7, 0, 0,
};
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
+ CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
};
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
+ CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
-
int needs_reset = 0;
unsigned bsp_apicid = 0;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
int needs_reset = 0;
unsigned bsp_apicid = 0;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
-
enumerate_ht_chain();
enumerate_ht_chain();
-
sio_setup();
sio_setup();
-
- /* Setup the mcp55 */
mcp55_enable_rom();
}
mcp55_enable_rom();
}
- if (bist == 0)
{
+ if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
- }
pnp_enter_ext_func_mode(SERIAL_DEV);
pnp_write_config(SERIAL_DEV, 0x24, 0x84 | (1 << 6));
pnp_enter_ext_func_mode(SERIAL_DEV);
pnp_write_config(SERIAL_DEV, 0x24, 0x84 | (1 << 6));
@@
-177,13
+166,9
@@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
msr=rdmsr(0xc0010042);
printk(BIOS_DEBUG, "begin msr fid, vid %08x, %08x\n", msr.hi, msr.lo);
}
msr=rdmsr(0xc0010042);
printk(BIOS_DEBUG, "begin msr fid, vid %08x, %08x\n", msr.hi, msr.lo);
}
-
enable_fid_change();
enable_fid_change();
-
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
-
init_fidvid_bsp(bsp_apicid);
init_fidvid_bsp(bsp_apicid);
-
// show final fid and vid
{
msr_t msr;
// show final fid and vid
{
msr_t msr;
diff --git
a/src/mainboard/supermicro/h8dmr_fam10/romstage.c
b/src/mainboard/supermicro/h8dmr_fam10/romstage.c
index 174a6cefcf871d2e178a575490fb0da5da8f860b..61551a718c247ecff0b8822fd349771156b79b6a 100644
(file)
--- a/
src/mainboard/supermicro/h8dmr_fam10/romstage.c
+++ b/
src/mainboard/supermicro/h8dmr_fam10/romstage.c
@@
-51,10
+51,7
@@
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
- /* nothing to do */
-}
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address)
{
static inline int spd_read_byte(unsigned device, unsigned address)
{
@@
-111,30
+108,22
@@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE +
CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
{
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE +
CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
-
- u32 bsp_apicid = 0;
- u32 val;
- u32 wants_reset;
+ u32 bsp_apicid = 0, val, wants_reset;
msr_t msr;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
msr_t msr;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
-
set_bsp_node_CHtExtNodeCfgEn();
enumerate_ht_chain();
set_bsp_node_CHtExtNodeCfgEn();
enumerate_ht_chain();
-
sio_setup();
sio_setup();
-
- /* Setup the mcp55 */
mcp55_enable_rom();
}
post_code(0x30);
mcp55_enable_rom();
}
post_code(0x30);
- if (bist == 0)
{
+ if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
- }
post_code(0x32);
post_code(0x32);
diff --git
a/src/mainboard/supermicro/h8qme_fam10/romstage.c
b/src/mainboard/supermicro/h8qme_fam10/romstage.c
index e77b139745da77209f0d29b18322fc1b983a0eaf..dac57f977bde5017c8179bcf8bb874ac7c4cfa65 100644
(file)
--- a/
src/mainboard/supermicro/h8qme_fam10/romstage.c
+++ b/
src/mainboard/supermicro/h8qme_fam10/romstage.c
@@
-117,6
+117,7
@@
static const u8 spd_addr[] = {
#define GPIO1_DEV PNP_DEV(0x2e, W83627HF_GAME_MIDI_GPIO1)
#define GPIO2_DEV PNP_DEV(0x2e, W83627HF_GPIO2)
#define GPIO3_DEV PNP_DEV(0x2e, W83627HF_GPIO3)
#define GPIO1_DEV PNP_DEV(0x2e, W83627HF_GAME_MIDI_GPIO1)
#define GPIO2_DEV PNP_DEV(0x2e, W83627HF_GPIO2)
#define GPIO3_DEV PNP_DEV(0x2e, W83627HF_GPIO3)
+
static void write_GPIO(void)
{
pnp_enter_ext_func_mode(GPIO1_DEV);
static void write_GPIO(void)
{
pnp_enter_ext_func_mode(GPIO1_DEV);
@@
-156,31
+157,24
@@
static void write_GPIO(void)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
- struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
-
- u32 bsp_apicid = 0;
- u32 val;
- u32 wants_reset;
+ struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
+ + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+ u32 bsp_apicid = 0, val, wants_reset;
msr_t msr;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
msr_t msr;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
-
set_bsp_node_CHtExtNodeCfgEn();
enumerate_ht_chain();
set_bsp_node_CHtExtNodeCfgEn();
enumerate_ht_chain();
-
sio_setup();
sio_setup();
-
- /* Setup the mcp55 */
mcp55_enable_rom();
}
post_code(0x30);
mcp55_enable_rom();
}
post_code(0x30);
- if (bist == 0)
{
+ if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
- }
post_code(0x32);
post_code(0x32);
diff --git
a/src/mainboard/supermicro/x6dai_g/romstage.c
b/src/mainboard/supermicro/x6dai_g/romstage.c
index b95bbc9ebf4409811785154683b014ae69dc56f1..2873d8af994dcbda705de3c1d83ce5b9b5d8a77f 100644
(file)
--- a/
src/mainboard/supermicro/x6dai_g/romstage.c
+++ b/
src/mainboard/supermicro/x6dai_g/romstage.c
@@
-60,9
+60,8
@@
static void main(unsigned long bist)
if (bist == 0) {
/* Skip this if there was a built in self test failure */
early_mtrr_init();
if (bist == 0) {
/* Skip this if there was a built in self test failure */
early_mtrr_init();
- if (memory_initialized())
{
+ if (memory_initialized())
skip_romstage();
skip_romstage();
- }
}
/* Setup the console */
}
/* Setup the console */
@@
-77,16
+76,13
@@
static void main(unsigned long bist)
/* config LPC decode for flash memory access */
device_t dev;
dev = pci_locate_device(PCI_ID(0x8086, 0x25a1), 0);
/* config LPC decode for flash memory access */
device_t dev;
dev = pci_locate_device(PCI_ID(0x8086, 0x25a1), 0);
- if (dev == PCI_DEV_INVALID)
{
+ if (dev == PCI_DEV_INVALID)
die("Missing 6300ESB?");
die("Missing 6300ESB?");
- }
pci_write_config32(dev, 0xe8, 0x00000000);
pci_write_config8(dev, 0xf0, 0x00);
#if 0
display_cpuid_update_microcode();
pci_write_config32(dev, 0xe8, 0x00000000);
pci_write_config8(dev, 0xf0, 0x00);
#if 0
display_cpuid_update_microcode();
-#endif
-#if 0
print_pci_devices();
#endif
#if 1
print_pci_devices();
#endif
#if 1
@@
-94,9
+90,8
@@
static void main(unsigned long bist)
#endif
#if 0
int i;
#endif
#if 0
int i;
- for(i = 0; i < 1; i++)
{
+ for(i = 0; i < 1; i++)
dump_spd_registers();
dump_spd_registers();
- }
#endif
disable_watchdogs();
sdram_initialize(ARRAY_SIZE(mch), mch);
#endif
disable_watchdogs();
sdram_initialize(ARRAY_SIZE(mch), mch);
diff --git
a/src/mainboard/supermicro/x6dhe_g/romstage.c
b/src/mainboard/supermicro/x6dhe_g/romstage.c
index 995234b808ce85a75bed8391fa781c4c74df7423..c5107d9fc1961554bacb202e7c3180307c224ee8 100644
(file)
--- a/
src/mainboard/supermicro/x6dhe_g/romstage.c
+++ b/
src/mainboard/supermicro/x6dhe_g/romstage.c
@@
-49,12
+49,6
@@
static void main(unsigned long bist)
static const struct mem_controller mch[] = {
{
.node_id = 0,
static const struct mem_controller mch[] = {
{
.node_id = 0,
- /*
- .f0 = PCI_DEV(0, 0x00, 0),
- .f1 = PCI_DEV(0, 0x00, 1),
- .f2 = PCI_DEV(0, 0x00, 2),
- .f3 = PCI_DEV(0, 0x00, 3),
- */
.channel0 = {DIMM0, DIMM1, DIMM2, DIMM3, },
.channel1 = {DIMM4, DIMM5, DIMM6, DIMM7, },
}
.channel0 = {DIMM0, DIMM1, DIMM2, DIMM3, },
.channel1 = {DIMM4, DIMM5, DIMM6, DIMM7, },
}
@@
-63,9
+57,8
@@
static void main(unsigned long bist)
if (bist == 0) {
/* Skip this if there was a built in self test failure */
early_mtrr_init();
if (bist == 0) {
/* Skip this if there was a built in self test failure */
early_mtrr_init();
- if (memory_initialized())
{
+ if (memory_initialized())
skip_romstage();
skip_romstage();
- }
}
/* Setup the console */
}
/* Setup the console */
@@
-83,16
+76,13
@@
static void main(unsigned long bist)
/* config LPC decode for flash memory access */
device_t dev;
dev = pci_locate_device(PCI_ID(0x8086, 0x25a1), 0);
/* config LPC decode for flash memory access */
device_t dev;
dev = pci_locate_device(PCI_ID(0x8086, 0x25a1), 0);
- if (dev == PCI_DEV_INVALID)
{
+ if (dev == PCI_DEV_INVALID)
die("Missing esb6300?");
die("Missing esb6300?");
- }
pci_write_config32(dev, 0xe8, 0x00000000);
pci_write_config8(dev, 0xf0, 0x00);
#if 0
display_cpuid_update_microcode();
pci_write_config32(dev, 0xe8, 0x00000000);
pci_write_config8(dev, 0xf0, 0x00);
#if 0
display_cpuid_update_microcode();
-#endif
-#if 0
print_pci_devices();
#endif
#if 1
print_pci_devices();
#endif
#if 1
@@
-101,9
+91,8
@@
static void main(unsigned long bist)
#if 0
// dump_spd_registers(&cpu[0]);
int i;
#if 0
// dump_spd_registers(&cpu[0]);
int i;
- for(i = 0; i < 1; i++)
{
+ for(i = 0; i < 1; i++)
dump_spd_registers();
dump_spd_registers();
- }
#endif
disable_watchdogs();
// dump_ipmi_registers();
#endif
disable_watchdogs();
// dump_ipmi_registers();
@@
-111,8
+100,6
@@
static void main(unsigned long bist)
sdram_initialize(ARRAY_SIZE(mch), mch);
#if 0
dump_pci_devices();
sdram_initialize(ARRAY_SIZE(mch), mch);
#if 0
dump_pci_devices();
-#endif
-#if 0
dump_pci_device(PCI_DEV(0, 0x00, 0));
dump_bar14(PCI_DEV(0, 0x00, 0));
#endif
dump_pci_device(PCI_DEV(0, 0x00, 0));
dump_bar14(PCI_DEV(0, 0x00, 0));
#endif
diff --git
a/src/mainboard/supermicro/x6dhe_g2/romstage.c
b/src/mainboard/supermicro/x6dhe_g2/romstage.c
index eef04d4f2819365309f826005e670527be345bf0..af042477d2c6a87ba2f3c76710900e4f9dcde2f0 100644
(file)
--- a/
src/mainboard/supermicro/x6dhe_g2/romstage.c
+++ b/
src/mainboard/supermicro/x6dhe_g2/romstage.c
@@
-47,13
+47,7
@@
static void main(unsigned long bist)
static const struct mem_controller mch[] = {
{
.node_id = 0,
static const struct mem_controller mch[] = {
{
.node_id = 0,
- /*
- .f0 = PCI_DEV(0, 0x00, 0),
- .f1 = PCI_DEV(0, 0x00, 1),
- .f2 = PCI_DEV(0, 0x00, 2),
- .f3 = PCI_DEV(0, 0x00, 3),
- */
- .channel0 = {DIMM3, DIMM2, DIMM1, DIMM0, },
+ .channel0 = {DIMM3, DIMM2, DIMM1, DIMM0, },
.channel1 = {DIMM7, DIMM6, DIMM5, DIMM4, },
}
};
.channel1 = {DIMM7, DIMM6, DIMM5, DIMM4, },
}
};
@@
-61,9
+55,8
@@
static void main(unsigned long bist)
if (bist == 0) {
/* Skip this if there was a built in self test failure */
early_mtrr_init();
if (bist == 0) {
/* Skip this if there was a built in self test failure */
early_mtrr_init();
- if (memory_initialized())
{
+ if (memory_initialized())
skip_romstage();
skip_romstage();
- }
}
/* Setup the console */
}
/* Setup the console */
@@
-81,16
+74,13
@@
static void main(unsigned long bist)
/* config LPC decode for flash memory access */
device_t dev;
dev = pci_locate_device(PCI_ID(0x8086, 0x25a1), 0);
/* config LPC decode for flash memory access */
device_t dev;
dev = pci_locate_device(PCI_ID(0x8086, 0x25a1), 0);
- if (dev == PCI_DEV_INVALID)
{
+ if (dev == PCI_DEV_INVALID)
die("Missing ich5r?");
die("Missing ich5r?");
- }
pci_write_config32(dev, 0xe8, 0x00000000);
pci_write_config8(dev, 0xf0, 0x00);
#if 0
display_cpuid_update_microcode();
pci_write_config32(dev, 0xe8, 0x00000000);
pci_write_config8(dev, 0xf0, 0x00);
#if 0
display_cpuid_update_microcode();
-#endif
-#if 0
print_pci_devices();
#endif
#if 1
print_pci_devices();
#endif
#if 1
@@
-99,9
+89,8
@@
static void main(unsigned long bist)
#if 0
// dump_spd_registers(&cpu[0]);
int i;
#if 0
// dump_spd_registers(&cpu[0]);
int i;
- for(i = 0; i < 1; i++)
{
+ for(i = 0; i < 1; i++)
dump_spd_registers();
dump_spd_registers();
- }
#endif
disable_watchdogs();
// dump_ipmi_registers();
#endif
disable_watchdogs();
// dump_ipmi_registers();
diff --git
a/src/mainboard/supermicro/x6dhr_ig/romstage.c
b/src/mainboard/supermicro/x6dhr_ig/romstage.c
index 89429466cfa36b80ab64ac1b5f257732f361c67a..839be041842c49c21d2784bde242627b5d21be01 100644
(file)
--- a/
src/mainboard/supermicro/x6dhr_ig/romstage.c
+++ b/
src/mainboard/supermicro/x6dhr_ig/romstage.c
@@
-62,9
+62,8
@@
static void main(unsigned long bist)
if (bist == 0) {
/* Skip this if there was a built in self test failure */
early_mtrr_init();
if (bist == 0) {
/* Skip this if there was a built in self test failure */
early_mtrr_init();
- if (memory_initialized())
{
+ if (memory_initialized())
skip_romstage();
skip_romstage();
- }
}
/* Setup the console */
}
/* Setup the console */
@@
-82,16
+81,13
@@
static void main(unsigned long bist)
/* config LPC decode for flash memory access */
device_t dev;
dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0);
/* config LPC decode for flash memory access */
device_t dev;
dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0);
- if (dev == PCI_DEV_INVALID)
{
+ if (dev == PCI_DEV_INVALID)
die("Missing ich5?");
die("Missing ich5?");
- }
pci_write_config32(dev, 0xe8, 0x00000000);
pci_write_config8(dev, 0xf0, 0x00);
#if 0
display_cpuid_update_microcode();
pci_write_config32(dev, 0xe8, 0x00000000);
pci_write_config8(dev, 0xf0, 0x00);
#if 0
display_cpuid_update_microcode();
-#endif
-#if 0
print_pci_devices();
#endif
#if 1
print_pci_devices();
#endif
#if 1
@@
-100,9
+96,8
@@
static void main(unsigned long bist)
#if 0
// dump_spd_registers(&cpu[0]);
int i;
#if 0
// dump_spd_registers(&cpu[0]);
int i;
- for(i = 0; i < 1; i++)
{
+ for(i = 0; i < 1; i++)
dump_spd_registers();
dump_spd_registers();
- }
#endif
disable_watchdogs();
// dump_ipmi_registers();
#endif
disable_watchdogs();
// dump_ipmi_registers();
diff --git
a/src/mainboard/supermicro/x6dhr_ig2/romstage.c
b/src/mainboard/supermicro/x6dhr_ig2/romstage.c
index ba6ba914be253f5c617bea5c851fa9afc83269ff..76c94b228f531aad3731d73b922337b8fc20df34 100644
(file)
--- a/
src/mainboard/supermicro/x6dhr_ig2/romstage.c
+++ b/
src/mainboard/supermicro/x6dhr_ig2/romstage.c
@@
-48,12
+48,6
@@
static void main(unsigned long bist)
static const struct mem_controller mch[] = {
{
.node_id = 0,
static const struct mem_controller mch[] = {
{
.node_id = 0,
- /*
- .f0 = PCI_DEV(0, 0x00, 0),
- .f1 = PCI_DEV(0, 0x00, 1),
- .f2 = PCI_DEV(0, 0x00, 2),
- .f3 = PCI_DEV(0, 0x00, 3),
- */
.channel0 = {DIMM3, DIMM2, DIMM1, DIMM0, },
.channel1 = {DIMM7, DIMM6, DIMM5, DIMM4, },
}
.channel0 = {DIMM3, DIMM2, DIMM1, DIMM0, },
.channel1 = {DIMM7, DIMM6, DIMM5, DIMM4, },
}
@@
-62,9
+56,8
@@
static void main(unsigned long bist)
if (bist == 0) {
/* Skip this if there was a built in self test failure */
early_mtrr_init();
if (bist == 0) {
/* Skip this if there was a built in self test failure */
early_mtrr_init();
- if (memory_initialized())
{
+ if (memory_initialized())
skip_romstage();
skip_romstage();
- }
}
/* Setup the console */
}
/* Setup the console */
@@
-82,16
+75,13
@@
static void main(unsigned long bist)
/* config LPC decode for flash memory access */
device_t dev;
dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0);
/* config LPC decode for flash memory access */
device_t dev;
dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0);
- if (dev == PCI_DEV_INVALID)
{
+ if (dev == PCI_DEV_INVALID)
die("Missing ich5?");
die("Missing ich5?");
- }
pci_write_config32(dev, 0xe8, 0x00000000);
pci_write_config8(dev, 0xf0, 0x00);
#if 0
display_cpuid_update_microcode();
pci_write_config32(dev, 0xe8, 0x00000000);
pci_write_config8(dev, 0xf0, 0x00);
#if 0
display_cpuid_update_microcode();
-#endif
-#if 0
print_pci_devices();
#endif
#if 1
print_pci_devices();
#endif
#if 1
@@
-100,9
+90,8
@@
static void main(unsigned long bist)
#if 0
// dump_spd_registers(&cpu[0]);
int i;
#if 0
// dump_spd_registers(&cpu[0]);
int i;
- for(i = 0; i < 1; i++)
{
+ for(i = 0; i < 1; i++)
dump_spd_registers();
dump_spd_registers();
- }
#endif
disable_watchdogs();
// dump_ipmi_registers();
#endif
disable_watchdogs();
// dump_ipmi_registers();
@@
-110,8
+99,6
@@
static void main(unsigned long bist)
sdram_initialize(ARRAY_SIZE(mch), mch);
#if 0
dump_pci_devices();
sdram_initialize(ARRAY_SIZE(mch), mch);
#if 0
dump_pci_devices();
-#endif
-#if 0
dump_pci_device(PCI_DEV(0, 0x00, 0));
dump_bar14(PCI_DEV(0, 0x00, 0));
#endif
dump_pci_device(PCI_DEV(0, 0x00, 0));
dump_bar14(PCI_DEV(0, 0x00, 0));
#endif
diff --git
a/src/mainboard/technexion/tim5690/romstage.c
b/src/mainboard/technexion/tim5690/romstage.c
index 52d61f017a9f0105546a3d318b9719316da42d34..f9f1e70ce1f7d0e288585c32d829ed26cd5c2e96 100644
(file)
--- a/
src/mainboard/technexion/tim5690/romstage.c
+++ b/
src/mainboard/technexion/tim5690/romstage.c
@@
-47,17
+47,9
@@
#include "southbridge/amd/rs690/rs690_early_setup.c"
#include "southbridge/amd/sb600/sb600_early_setup.c"
#include "southbridge/amd/rs690/rs690_early_setup.c"
#include "southbridge/amd/sb600/sb600_early_setup.c"
-/* CAN'T BE REMOVED! crt0.S will use it. I don't know WHY!*/
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-}
-
-/* called in raminit_f.c */
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
-}
+static void memreset(int controllers, const struct mem_controller *ctrl) { }
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
-/*called in raminit_f.c */
static inline int spd_read_byte(u32 device, u32 address)
{
return smbus_read_byte(device, address);
static inline int spd_read_byte(u32 device, u32 address)
{
return smbus_read_byte(device, address);
@@
-90,7
+82,6
@@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
-
/* sb600_lpc_port80(); */
sb600_pci_port80();
}
/* sb600_lpc_port80(); */
sb600_pci_port80();
}
@@
-98,9
+89,8
@@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
technexion_post_code_init();
technexion_post_code(LED_MESSAGE_START);
technexion_post_code_init();
technexion_post_code(LED_MESSAGE_START);
- if (bist == 0)
{
+ if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
- }
enable_rs690_dev8();
sb600_lpc_init();
enable_rs690_dev8();
sb600_lpc_init();
@@
-141,8
+131,7
@@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Check to see if processor is capable of changing FIDVID */
/* otherwise it will throw a GP# when reading FIDVID_STATUS */
cpuid1 = cpuid(0x80000007);
/* Check to see if processor is capable of changing FIDVID */
/* otherwise it will throw a GP# when reading FIDVID_STATUS */
cpuid1 = cpuid(0x80000007);
- if( (cpuid1.edx & 0x6) == 0x6 ) {
-
+ if ((cpuid1.edx & 0x6) == 0x6) {
/* Read FIDVID_STATUS */
msr=rdmsr(0xc0010042);
printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
/* Read FIDVID_STATUS */
msr=rdmsr(0xc0010042);
printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
@@
-154,7
+143,6
@@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* show final fid and vid */
msr=rdmsr(0xc0010042);
printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
/* show final fid and vid */
msr=rdmsr(0xc0010042);
printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
-
} else {
printk(BIOS_DEBUG, "Changing FIDVID not supported\n");
}
} else {
printk(BIOS_DEBUG, "Changing FIDVID not supported\n");
}
diff --git
a/src/mainboard/technexion/tim8690/romstage.c
b/src/mainboard/technexion/tim8690/romstage.c
index a172930e41b6fb02f5609d9da78f168ce3727fc1..276ca08682862ceb267b5a3baf1a2a8aab9ae7f6 100644
(file)
--- a/
src/mainboard/technexion/tim8690/romstage.c
+++ b/
src/mainboard/technexion/tim8690/romstage.c
@@
-47,17
+47,9
@@
#include "southbridge/amd/rs690/rs690_early_setup.c"
#include "southbridge/amd/sb600/sb600_early_setup.c"
#include "southbridge/amd/rs690/rs690_early_setup.c"
#include "southbridge/amd/sb600/sb600_early_setup.c"
-/* CAN'T BE REMOVED! crt0.S will use it. I don't know WHY!*/
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-}
-
-/* called in raminit_f.c */
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
-}
+static void memreset(int controllers, const struct mem_controller *ctrl) { }
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
-/*called in raminit_f.c */
static inline int spd_read_byte(u32 device, u32 address)
{
return smbus_read_byte(device, address);
static inline int spd_read_byte(u32 device, u32 address)
{
return smbus_read_byte(device, address);
@@
-88,14
+80,12
@@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
-
/* sb600_lpc_port80(); */
sb600_pci_port80();
}
/* sb600_lpc_port80(); */
sb600_pci_port80();
}
- if (bist == 0)
{
+ if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
- }
enable_rs690_dev8();
sb600_lpc_init();
enable_rs690_dev8();
sb600_lpc_init();
@@
-136,8
+126,7
@@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Check to see if processor is capable of changing FIDVID */
/* otherwise it will throw a GP# when reading FIDVID_STATUS */
cpuid1 = cpuid(0x80000007);
/* Check to see if processor is capable of changing FIDVID */
/* otherwise it will throw a GP# when reading FIDVID_STATUS */
cpuid1 = cpuid(0x80000007);
- if( (cpuid1.edx & 0x6) == 0x6 ) {
-
+ if ((cpuid1.edx & 0x6) == 0x6 ) {
/* Read FIDVID_STATUS */
msr=rdmsr(0xc0010042);
printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
/* Read FIDVID_STATUS */
msr=rdmsr(0xc0010042);
printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
@@
-149,7
+138,6
@@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* show final fid and vid */
msr=rdmsr(0xc0010042);
printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
/* show final fid and vid */
msr=rdmsr(0xc0010042);
printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
-
} else {
printk(BIOS_DEBUG, "Changing FIDVID not supported\n");
}
} else {
printk(BIOS_DEBUG, "Changing FIDVID not supported\n");
}
diff --git
a/src/mainboard/televideo/tc7020/romstage.c
b/src/mainboard/televideo/tc7020/romstage.c
index 177c44739fdcffcc18d936a14d8cc3279cf8e9ab..8074c874e14f732ee55864469a001635cc0a34b6 100644
(file)
--- a/
src/mainboard/televideo/tc7020/romstage.c
+++ b/
src/mainboard/televideo/tc7020/romstage.c
@@
-35,20
+35,11
@@
static void main(unsigned long bist)
{
static void main(unsigned long bist)
{
- /* Initialize the serial console. */
pc97317_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
console_init();
pc97317_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
console_init();
-
- /* Halt if there was a built in self test failure. */
report_bist_failure(bist);
report_bist_failure(bist);
-
cs5530_enable_rom();
cs5530_enable_rom();
-
- /* Initialize RAM. */
sdram_init();
sdram_init();
-
- /* Check whether RAM works. */
/* ram_check(0, 640 * 1024); */
}
/* ram_check(0, 640 * 1024); */
}
-
diff --git
a/src/mainboard/thomson/ip1000/romstage.c
b/src/mainboard/thomson/ip1000/romstage.c
index b34f963b5fe75bd906ba4c61609b9c58c8fa9302..e399dd128f9621f25fe324ccacab2ffd539caddd 100644
(file)
--- a/
src/mainboard/thomson/ip1000/romstage.c
+++ b/
src/mainboard/thomson/ip1000/romstage.c
@@
-98,9
+98,8
@@
static void mb_early_setup(void)
void main(unsigned long bist)
{
if (bist == 0) {
void main(unsigned long bist)
{
if (bist == 0) {
- if (memory_initialized())
{
+ if (memory_initialized())
hard_reset();
hard_reset();
- }
}
/* Set southbridge and superio gpios */
}
/* Set southbridge and superio gpios */
diff --git
a/src/mainboard/traverse/geos/romstage.c
b/src/mainboard/traverse/geos/romstage.c
index 79464970e4c3e8a96d76a5753bac50d12e83a7a6..f6a4ccfece5fe14ef60d152ffc9f89b8873141f3 100644
(file)
--- a/
src/mainboard/traverse/geos/romstage.c
+++ b/
src/mainboard/traverse/geos/romstage.c
@@
-52,11
+52,6
@@
static inline int spd_read_byte(unsigned int device, unsigned int address)
#include "cpu/amd/model_lx/syspreinit.c"
#include "cpu/amd/model_lx/msrinit.c"
#include "cpu/amd/model_lx/syspreinit.c"
#include "cpu/amd/model_lx/msrinit.c"
-static void mb_gpio_init(void)
-{
- /* Early mainboard specific GPIO setup. */
-}
-
void main(unsigned long bist)
{
post_code(0x01);
void main(unsigned long bist)
{
post_code(0x01);
@@
-78,7
+73,6
@@
void main(unsigned long bist)
*/
/* If debug. real setup done in chipset init via devicetree.cb. */
cs5536_setup_onchipuart(1);
*/
/* If debug. real setup done in chipset init via devicetree.cb. */
cs5536_setup_onchipuart(1);
- mb_gpio_init();
uart_init();
console_init();
uart_init();
console_init();
diff --git
a/src/mainboard/tyan/s2735/romstage.c
b/src/mainboard/tyan/s2735/romstage.c
index 4f954581135635a359fb2f7899b3912ef35047d7..c7c5eb036a386ae528d813a118fbcb369d9a8f5d 100644
(file)
--- a/
src/mainboard/tyan/s2735/romstage.c
+++ b/
src/mainboard/tyan/s2735/romstage.c
@@
-46,9
+46,8
@@
void main(unsigned long bist)
},
};
},
};
- if (bist == 0)
{
+ if (bist == 0)
enable_lapic();
enable_lapic();
- }
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
@@
-57,15
+56,12
@@
void main(unsigned long bist)
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
- if
(bios_reset_detected()) {
+ if
(bios_reset_detected())
hard_reset();
hard_reset();
- }
enable_smbus();
#if 0
dump_spd_registers(&memctrl[0]);
enable_smbus();
#if 0
dump_spd_registers(&memctrl[0]);
-#endif
-#if 0
dump_smbus_registers();
#endif
dump_smbus_registers();
#endif
@@
-79,4
+75,3
@@
void main(unsigned long bist)
dump_pci_device(PCI_DEV(0, 0, 0));
#endif
}
dump_pci_device(PCI_DEV(0, 0, 0));
#endif
}
-
diff --git
a/src/mainboard/tyan/s2850/romstage.c
b/src/mainboard/tyan/s2850/romstage.c
index 41a4ffa79f1127ef6aa2d68a1de98b0aed529093..4f78797030b665a560bccf2570bb64fd8cfe03c5 100644
(file)
--- a/
src/mainboard/tyan/s2850/romstage.c
+++ b/
src/mainboard/tyan/s2850/romstage.c
@@
-29,28
+29,23
@@
static void memreset_setup(void)
{
static void memreset_setup(void)
{
- if (is_cpu_pre_c0()) {
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0
- }
- else {
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1
- }
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
+ if (is_cpu_pre_c0())
+ outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0
+ else
+ outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1
+ outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
}
static void memreset(int controllers, const struct mem_controller *ctrl)
{
if (is_cpu_pre_c0()) {
udelay(800);
}
static void memreset(int controllers, const struct mem_controller *ctrl)
{
if (is_cpu_pre_c0()) {
udelay(800);
- outb((
0<<7)|(0<<6)|(0<<5)|(0<<4)|(
1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
+ outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
udelay(90);
}
}
udelay(90);
}
}
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
- /* nothing to do */
-}
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address)
{
static inline int spd_read_byte(unsigned device, unsigned address)
{
@@
-86,16
+81,12
@@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
-
enumerate_ht_chain();
enumerate_ht_chain();
-
- /* Setup the amd8111 */
amd8111_enable_rom();
}
amd8111_enable_rom();
}
- if (bist == 0)
{
+ if (bist == 0)
init_cpus(cpu_init_detectedx);
init_cpus(cpu_init_detectedx);
- }
// post_code(0x32);
// post_code(0x32);
@@
-128,4
+119,3
@@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_cache_as_ram();
}
post_cache_as_ram();
}
-
diff --git
a/src/mainboard/tyan/s2875/romstage.c
b/src/mainboard/tyan/s2875/romstage.c
index 275ff2720cca67d6bbe486be1365487408285db4..55448bd381a9e3f15f02cd427c5061adbed95be9 100644
(file)
--- a/
src/mainboard/tyan/s2875/romstage.c
+++ b/
src/mainboard/tyan/s2875/romstage.c
@@
-29,28
+29,23
@@
static void memreset_setup(void)
{
static void memreset_setup(void)
{
- if (is_cpu_pre_c0()) {
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0
- }
- else {
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1
- }
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
+ if (is_cpu_pre_c0())
+ outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0
+ else
+ outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1
+ outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
}
static void memreset(int controllers, const struct mem_controller *ctrl)
{
if (is_cpu_pre_c0()) {
udelay(800);
}
static void memreset(int controllers, const struct mem_controller *ctrl)
{
if (is_cpu_pre_c0()) {
udelay(800);
- outb((
0<<7)|(0<<6)|(0<<5)|(0<<4)|(
1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
+ outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
udelay(90);
}
}
udelay(90);
}
}
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
- /* nothing to do */
-}
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address)
{
static inline int spd_read_byte(unsigned device, unsigned address)
{
@@
-97,15
+92,12
@@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
-
enumerate_ht_chain();
enumerate_ht_chain();
-
amd8111_enable_rom();
}
amd8111_enable_rom();
}
- if (bist == 0)
{
+ if (bist == 0)
init_cpus(cpu_init_detectedx);
init_cpus(cpu_init_detectedx);
- }
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
@@
-135,6
+127,4
@@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
sdram_initialize(ARRAY_SIZE(cpu), cpu);
post_cache_as_ram();
sdram_initialize(ARRAY_SIZE(cpu), cpu);
post_cache_as_ram();
-
}
}
-
diff --git
a/src/mainboard/tyan/s2880/romstage.c
b/src/mainboard/tyan/s2880/romstage.c
index d9328dd18618f80db4184e865a7b02a448823caa..9ecf09bd3e3e17fc0f8ee2deba2e2e34a47b2bf8 100644
(file)
--- a/
src/mainboard/tyan/s2880/romstage.c
+++ b/
src/mainboard/tyan/s2880/romstage.c
@@
-29,28
+29,23
@@
static void memreset_setup(void)
{
static void memreset_setup(void)
{
- if (is_cpu_pre_c0()) {
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0
- }
- else {
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1
- }
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
+ if (is_cpu_pre_c0())
+ outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0
+ else
+ outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1
+ outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
}
static void memreset(int controllers, const struct mem_controller *ctrl)
{
if (is_cpu_pre_c0()) {
udelay(800);
}
static void memreset(int controllers, const struct mem_controller *ctrl)
{
if (is_cpu_pre_c0()) {
udelay(800);
- outb((
0<<7)|(0<<6)|(0<<5)|(0<<4)|(
1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
+ outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
udelay(90);
}
}
udelay(90);
}
}
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
- /* nothing to do */
-}
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address)
{
static inline int spd_read_byte(unsigned device, unsigned address)
{
@@
-97,16
+92,12
@@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
-
enumerate_ht_chain();
enumerate_ht_chain();
-
amd8111_enable_rom();
}
amd8111_enable_rom();
}
- if (bist == 0)
{
+ if (bist == 0)
init_cpus(cpu_init_detectedx);
init_cpus(cpu_init_detectedx);
- }
-
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
@@
-138,4
+129,3
@@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_cache_as_ram();
}
post_cache_as_ram();
}
-
diff --git
a/src/mainboard/tyan/s2881/romstage.c
b/src/mainboard/tyan/s2881/romstage.c
index c7dce483a2517a0c73f703cfcf392119ae894f9a..9a20be7089baad968ce712790ca1257a68839dfc 100644
(file)
--- a/
src/mainboard/tyan/s2881/romstage.c
+++ b/
src/mainboard/tyan/s2881/romstage.c
@@
-28,28
+28,23
@@
static void memreset_setup(void)
{
static void memreset_setup(void)
{
- if (is_cpu_pre_c0()) {
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0
- }
- else {
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1
- }
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
+ if (is_cpu_pre_c0())
+ outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0
+ else
+ outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1
+ outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
}
static void memreset(int controllers, const struct mem_controller *ctrl)
{
if (is_cpu_pre_c0()) {
udelay(800);
}
static void memreset(int controllers, const struct mem_controller *ctrl)
{
if (is_cpu_pre_c0()) {
udelay(800);
- outb((
0<<7)|(0<<6)|(0<<5)|(0<<4)|(
1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
+ outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
udelay(90);
}
}
udelay(90);
}
}
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
- /* nothing to do */
-}
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address)
{
static inline int spd_read_byte(unsigned device, unsigned address)
{
@@
-69,33
+64,27
@@
static inline int spd_read_byte(unsigned device, unsigned address)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr [] = {
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr [] = {
-
DIMM0, DIMM2, 0, 0,
-
DIMM1, DIMM3, 0, 0,
+ DIMM0, DIMM2, 0, 0,
+ DIMM1, DIMM3, 0, 0,
#if CONFIG_MAX_PHYSICAL_CPUS > 1
#if CONFIG_MAX_PHYSICAL_CPUS > 1
-
DIMM4, DIMM6, 0, 0,
-
DIMM5, DIMM7, 0, 0,
+ DIMM4, DIMM6, 0, 0,
+ DIMM5, DIMM7, 0, 0,
#endif
};
int needs_reset;
#endif
};
int needs_reset;
- unsigned bsp_apicid = 0;
-
+ unsigned bsp_apicid = 0, nodes;
struct mem_controller ctrl[8];
struct mem_controller ctrl[8];
- unsigned nodes;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
-
enumerate_ht_chain();
enumerate_ht_chain();
-
- /* Setup the amd8111 */
amd8111_enable_rom();
}
amd8111_enable_rom();
}
- if (bist == 0)
{
+ if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx);
bsp_apicid = init_cpus(cpu_init_detectedx);
- }
// post_code(0x32);
// post_code(0x32);
@@
-131,8
+120,6
@@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
enable_smbus();
#if 0
dump_spd_registers(&cpu[0]);
enable_smbus();
#if 0
dump_spd_registers(&cpu[0]);
-#endif
-#if 0
dump_smbus_registers();
#endif
dump_smbus_registers();
#endif
@@
-151,4
+138,3
@@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_cache_as_ram();
}
post_cache_as_ram();
}
-
diff --git
a/src/mainboard/tyan/s2882/romstage.c
b/src/mainboard/tyan/s2882/romstage.c
index cfcc7a9ae5b7cb62eb45ade4f26cfd44bdeef7d9..9ecf09bd3e3e17fc0f8ee2deba2e2e34a47b2bf8 100644
(file)
--- a/
src/mainboard/tyan/s2882/romstage.c
+++ b/
src/mainboard/tyan/s2882/romstage.c
@@
-29,28
+29,23
@@
static void memreset_setup(void)
{
static void memreset_setup(void)
{
- if (is_cpu_pre_c0()) {
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0
- }
- else {
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1
- }
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
+ if (is_cpu_pre_c0())
+ outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0
+ else
+ outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1
+ outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
}
static void memreset(int controllers, const struct mem_controller *ctrl)
{
if (is_cpu_pre_c0()) {
udelay(800);
}
static void memreset(int controllers, const struct mem_controller *ctrl)
{
if (is_cpu_pre_c0()) {
udelay(800);
- outb((
0<<7)|(0<<6)|(0<<5)|(0<<4)|(
1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
+ outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
udelay(90);
}
}
udelay(90);
}
}
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
- /* nothing to do */
-}
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address)
{
static inline int spd_read_byte(unsigned device, unsigned address)
{
@@
-97,15
+92,12
@@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
-
enumerate_ht_chain();
enumerate_ht_chain();
-
amd8111_enable_rom();
}
amd8111_enable_rom();
}
- if (bist == 0)
{
+ if (bist == 0)
init_cpus(cpu_init_detectedx);
init_cpus(cpu_init_detectedx);
- }
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
diff --git
a/src/mainboard/tyan/s2885/romstage.c
b/src/mainboard/tyan/s2885/romstage.c
index 012b915db7a3998d6a5b3b3e19018aefb1224eb2..3ebe6b5698e61f82a76f5fd086e2ab2b996f8f3d 100644
(file)
--- a/
src/mainboard/tyan/s2885/romstage.c
+++ b/
src/mainboard/tyan/s2885/romstage.c
@@
-28,28
+28,23
@@
static void memreset_setup(void)
{
static void memreset_setup(void)
{
- if (is_cpu_pre_c0()) {
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0
- }
- else {
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1
- }
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
+ if (is_cpu_pre_c0())
+ outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0
+ else
+ outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1
+ outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
}
static void memreset(int controllers, const struct mem_controller *ctrl)
{
if (is_cpu_pre_c0()) {
udelay(800);
}
static void memreset(int controllers, const struct mem_controller *ctrl)
{
if (is_cpu_pre_c0()) {
udelay(800);
- outb((
0<<7)|(0<<6)|(0<<5)|(0<<4)|(
1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
+ outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
udelay(90);
}
}
udelay(90);
}
}
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
- /* nothing to do */
-}
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address)
{
static inline int spd_read_byte(unsigned device, unsigned address)
{
@@
-59,7
+54,7
@@
static inline int spd_read_byte(unsigned device, unsigned address)
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "lib/generic_sdram.c"
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "lib/generic_sdram.c"
-#include "resourcemap.c"
/* tyan does not want the default */
+#include "resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c"
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/model_fxx/init_cpus.c"
#include "cpu/amd/dualcore/dualcore.c"
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/model_fxx/init_cpus.c"
@@
-78,26
+73,18
@@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
};
int needs_reset;
};
int needs_reset;
- unsigned bsp_apicid = 0;
-
+ unsigned bsp_apicid = 0, nodes;
struct mem_controller ctrl[8];
struct mem_controller ctrl[8];
- unsigned nodes;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
-
enumerate_ht_chain();
enumerate_ht_chain();
-
- /* Setup the amd8111 */
amd8111_enable_rom();
}
amd8111_enable_rom();
}
- if (bist == 0)
{
+ if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx);
bsp_apicid = init_cpus(cpu_init_detectedx);
- }
-
-// post_code(0x32);
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
diff --git
a/src/mainboard/tyan/s2891/romstage.c
b/src/mainboard/tyan/s2891/romstage.c
index 75405753e9bd21870faa1b980d2e1a6d21012a85..39bdc65e7e9f905d0d04a55c2d0099199ed69f1c 100644
(file)
--- a/
src/mainboard/tyan/s2891/romstage.c
+++ b/
src/mainboard/tyan/s2891/romstage.c
@@
-25,18
+25,9
@@
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-static void memreset_setup(void)
-{
-}
-
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-}
-
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
- /* nothing to do */
-}
+static void memreset_setup(void) { }
+static void memreset(int controllers, const struct mem_controller *ctrl) { }
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address)
{
static inline int spd_read_byte(unsigned device, unsigned address)
{
@@
-46,7
+37,7
@@
static inline int spd_read_byte(unsigned device, unsigned address)
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "lib/generic_sdram.c"
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "lib/generic_sdram.c"
-#include "resourcemap.c"
/* tyan does not want the default */
+#include "resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c"
#include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
#include "southbridge/nvidia/ck804/ck804_early_setup.c"
#include "cpu/amd/dualcore/dualcore.c"
#include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
#include "southbridge/nvidia/ck804/ck804_early_setup.c"
@@
-92,23
+83,18
@@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
};
int needs_reset;
};
int needs_reset;
- unsigned bsp_apicid = 0;
-
+ unsigned bsp_apicid = 0, nodes;
struct mem_controller ctrl[8];
struct mem_controller ctrl[8];
- unsigned nodes;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
-
enumerate_ht_chain();
enumerate_ht_chain();
-
sio_setup();
}
sio_setup();
}
- if (bist == 0)
{
+ if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx);
bsp_apicid = init_cpus(cpu_init_detectedx);
- }
// post_code(0x32);
// post_code(0x32);
@@
-135,9
+121,7
@@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
#endif
needs_reset |= ht_setup_chains_x();
#endif
needs_reset |= ht_setup_chains_x();
-
needs_reset |= ck804_early_setup_x();
needs_reset |= ck804_early_setup_x();
-
if (needs_reset) {
printk(BIOS_INFO, "ht reset -\n");
soft_reset();
if (needs_reset) {
printk(BIOS_INFO, "ht reset -\n");
soft_reset();
@@
-152,8
+136,6
@@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
enable_smbus();
#if 0
dump_spd_registers(&cpu[0]);
enable_smbus();
#if 0
dump_spd_registers(&cpu[0]);
-#endif
-#if 0
dump_smbus_registers();
#endif
dump_smbus_registers();
#endif
@@
-162,12
+144,8
@@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
#if 0
print_pci_devices();
#if 0
print_pci_devices();
-#endif
-
-#if 0
dump_pci_devices();
#endif
post_cache_as_ram();
}
dump_pci_devices();
#endif
post_cache_as_ram();
}
-
diff --git
a/src/mainboard/tyan/s2892/romstage.c
b/src/mainboard/tyan/s2892/romstage.c
index 180609c72e77e1f4ea3d93443b8c01126650988a..2ab6d32090a3b2b1ca0a21fad1e1a34f4a7acd1a 100644
(file)
--- a/
src/mainboard/tyan/s2892/romstage.c
+++ b/
src/mainboard/tyan/s2892/romstage.c
@@
-25,14
+25,8
@@
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-}
-
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
- /* nothing to do */
-}
+static void memreset(int controllers, const struct mem_controller *ctrl) { }
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address)
{
static inline int spd_read_byte(unsigned device, unsigned address)
{
@@
-42,7
+36,7
@@
static inline int spd_read_byte(unsigned device, unsigned address)
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "lib/generic_sdram.c"
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "lib/generic_sdram.c"
-#include "resourcemap.c"
/* tyan does not want the default */
+#include "resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c"
#include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
#include "cpu/amd/dualcore/dualcore.c"
#include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
@@
-84,23
+78,18
@@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
};
int needs_reset;
};
int needs_reset;
- unsigned bsp_apicid = 0;
-
+ unsigned bsp_apicid = 0, nodes;
struct mem_controller ctrl[8];
struct mem_controller ctrl[8];
- unsigned nodes;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
-
enumerate_ht_chain();
enumerate_ht_chain();
-
sio_setup();
}
sio_setup();
}
- if (bist == 0)
{
+ if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx);
bsp_apicid = init_cpus(cpu_init_detectedx);
- }
// post_code(0x32);
// post_code(0x32);
@@
-123,9
+112,7
@@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
#endif
needs_reset |= ht_setup_chains_x();
#endif
needs_reset |= ht_setup_chains_x();
-
needs_reset |= ck804_early_setup_x();
needs_reset |= ck804_early_setup_x();
-
if (needs_reset) {
printk(BIOS_INFO, "ht reset -\n");
soft_reset();
if (needs_reset) {
printk(BIOS_INFO, "ht reset -\n");
soft_reset();
@@
-143,4
+130,3
@@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_cache_as_ram();
}
post_cache_as_ram();
}
-
diff --git
a/src/mainboard/tyan/s2895/romstage.c
b/src/mainboard/tyan/s2895/romstage.c
index 84907ccc430680526fa653ac1bf25d89ca4e9371..7a6fcbc3a79a688ac626eaf8229630631fdcf139 100644
(file)
--- a/
src/mainboard/tyan/s2895/romstage.c
+++ b/
src/mainboard/tyan/s2895/romstage.c
@@
-19,38
+19,31
@@
#include "northbridge/amd/amdk8/reset_test.c"
#include "superio/smsc/lpc47b397/lpc47b397_early_serial.c"
#include "superio/smsc/lpc47b397/lpc47b397_early_gpio.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "superio/smsc/lpc47b397/lpc47b397_early_serial.c"
#include "superio/smsc/lpc47b397/lpc47b397_early_gpio.c"
-#define SUPERIO_GPIO_DEV PNP_DEV(0x2e, LPC47B397_RT)
-#define SUPERIO_GPIO_IO_BASE 0x400
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/debug.c"
#include <cpu/amd/mtrr.h>
#include "cpu/x86/mtrr/earlymtrr.c"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/debug.c"
#include <cpu/amd/mtrr.h>
#include "cpu/x86/mtrr/earlymtrr.c"
#include "northbridge/amd/amdk8/setup_resource_map.c"
-#define SERIAL_DEV PNP_DEV(0x2e, LPC47B397_SP1)
-
static void memreset_setup(void
)
-{
-}
+
#define SERIAL_DEV PNP_DEV(0x2e, LPC47B397_SP1
)
+#define SUPERIO_GPIO_DEV PNP_DEV(0x2e, LPC47B397_RT)
+#define SUPERIO_GPIO_IO_BASE 0x400
-static void memreset
(int controllers, const struct mem_controller *ctrl)
-{
-}
+static void memreset
_setup(void) { }
+static void memreset(int controllers, const struct mem_controller *ctrl) { }
+
static void activate_spd_rom(const struct mem_controller *ctrl) {
}
static void sio_gpio_setup(void)
{
unsigned value;
/*Enable onboard scsi*/
static void sio_gpio_setup(void)
{
unsigned value;
/*Enable onboard scsi*/
- lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x2c, (1<<7)|(0<<2)|(0<<1)|(0<<0)); // GP21, offset 0x2c, DISABLE_SCSI_L
+ lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x2c,
+ (1<<7)|(0<<2)|(0<<1)|(0<<0)); // GP21, offset 0x2c, DISABLE_SCSI_L
value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x4c);
lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x4c, (value|(1<<1)));
}
value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x4c);
lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x4c, (value|(1<<1)));
}
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
- /* nothing to do */
-}
-
static inline int spd_read_byte(unsigned device, unsigned address)
{
return smbus_read_byte(device, address);
static inline int spd_read_byte(unsigned device, unsigned address)
{
return smbus_read_byte(device, address);
@@
-59,7
+52,7
@@
static inline int spd_read_byte(unsigned device, unsigned address)
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "lib/generic_sdram.c"
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "lib/generic_sdram.c"
-#include "resourcemap.c"
/* tyan does not want the default */
+#include "resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c"
#include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
#include "cpu/amd/dualcore/dualcore.c"
#include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
@@
-113,23
+106,18
@@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
};
int needs_reset;
};
int needs_reset;
- unsigned bsp_apicid = 0;
-
+ unsigned bsp_apicid = 0, nodes;
struct mem_controller ctrl[8];
struct mem_controller ctrl[8];
- unsigned nodes;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
-
enumerate_ht_chain();
enumerate_ht_chain();
-
sio_setup();
}
sio_setup();
}
- if (bist == 0)
{
+ if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx);
bsp_apicid = init_cpus(cpu_init_detectedx);
- }
lpc47b397_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
lpc47b397_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
@@
-151,9
+139,7
@@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
wait_all_other_cores_started(bsp_apicid);
needs_reset |= ht_setup_chains_x();
wait_all_other_cores_started(bsp_apicid);
needs_reset |= ht_setup_chains_x();
-
needs_reset |= ck804_early_setup_x();
needs_reset |= ck804_early_setup_x();
-
if (needs_reset) {
printk(BIOS_INFO, "ht reset -\n");
soft_reset();
if (needs_reset) {
printk(BIOS_INFO, "ht reset -\n");
soft_reset();
@@
-172,4
+158,3
@@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_cache_as_ram();
}
post_cache_as_ram();
}
-
diff --git
a/src/mainboard/tyan/s2912/romstage.c
b/src/mainboard/tyan/s2912/romstage.c
index 8a3c5c3a7922661b29c227b8d1e73c4d08640859..ab0b4220b122daa129a08a192bbd9e6973994076 100644
(file)
--- a/
src/mainboard/tyan/s2912/romstage.c
+++ b/
src/mainboard/tyan/s2912/romstage.c
@@
-53,14
+53,8
@@
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-}
-
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
- /* nothing to do */
-}
+static void memreset(int controllers, const struct mem_controller *ctrl) { }
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address)
{
static inline int spd_read_byte(unsigned device, unsigned address)
{
@@
-113,40
+107,32
@@
static void sio_setup(void)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr [] = {
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr [] = {
-
// Node 0
-
DIMM0, DIMM2, 0, 0,
-
DIMM1, DIMM3, 0, 0,
-
// Node 1
-
DIMM4, DIMM6, 0, 0,
-
DIMM5, DIMM7, 0, 0,
+ // Node 0
+ DIMM0, DIMM2, 0, 0,
+ DIMM1, DIMM3, 0, 0,
+ // Node 1
+ DIMM4, DIMM6, 0, 0,
+ DIMM5, DIMM7, 0, 0,
};
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
+ CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
};
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
+ CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
-
int needs_reset = 0;
unsigned bsp_apicid = 0;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
int needs_reset = 0;
unsigned bsp_apicid = 0;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
-
enumerate_ht_chain();
enumerate_ht_chain();
-
sio_setup();
sio_setup();
-
- /* Setup the mcp55 */
mcp55_enable_rom();
}
mcp55_enable_rom();
}
- if (bist == 0)
{
+ if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
- }
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-
setup_mb_resource_map();
setup_mb_resource_map();
-
uart_init();
/* Halt if there was a built in self test failure */
uart_init();
/* Halt if there was a built in self test failure */
@@
-181,26
+167,19
@@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
#if CONFIG_SET_FIDVID
ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
#if CONFIG_SET_FIDVID
-
{
msr_t msr;
msr=rdmsr(0xc0010042);
print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
{
msr_t msr;
msr=rdmsr(0xc0010042);
print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
-
}
}
-
enable_fid_change();
enable_fid_change();
-
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
-
init_fidvid_bsp(bsp_apicid);
init_fidvid_bsp(bsp_apicid);
-
// show final fid and vid
{
msr_t msr;
msr=rdmsr(0xc0010042);
print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
// show final fid and vid
{
msr_t msr;
msr=rdmsr(0xc0010042);
print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
-
}
#endif
}
#endif
diff --git
a/src/mainboard/tyan/s2912_fam10/romstage.c
b/src/mainboard/tyan/s2912_fam10/romstage.c
index 6f420bfe6314b1ad917f7b30940ed62e441d9a3b..550e86607a8f2dd2e7029160920c860ffbd15f3f 100644
(file)
--- a/
src/mainboard/tyan/s2912_fam10/romstage.c
+++ b/
src/mainboard/tyan/s2912_fam10/romstage.c
@@
-52,10
+52,7
@@
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
- /* nothing to do */
-}
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address)
{
static inline int spd_read_byte(unsigned device, unsigned address)
{
@@
-117,29
+114,22
@@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
{
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
- u32 bsp_apicid = 0;
- u32 val;
- u32 wants_reset;
+ u32 bsp_apicid = 0, val, wants_reset;
msr_t msr;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
msr_t msr;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
-
set_bsp_node_CHtExtNodeCfgEn();
enumerate_ht_chain();
set_bsp_node_CHtExtNodeCfgEn();
enumerate_ht_chain();
-
sio_setup();
sio_setup();
-
- /* Setup the mcp55 */
mcp55_enable_rom();
}
post_code(0x30);
mcp55_enable_rom();
}
post_code(0x30);
- if (bist == 0)
{
+ if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
- }
post_code(0x32);
post_code(0x32);
@@
-256,4
+246,3
@@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
post_code(0x43); // Should never see this post code.
}
post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
post_code(0x43); // Should never see this post code.
}
-
diff --git
a/src/mainboard/tyan/s4880/romstage.c
b/src/mainboard/tyan/s4880/romstage.c
index 09a052fc3ca3b69865d47a27d91b56aba137ac72..b542bfdbe54fa01206ecd11de4c9c22494400a11 100644
(file)
--- a/
src/mainboard/tyan/s4880/romstage.c
+++ b/
src/mainboard/tyan/s4880/romstage.c
@@
-28,23
+28,22
@@
static void memreset_setup(void)
{
static void memreset_setup(void)
{
- if (is_cpu_pre_c0()) {
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0
- }
- else {
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1
- }
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
+ if (is_cpu_pre_c0())
+ outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0
+ else
+ outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1
+ outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
}
static void memreset(int controllers, const struct mem_controller *ctrl)
{
if (is_cpu_pre_c0()) {
udelay(800);
}
static void memreset(int controllers, const struct mem_controller *ctrl)
{
if (is_cpu_pre_c0()) {
udelay(800);
- outb((
0<<7)|(0<<6)|(0<<5)|(0<<4)|(
1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
+ outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
udelay(90);
}
}
udelay(90);
}
}
+
static inline void activate_spd_rom(const struct mem_controller *ctrl)
{
#define SMBUS_HUB 0x18
static inline void activate_spd_rom(const struct mem_controller *ctrl)
{
#define SMBUS_HUB 0x18
@@
-52,6
+51,7
@@
static inline void activate_spd_rom(const struct mem_controller *ctrl)
smbus_write_byte(SMBUS_HUB, 0x01, device);
smbus_write_byte(SMBUS_HUB, 0x03, 0);
}
smbus_write_byte(SMBUS_HUB, 0x01, device);
smbus_write_byte(SMBUS_HUB, 0x03, 0);
}
+
#if 0
static inline void change_i2c_mux(unsigned device)
{
#if 0
static inline void change_i2c_mux(unsigned device)
{
@@
-73,7
+73,7
@@
static inline int spd_read_byte(unsigned device, unsigned address)
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "lib/generic_sdram.c"
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "lib/generic_sdram.c"
-#include "resourcemap.c"
/* tyan does not want the default */
+#include "resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c"
#include <spd.h>
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/dualcore/dualcore.c"
#include <spd.h>
#include "cpu/amd/car/post_cache_as_ram.c"
@@
-110,7
+110,6
@@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
},
#endif
},
#endif
-
#if CONFIG_MAX_PHYSICAL_CPUS > 2
{
.node_id = 2,
#if CONFIG_MAX_PHYSICAL_CPUS > 2
{
.node_id = 2,
@@
-140,15
+139,12
@@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
-
enumerate_ht_chain();
enumerate_ht_chain();
-
amd8111_enable_rom();
}
amd8111_enable_rom();
}
- if (bist == 0)
{
+ if (bist == 0)
init_cpus(cpu_init_detectedx);
init_cpus(cpu_init_detectedx);
- }
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
diff --git
a/src/mainboard/tyan/s4882/romstage.c
b/src/mainboard/tyan/s4882/romstage.c
index 152996fee4b8c3c7b938f59baec2ae595d41c8c6..7750750ca19ed5b7fdd519ca72fc0e8c36a57eb4 100644
(file)
--- a/
src/mainboard/tyan/s4882/romstage.c
+++ b/
src/mainboard/tyan/s4882/romstage.c
@@
-27,23
+27,22
@@
static void memreset_setup(void)
{
static void memreset_setup(void)
{
- if (is_cpu_pre_c0()) {
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0
- }
- else {
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1
- }
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
+ if (is_cpu_pre_c0())
+ outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0
+ else
+ outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1
+ outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
}
static void memreset(int controllers, const struct mem_controller *ctrl)
{
if (is_cpu_pre_c0()) {
udelay(800);
}
static void memreset(int controllers, const struct mem_controller *ctrl)
{
if (is_cpu_pre_c0()) {
udelay(800);
- outb((
0<<7)|(0<<6)|(0<<5)|(0<<4)|(
1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
+ outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
udelay(90);
}
}
udelay(90);
}
}
+
static inline void activate_spd_rom(const struct mem_controller *ctrl)
{
#define SMBUS_HUB 0x18
static inline void activate_spd_rom(const struct mem_controller *ctrl)
{
#define SMBUS_HUB 0x18
@@
-57,6
+56,7
@@
static inline void activate_spd_rom(const struct mem_controller *ctrl)
smbus_write_byte(SMBUS_HUB, 0x03, 0);
}
smbus_write_byte(SMBUS_HUB, 0x03, 0);
}
+
#if 0
static inline void change_i2c_mux(unsigned device)
{
#if 0
static inline void change_i2c_mux(unsigned device)
{
@@
-81,7
+81,7
@@
static inline int spd_read_byte(unsigned device, unsigned address)
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "lib/generic_sdram.c"
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "lib/generic_sdram.c"
-#include "resourcemap.c"
/* tyan does not want the default */
+#include "resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c"
#include <spd.h>
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/dualcore/dualcore.c"
#include <spd.h>
#include "cpu/amd/car/post_cache_as_ram.c"
@@
-112,24
+112,18
@@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
};
int needs_reset;
};
int needs_reset;
- unsigned bsp_apicid = 0;
-
+ unsigned bsp_apicid = 0, nodes;
struct mem_controller ctrl[8];
struct mem_controller ctrl[8];
- unsigned nodes;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
-
enumerate_ht_chain();
enumerate_ht_chain();
-
amd8111_enable_rom();
}
amd8111_enable_rom();
}
- if (bist == 0)
{
+ if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx);
bsp_apicid = init_cpus(cpu_init_detectedx);
- }
-
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
@@
-169,6
+163,4
@@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
sdram_initialize(nodes, ctrl);
post_cache_as_ram();
sdram_initialize(nodes, ctrl);
post_cache_as_ram();
-
}
}
-
diff --git
a/src/mainboard/via/epia-cn/romstage.c
b/src/mainboard/via/epia-cn/romstage.c
index 2292b0a5ae28e0e8740eff5871c6934861abba63..1d37ced6d98ab560486e42f5a75f59aaa1efd216 100644
(file)
--- a/
src/mainboard/via/epia-cn/romstage.c
+++ b/
src/mainboard/via/epia-cn/romstage.c
@@
-47,7
+47,8
@@
static void enable_mainboard_devices(void)
{
device_t dev;
{
device_t dev;
- dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
+ dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
+ PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
if (dev == PCI_DEV_INVALID)
die("Southbridge not found!!!\n");
if (dev == PCI_DEV_INVALID)
die("Southbridge not found!!!\n");
@@
-87,21
+88,10
@@
void main(unsigned long bist)
enable_vt8235_serial();
uart_init();
console_init();
enable_vt8235_serial();
uart_init();
console_init();
-
- print_spew("In romstage.c:main()\n");
-
enable_smbus();
smbus_fixup(&ctrl);
enable_smbus();
smbus_fixup(&ctrl);
-
- /* Halt if there was a built-in self test failure. */
report_bist_failure(bist);
report_bist_failure(bist);
-
- print_debug("Enabling mainboard devices\n");
enable_mainboard_devices();
enable_mainboard_devices();
-
ddr_ram_setup(&ctrl);
ddr_ram_setup(&ctrl);
-
/* ram_check(0, 640 * 1024); */
/* ram_check(0, 640 * 1024); */
-
- print_spew("Leaving romstage.c:main()\n");
}
}
diff --git
a/src/mainboard/via/epia-m/romstage.c
b/src/mainboard/via/epia-m/romstage.c
index 7dba82c85299d2f7e99366b979f7c8f2e321e44e..508d298604b23b80fdac427b9c3870d5882c80f1 100644
(file)
--- a/
src/mainboard/via/epia-m/romstage.c
+++ b/
src/mainboard/via/epia-m/romstage.c
@@
-30,7
+30,7
@@
static void enable_mainboard_devices(void)
device_t dev;
dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA,
device_t dev;
dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA,
- PCI_DEVICE_ID_VIA_8235), 0);
+
PCI_DEVICE_ID_VIA_8235), 0);
if (dev == PCI_DEV_INVALID) {
die("Southbridge not found!!!\n");
if (dev == PCI_DEV_INVALID) {
die("Southbridge not found!!!\n");
@@
-72,9
+72,7
@@
static void main(unsigned long bist)
{
device_t dev;
{
device_t dev;
- /*
- * Enable VGA; 32MB buffer.
- */
+ /* Enable VGA; 32MB buffer. */
pci_write_config8(0, 0xe1, 0xdd);
/*
pci_write_config8(0, 0xe1, 0xdd);
/*
@@
-83,9
+81,8
@@
static void main(unsigned long bist)
*/
dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_6305), 0);
*/
dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_6305), 0);
- if (dev != PCI_DEV_INVALID)
{
+ if (dev != PCI_DEV_INVALID)
pci_write_config8(dev, 0x15, 0x1c);
pci_write_config8(dev, 0x15, 0x1c);
- }
enable_vt8235_serial();
uart_init();
enable_vt8235_serial();
uart_init();
@@
-122,12
+119,8
@@
static void main(unsigned long bist)
}
#endif
}
#endif
- if (bist == 0) {
- print_debug(" Doing MTRR init.\n");
+ if (bist == 0)
early_mtrr_init();
early_mtrr_init();
- }
//dump_pci_devices();
//dump_pci_devices();
-
- print_spew("Leaving romstage.c:main()\n");
}
}
diff --git
a/src/mainboard/via/epia-m700/romstage.c
b/src/mainboard/via/epia-m700/romstage.c
index 62ea809b477e687c74bf0969ca5ec9192dbf0d1f..6d0957049becd8b3fb3cb63f30f409683b9ba43d 100644
(file)
--- a/
src/mainboard/via/epia-m700/romstage.c
+++ b/
src/mainboard/via/epia-m700/romstage.c
@@
-448,17
+448,6
@@
void main(unsigned long bist)
/* This fix does help vx800!, but vx855 doesn't need this. */
/* smbus_fixup(&ctrl); */
/* This fix does help vx800!, but vx855 doesn't need this. */
/* smbus_fixup(&ctrl); */
- if (bist == 0) {
- /*
- * CAR needs MTRR until memory is ok, so disable this
- * early_mtrr_init() call.
- */
-#if 0
- print_debug("doing early_mtrr\n");
- early_mtrr_init();
-#endif
- }
-
/* Halt if there was a built-in self test failure. */
report_bist_failure(bist);
/* Halt if there was a built-in self test failure. */
report_bist_failure(bist);
diff --git
a/src/mainboard/via/epia-n/romstage.c
b/src/mainboard/via/epia-n/romstage.c
index 449fe95ff1b793b5089d8f0d095dfbb86b60748f..90d92383ad6fde4349b4e036c8bcb291d2218e2a 100644
(file)
--- a/
src/mainboard/via/epia-n/romstage.c
+++ b/
src/mainboard/via/epia-n/romstage.c
@@
-62,7
+62,8
@@
static void enable_mainboard_devices(void)
device_t dev;
u8 reg;
device_t dev;
u8 reg;
- dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
+ dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
+ PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
if (dev == PCI_DEV_INVALID)
die("Southbridge not found!!!\n");
if (dev == PCI_DEV_INVALID)
die("Southbridge not found!!!\n");
@@
-110,14
+111,10
@@
static void main(unsigned long bist)
pci_write_config8(ctrl.d0f0, 0x4f, 0x01);
w83697hf_set_clksel_48(SERIAL_DEV);
pci_write_config8(ctrl.d0f0, 0x4f, 0x01);
w83697hf_set_clksel_48(SERIAL_DEV);
-
w83697hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
w83697hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-
uart_init();
console_init();
uart_init();
console_init();
- print_spew("In romstage.c:main()\n");
-
enable_smbus();
smbus_fixup(&ctrl);
enable_smbus();
smbus_fixup(&ctrl);
@@
-130,18
+127,13
@@
static void main(unsigned long bist)
print_debug("Enable F-ROM Shadow RAM\n");
enable_shadow_ram();
print_debug("Enable F-ROM Shadow RAM\n");
enable_shadow_ram();
- /* setup cpu */
print_debug("Setup CPU Interface\n");
c3_cpu_setup(ctrl.d0f2);
ddr_ram_setup();
print_debug("Setup CPU Interface\n");
c3_cpu_setup(ctrl.d0f2);
ddr_ram_setup();
- if (bist == 0) {
- print_debug("doing early_mtrr\n");
+ if (bist == 0)
early_mtrr_init();
early_mtrr_init();
- }
//ram_check(0, 640 * 1024);
//ram_check(0, 640 * 1024);
-
- print_spew("Leaving romstage.c:main()\n");
}
}
diff --git
a/src/mainboard/via/epia/romstage.c
b/src/mainboard/via/epia/romstage.c
index 24167baebed38c482edb9ac9e7446d29d380108c..2bae6c4c81fe707a220063fc90c188bf6e9505fe 100644
(file)
--- a/
src/mainboard/via/epia/romstage.c
+++ b/
src/mainboard/via/epia/romstage.c
@@
-31,9
+31,8
@@
static void enable_mainboard_devices(void)
dev = pci_locate_device(PCI_ID(0x1106,0x8231), 0);
dev = pci_locate_device(PCI_ID(0x1106,0x8231), 0);
- if (dev == PCI_DEV_INVALID)
{
+ if (dev == PCI_DEV_INVALID)
die("Southbridge not found!!!\n");
die("Southbridge not found!!!\n");
- }
pci_write_config8(dev, 0x50, 7);
pci_write_config8(dev, 0x51, 0xff);
pci_write_config8(dev, 0x50, 7);
pci_write_config8(dev, 0x51, 0xff);
@@
-74,9
+73,9
@@
static void enable_shadow_ram(void)
static void main(unsigned long bist)
{
static void main(unsigned long bist)
{
- if (bist == 0)
{
+ if (bist == 0)
early_mtrr_init();
early_mtrr_init();
- }
+
enable_vt8231_serial();
uart_init();
console_init();
enable_vt8231_serial();
uart_init();
console_init();
diff --git
a/src/mainboard/via/pc2500e/romstage.c
b/src/mainboard/via/pc2500e/romstage.c
index 3aa599bb49008a4ec44174b08570caf9a91ecabb..657b3cde6b4a9721f2680eced7e15ec51584080e 100644
(file)
--- a/
src/mainboard/via/pc2500e/romstage.c
+++ b/
src/mainboard/via/pc2500e/romstage.c
@@
-63,14
+63,9
@@
void main(unsigned long bist)
it8716f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
console_init();
it8716f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
console_init();
-
enable_smbus();
smbus_fixup(&ctrl);
enable_smbus();
smbus_fixup(&ctrl);
-
- /* Halt if there was a built-in self test failure. */
report_bist_failure(bist);
report_bist_failure(bist);
-
ddr_ram_setup(&ctrl);
ddr_ram_setup(&ctrl);
-
/* ram_check(0, 640 * 1024); */
}
/* ram_check(0, 640 * 1024); */
}
diff --git
a/src/mainboard/winent/pl6064/romstage.c
b/src/mainboard/winent/pl6064/romstage.c
index 0ba37f173ad5dbc13ddea4b73a62fbcca0eb12fb..becd698c0a83ef6adf74941568ceac8beba57823 100644
(file)
--- a/
src/mainboard/winent/pl6064/romstage.c
+++ b/
src/mainboard/winent/pl6064/romstage.c
@@
-56,11
+56,6
@@
static inline int spd_read_byte(unsigned int device, unsigned int address)
#include "cpu/amd/model_lx/syspreinit.c"
#include "cpu/amd/model_lx/msrinit.c"
#include "cpu/amd/model_lx/syspreinit.c"
#include "cpu/amd/model_lx/msrinit.c"
-static void mb_gpio_init(void)
-{
- /* Early mainboard specific GPIO setup. */
-}
-
void main(unsigned long bist)
{
post_code(0x01);
void main(unsigned long bist)
{
post_code(0x01);
@@
-79,7
+74,6
@@
void main(unsigned long bist)
*/
w83627hf_set_clksel_48(SERIAL_DEV);
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
*/
w83627hf_set_clksel_48(SERIAL_DEV);
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
- mb_gpio_init();
uart_init();
console_init();
uart_init();
console_init();
diff --git
a/src/mainboard/wyse/s50/romstage.c
b/src/mainboard/wyse/s50/romstage.c
index ba59d562c0f66cc345da622bc1bd2d451735d198..b1ece302febe3c99954bb399edece3b039d120d2 100644
(file)
--- a/
src/mainboard/wyse/s50/romstage.c
+++ b/
src/mainboard/wyse/s50/romstage.c
@@
-81,5
+81,4
@@
void main(unsigned long bist)
/* Check all of memory */
/*ram_check(0x00000000, 640*1024);*/
/* Check all of memory */
/*ram_check(0x00000000, 640*1024);*/
- print_err("ram check done\n");
}
}
diff --git
a/src/northbridge/via/vx800/examples/romstage.c
b/src/northbridge/via/vx800/examples/romstage.c
index f0e535a02c9a9c6d620fe91e02e50453396a7e84..6fbc4ebad4c2560488b2974652434d4af7ddd794 100644
(file)
--- a/
src/northbridge/via/vx800/examples/romstage.c
+++ b/
src/northbridge/via/vx800/examples/romstage.c
@@
-81,9
+81,7
@@
static void enable_mainboard_devices(void)
print_debug("In enable_mainboard_devices \n");
print_debug("In enable_mainboard_devices \n");
- /*
- Enable P2P Bridge Header for External PCI BUS.
- */
+ /* Enable P2P bridge Header for external PCI bus. */
dev = pci_locate_device(PCI_ID(0x1106, 0xa353), 0);
pci_write_config8(dev, 0x4f, 0x41);
}
dev = pci_locate_device(PCI_ID(0x1106, 0xa353), 0);
pci_write_config8(dev, 0x4f, 0x41);
}
@@
-91,6
+89,7
@@
static void enable_mainboard_devices(void)
static void enable_shadow_ram(void)
{
uint8_t shadowreg;
static void enable_shadow_ram(void)
{
uint8_t shadowreg;
+
pci_write_config8(PCI_DEV(0, 0, 3), 0x80, 0xff);
/* 0xf0000-0xfffff - ACPI tables */
shadowreg = pci_read_config8(PCI_DEV(0, 0, 3), 0x83);
pci_write_config8(PCI_DEV(0, 0, 3), 0x80, 0xff);
/* 0xf0000-0xfffff - ACPI tables */
shadowreg = pci_read_config8(PCI_DEV(0, 0, 3), 0x83);