src/mainboard/asus/m2v-mx_se/romstage.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2006 AMD
   5  * (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
   6  * Copyright (C) 2006 MSI
   7  * (Written by Bingxun Shi <bingxunshi@gmail.com> for MSI)
   8  * Copyright (C) 2008 Rudolf Marek <r.marek@assembler.cz>
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  23  */
  24
  25 unsigned int get_sbdn(unsigned bus);
  26
  27 #if CONFIG_K8_REV_F_SUPPORT == 1
  28 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
  29 #endif
  30
  31 #include <stdint.h>
  32 #include <string.h>
  33 #include <device/pci_def.h>
  34 #include <arch/io.h>
  35 #include <device/pnp_def.h>
  36 #include <arch/romcc_io.h>
  37 #include <cpu/amd/mtrr.h>
  38 #include <cpu/x86/lapic.h>
  39 #include <pc80/mc146818rtc.h>
  40 #include <console/console.h>
  41 #include <cpu/amd/model_fxx_rev.h>
  42 #include "northbridge/amd/amdk8/raminit.h"
  43 #include "cpu/amd/model_fxx/apic_timer.c"
  44 #include "lib/delay.c"
  45 #include "northbridge/amd/amdk8/reset_test.c"
  46 #include "northbridge/amd/amdk8/debug.c"
  47 #include "superio/ite/it8712f/it8712f_early_serial.c"
  48 #include "southbridge/via/vt8237r/vt8237r_early_smbus.c"
  49 #include "cpu/x86/mtrr/earlymtrr.c"
  50 #include "cpu/x86/bist.h"
  51 #include "northbridge/amd/amdk8/setup_resource_map.c"
  52 #include <spd.h>
  53
  54 #define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
  55 #define WATCHDOG_DEV PNP_DEV(0x2e, IT8712F_GPIO)
  56
  57 static void memreset(int controllers, const struct mem_controller *ctrl) { }
  58 static void activate_spd_rom(const struct mem_controller *ctrl) { }
  59
  60 static inline int spd_read_byte(unsigned device, unsigned address)
  61 {
  62         return smbus_read_byte(device, address);
  63 }
  64
  65 // defines S3_NVRAM_EARLY:
  66 #include "southbridge/via/k8t890/k8t890_early_car.c"
  67 #include "northbridge/amd/amdk8/amdk8.h"
  68 #include "northbridge/amd/amdk8/incoherent_ht.c"
  69 #include "northbridge/amd/amdk8/coherent_ht.c"
  70 #include "northbridge/amd/amdk8/raminit_f.c"
  71 #include "lib/generic_sdram.c"
  72 #include "cpu/amd/dualcore/dualcore.c"
  73 #include "cpu/amd/car/post_cache_as_ram.c"
  74 #include "cpu/amd/model_fxx/init_cpus.c"
  75
  76 #define SB_VFSMAF 0
  77
  78 /* this function might fail on some K8 CPUs with errata #181 */
  79 static void ldtstop_sb(void)
  80 {
  81         print_debug("toggle LDTSTP#\n");
  82         u8 reg = inb (VT8237R_ACPI_IO_BASE + 0x5c);
  83         reg = reg ^ (1 << 0);
  84         outb(reg, VT8237R_ACPI_IO_BASE + 0x5c);
  85         reg = inb(VT8237R_ACPI_IO_BASE + 0x15);
  86         print_debug("done\n");
  87 }
  88
  89 #include "cpu/amd/model_fxx/fidvid.c"
  90 #include "northbridge/amd/amdk8/resourcemap.c"
  91
  92 void soft_reset(void)
  93 {
  94         uint8_t tmp;
  95
  96         set_bios_reset();
  97         print_debug("soft reset \n");
  98
  99         /* PCI reset */
 100         tmp = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x4f);
 101         tmp |= 0x01;
 102         /* FIXME from S3 set bit1 to disable USB reset VT8237A/S */
 103         pci_write_config8(PCI_DEV(0, 0x11, 0), 0x4f, tmp);
 104
 105         while (1) {
 106                 /* daisy daisy ... */
 107                 hlt();
 108         }
 109 }
 110
 111 unsigned int get_sbdn(unsigned bus)
 112 {
 113         device_t dev;
 114
 115         dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA,
 116                                         PCI_DEVICE_ID_VIA_VT8237R_LPC), bus);
 117         return (dev >> 15) & 0x1f;
 118 }
 119
 120 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 121 {
 122         static const uint16_t spd_addr[] = {
 123                 // Node 0
 124                 DIMM0, DIMM2, 0, 0,
 125                 DIMM1, DIMM3, 0, 0,
 126                 // Node 1
 127                 DIMM4, DIMM6, 0, 0,
 128                 DIMM5, DIMM7, 0, 0,
 129         };
 130         unsigned bsp_apicid = 0;
 131         int needs_reset = 0;
 132         struct sys_info *sysinfo =
 133             (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 134
 135         it8712f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 136         it8712f_kill_watchdog();
 137         it8712f_enable_3vsbsw();
 138         uart_init();
 139         console_init();
 140         enable_rom_decode();
 141
 142         printk(BIOS_INFO, "now booting... \n");
 143
 144         if (bist == 0)
 145                 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 146
 147         /* Halt if there was a built in self test failure. */
 148         report_bist_failure(bist);
 149         setup_default_resource_map();
 150         setup_coherent_ht_domain();
 151         wait_all_core0_started();
 152
 153         printk(BIOS_INFO, "now booting... All core 0 started\n");
 154
 155 #if CONFIG_LOGICAL_CPUS==1
 156         /* It is said that we should start core1 after all core0 launched. */
 157         start_other_cores();
 158         wait_all_other_cores_started(bsp_apicid);
 159 #endif
 160         init_timer();
 161         ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. */
 162
 163         needs_reset = optimize_link_coherent_ht();
 164         print_debug_hex8(needs_reset);
 165         needs_reset |= optimize_link_incoherent_ht(sysinfo);
 166         print_debug_hex8(needs_reset);
 167         needs_reset |= k8t890_early_setup_ht();
 168         print_debug_hex8(needs_reset);
 169
 170         vt8237_early_network_init(NULL);
 171         vt8237_early_spi_init();
 172
 173         if (needs_reset) {
 174                 printk(BIOS_DEBUG, "ht reset -\n");
 175                 soft_reset();
 176                 printk(BIOS_DEBUG, "FAILED!\n");
 177         }
 178
 179         /* the HT settings needs to be OK, because link freq chnage may cause HT disconnect */
 180         /* allow LDT STOP asserts */
 181         vt8237_sb_enable_fid_vid();
 182
 183         enable_fid_change();
 184         print_debug("after enable_fid_change\n");
 185
 186         init_fidvid_bsp(bsp_apicid);
 187
 188         /* Stop the APs so we can start them later in init. */
 189         allow_all_aps_stop(bsp_apicid);
 190
 191         /* It's the time to set ctrl now. */
 192         fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 193         enable_smbus();
 194         sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 195         post_cache_as_ram();
 196 }