2 * This file is part of the coreboot project.
4 * Copyright (C) 2007-2010 coresystems GmbH
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 // __PRE_RAM__ means: use "unsigned" for device, not a struct.
25 #include <arch/romcc_io.h>
26 #include <device/pci_def.h>
27 #include <device/pnp_def.h>
28 #include <cpu/x86/lapic.h>
30 #include "superio/winbond/w83627ehg/w83627ehg.h"
31 #include <pc80/mc146818rtc.h>
32 #include <console/console.h>
34 #include <cpu/x86/bist.h>
35 #include "superio/winbond/w83627ehg/w83627ehg_early_serial.c"
36 #include "northbridge/intel/i945/i945.h"
37 #include "northbridge/intel/i945/raminit.h"
38 #include "southbridge/intel/i82801gx/i82801gx.h"
40 #define SERIAL_DEV PNP_DEV(0x4e, W83627EHG_SP1)
42 void enable_smbus(void);
44 void setup_ich7_gpios(void)
46 printk(BIOS_DEBUG, " GPIOS...");
47 /* General Registers */
48 outl(0x1f1ff7c0, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */
49 outl(0xe0e8efc3, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */
50 outl(0xebffeeff, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */
51 /* Output Control Registers */
52 outl(0x00000000, DEFAULT_GPIOBASE + 0x18); /* GPO_BLINK */
53 /* Input Control Registers */
54 outl(0x00002180, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */
55 outl(0x000100ff, DEFAULT_GPIOBASE + 0x30); /* GPIO_USE_SEL2 */
56 outl(0x00000030, DEFAULT_GPIOBASE + 0x34); /* GP_IO_SEL2 */
57 outl(0x00010035, DEFAULT_GPIOBASE + 0x38); /* GP_LVL */
60 static void ich7_enable_lpc(void)
63 pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0);
64 // Set COM1/COM2 decode range
65 pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010);
66 // Enable COM1/COM2/KBD/SuperIO1+2
67 pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x340b);
68 // Enable HWM at 0x290
69 pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x00fc0291);
71 pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00000301);
74 /* This box has one superio
75 * Also set up the GPIOs from the beginning. This is the "no schematic
76 * but safe anyways" method.
78 static void early_superio_config_w83627ehg(void)
82 dev=PNP_DEV(0x4e, W83627EHG_SP1);
83 pnp_enter_ext_func_mode(dev);
85 pnp_write_config(dev, 0x24, 0xc4); // PNPCSV
87 pnp_write_config(dev, 0x29, 0x01); // GPIO settings
88 pnp_write_config(dev, 0x2a, 0x40); // GPIO settings should be fc but gets set to 02
89 pnp_write_config(dev, 0x2b, 0xc0); // GPIO settings?
90 pnp_write_config(dev, 0x2c, 0x03); // GPIO settings?
91 pnp_write_config(dev, 0x2d, 0x20); // GPIO settings?
93 dev=PNP_DEV(0x4e, W83627EHG_SP1);
94 pnp_set_logical_device(dev);
95 pnp_set_enable(dev, 0);
96 pnp_set_iobase(dev, PNP_IDX_IO0, 0x3f8);
97 pnp_set_irq(dev, PNP_IDX_IRQ0, 4);
98 pnp_set_enable(dev, 1);
100 dev=PNP_DEV(0x4e, W83627EHG_SP2);
101 pnp_set_logical_device(dev);
102 pnp_set_enable(dev, 0);
103 pnp_set_iobase(dev, PNP_IDX_IO0, 0x2f8);
104 pnp_set_irq(dev, PNP_IDX_IRQ0, 3);
105 // pnp_write_config(dev, 0xf1, 4); // IRMODE0
106 pnp_set_enable(dev, 1);
108 dev=PNP_DEV(0x4e, W83627EHG_KBC); // Keyboard
109 pnp_set_logical_device(dev);
110 pnp_set_enable(dev, 0);
111 pnp_set_iobase(dev, PNP_IDX_IO0, 0x60);
112 pnp_set_iobase(dev, PNP_IDX_IO1, 0x64);
113 //pnp_write_config(dev, 0xf0, 0x82);
114 pnp_set_enable(dev, 1);
116 dev=PNP_DEV(0x4e, W83627EHG_GPIO2);
117 pnp_set_logical_device(dev);
118 pnp_set_enable(dev, 1); // Just enable it
120 dev=PNP_DEV(0x4e, W83627EHG_GPIO3);
121 pnp_set_logical_device(dev);
122 pnp_set_enable(dev, 0);
123 pnp_write_config(dev, 0xf0, 0xfb); // GPIO bit 2 is output
124 pnp_write_config(dev, 0xf1, 0x00); // GPIO bit 2 is 0
125 pnp_write_config(dev, 0x30, 0x03); // Enable GPIO3+4. pnp_set_enable is not sufficient
127 dev=PNP_DEV(0x4e, W83627EHG_FDC);
128 pnp_set_logical_device(dev);
129 pnp_set_enable(dev, 0);
131 dev=PNP_DEV(0x4e, W83627EHG_PP);
132 pnp_set_logical_device(dev);
133 pnp_set_enable(dev, 0);
136 dev=PNP_DEV(0x4e, W83627EHG_HWM);
137 pnp_set_logical_device(dev);
138 pnp_set_enable(dev, 0);
139 pnp_set_iobase(dev, PNP_IDX_IO0, 0xa00);
140 pnp_set_enable(dev, 1);
142 pnp_exit_ext_func_mode(dev);
145 static void rcba_config(void)
147 /* Set up virtual channel 0 */
148 //RCBA32(0x0014) = 0x80000001;
149 //RCBA32(0x001c) = 0x03128010;
151 /* Device 1f interrupt pin register */
152 RCBA32(0x3100) = 0x00042210;
153 /* Device 1d interrupt pin register */
154 RCBA32(0x310c) = 0x00214321;
156 /* dev irq route register */
157 RCBA16(0x3140) = 0x0132;
158 RCBA16(0x3142) = 0x0146;
159 RCBA16(0x3144) = 0x0237;
160 RCBA16(0x3146) = 0x3201;
161 RCBA16(0x3148) = 0x0146;
164 RCBA8(0x31ff) = 0x03;
166 /* Enable upper 128bytes of CMOS */
167 RCBA32(0x3400) = (1 << 2);
169 /* Enable PCIe Root Port Clock Gate */
170 // RCBA32(0x341c) = 0x00000001;
173 static void early_ich7_init(void)
178 // program secondary mlt XXX byte?
179 pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20);
181 // reset rtc power status
182 reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4);
184 pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8);
186 // usb transient disconnect
187 reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad);
189 pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8);
191 reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc);
192 reg32 |= (1 << 29) | (1 << 17);
193 pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32);
195 reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc);
196 reg32 |= (1 << 31) | (1 << 27);
197 pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32);
199 RCBA32(0x0088) = 0x0011d000;
200 RCBA16(0x01fc) = 0x060f;
201 RCBA32(0x01f4) = 0x86000040;
202 RCBA32(0x0214) = 0x10030549;
203 RCBA32(0x0218) = 0x00020504;
204 RCBA8(0x0220) = 0xc5;
205 reg32 = RCBA32(0x3410);
207 RCBA32(0x3410) = reg32;
208 reg32 = RCBA32(0x3430);
211 RCBA32(0x3430) = reg32;
212 RCBA32(0x3418) |= (1 << 0);
213 RCBA16(0x0200) = 0x2008;
214 RCBA8(0x2027) = 0x0d;
215 RCBA16(0x3e08) |= (1 << 7);
216 RCBA16(0x3e48) |= (1 << 7);
217 RCBA32(0x3e0e) |= (1 << 7);
218 RCBA32(0x3e4e) |= (1 << 7);
220 // next step only on ich7m b0 and later:
221 reg32 = RCBA32(0x2034);
222 reg32 &= ~(0x0f << 16);
224 RCBA32(0x2034) = reg32;
229 // Now, this needs to be included because it relies on the symbol
230 // __PRE_RAM__ being set during CAR stage (in order to compile the
231 // BSS free versions of the functions). Either rewrite the code
232 // to be always BSS free, or invent a flag that's better suited than
233 // __PRE_RAM__ to determine whether we're in ram init stage (stage 1)
235 #include "lib/cbmem.c"
237 void main(unsigned long bist)
246 early_superio_config_w83627ehg();
248 /* Set up the console */
252 i82801gx_enable_usbdebug(1);
253 early_usbdebug_init();
258 /* Halt if there was a built in self test failure */
259 report_bist_failure(bist);
261 if (MCHBAR16(SSKPD) == 0xCAFE) {
262 printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n");
264 while (1) asm("hlt");
267 /* Perform some early chipset initialization required
268 * before RAM initialization can work
270 i945_early_initialization();
273 reg32 = inl(DEFAULT_PMBASE + 0x04);
274 printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32);
275 if (((reg32 >> 10) & 7) == 5) {
276 #if CONFIG_HAVE_ACPI_RESUME
277 printk(BIOS_DEBUG, "Resume from S3 detected.\n");
279 /* Clear SLP_TYPE. This will break stage2 but
280 * we care for that when we get there.
282 outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04);
284 printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
288 /* Enable SPD ROMs and DDR-II DRAM */
291 #if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
292 dump_spd_registers();
295 sdram_initialize(boot_mode);
297 /* Perform some initialization that must run before stage2 */
300 /* This should probably go away. Until now it is required
301 * and mainboard specific
305 /* Chipset Errata! */
308 /* Initialize the internal PCIe links before we go into stage2 */
309 i945_late_initialization();
311 #if !CONFIG_HAVE_ACPI_RESUME
312 #if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
313 #if CONFIG_DEBUG_RAM_SETUP
314 sdram_dump_mchbar_registers();
318 /* This will not work if TSEG is in place! */
319 u32 tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c);
321 printk(BIOS_DEBUG, "TOM: 0x%08x\n", tom);
322 ram_check(0x00000000, 0x000a0000);
323 //ram_check(0x00100000, tom);
330 MCHBAR16(SSKPD) = 0xCAFE;
332 #if CONFIG_HAVE_ACPI_RESUME
333 /* Start address of high memory tables */
334 unsigned long high_ram_base = get_top_of_ram() - HIGH_MEMORY_SIZE;
336 /* If there is no high memory area, we didn't boot before, so
337 * this is not a resume. In that case we just create the cbmem toc.
339 if ((boot_mode == 2) && cbmem_reinit((u64)high_ram_base)) {
340 void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME);
342 /* copy 1MB - 64K to high tables ram_base to prevent memory corruption
343 * through stage 2. We could keep stuff like stack and heap in high tables
344 * memory completely, but that's a wonderful clean up task for another
347 if (resume_backup_memory)
348 memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE, HIGH_MEMORY_SAVE);
350 /* Magic for S3 resume */
351 pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d);