src/mainboard/via/epia-m/romstage.c

   1 #include <stdint.h>
   2 #include <device/pci_def.h>
   3 #include <device/pci_ids.h>
   4 #include <arch/io.h>
   5 #include <device/pnp_def.h>
   6 #include <arch/romcc_io.h>
   7 #include <arch/hlt.h>
   8 #include <stdlib.h>
   9 #include <console/console.h>
  10 #include "lib/ramtest.c"
  11 #include "northbridge/via/vt8623/raminit.h"
  12 #include "cpu/x86/mtrr/earlymtrr.c"
  13 #include "cpu/x86/bist.h"
  14 #include "pc80/udelay_io.c"
  15 #include "lib/delay.c"
  16 #include "cpu/x86/lapic/boot_cpu.c"
  17 #include "lib/debug.c"
  18 #include "southbridge/via/vt8235/vt8235_early_smbus.c"
  19 #include "southbridge/via/vt8235/vt8235_early_serial.c"
  20
  21 static inline int spd_read_byte(unsigned device, unsigned address)
  22 {
  23         return smbus_read_byte(device, address);
  24 }
  25
  26 #include "northbridge/via/vt8623/raminit.c"
  27
  28 static void enable_mainboard_devices(void)
  29 {
  30         device_t dev;
  31
  32         dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA,
  33                                        PCI_DEVICE_ID_VIA_8235), 0);
  34
  35         if (dev == PCI_DEV_INVALID) {
  36                 die("Southbridge not found!!!\n");
  37         }
  38         pci_write_config8(dev, 0x50, 0x80);
  39         pci_write_config8(dev, 0x51, 0x1f);
  40 #if 0
  41         // This early setup switches IDE into compatibility mode before PCI gets
  42         // a chance to assign I/Os
  43         // movl    $CONFIG_ADDR(0, 0x89, 0x42), %eax
  44         // //      movb    $0x09, %dl
  45         // movb    $0x00, %dl
  46         // PCI_WRITE_CONFIG_BYTE
  47 #endif
  48         /* we do this here as in V2, we can not yet do raw operations
  49          * to pci!
  50          */
  51         dev += 0x100; /* ICKY */
  52
  53         pci_write_config8(dev, 0x04, 7);
  54         pci_write_config8(dev, 0x40, 3);
  55         pci_write_config8(dev, 0x42, 0);
  56         pci_write_config8(dev, 0x3c, 0xe);
  57         pci_write_config8(dev, 0x3d, 0);
  58 }
  59
  60 static void enable_shadow_ram(void)
  61 {
  62         device_t dev = 0; /* no need to look up 0:0.0 */
  63         unsigned char shadowreg;
  64         /* dev 0 for southbridge */
  65         shadowreg = pci_read_config8(dev, 0x63);
  66         /* 0xf0000-0xfffff */
  67         shadowreg |= 0x30;
  68         pci_write_config8(dev, 0x63, shadowreg);
  69 }
  70
  71 static void main(unsigned long bist)
  72 {
  73         device_t dev;
  74
  75         /* Enable VGA; 32MB buffer. */
  76         pci_write_config8(0, 0xe1, 0xdd);
  77
  78         /*
  79          * Disable the firewire stuff, which apparently steps on IO 0+ on
  80          * reset. Doh!
  81          */
  82         dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA,
  83                                 PCI_DEVICE_ID_VIA_6305), 0);
  84         if (dev != PCI_DEV_INVALID)
  85                 pci_write_config8(dev, 0x15, 0x1c);
  86
  87         enable_vt8235_serial();
  88         uart_init();
  89         console_init();
  90
  91         enable_smbus();
  92
  93         /* Halt if there was a built in self test failure */
  94         report_bist_failure(bist);
  95
  96         // init_timer();
  97
  98         post_code(0x05);
  99
 100         print_debug(" Enabling mainboard devices\n");
 101         enable_mainboard_devices();
 102
 103         print_debug(" Enabling shadow ram\n");
 104         enable_shadow_ram();
 105
 106         ddr_ram_setup((const struct mem_controller *)0);
 107
 108         /* Check all of memory */
 109 #if 0
 110         static const struct {
 111                 unsigned long lo, hi;
 112         } check_addrs[] = {
 113                 /* Check 16MB of memory @ 0*/
 114                 { 0x00000000, 0x01000000 },
 115         };
 116         int i;
 117         for(i = 0; i < ARRAY_SIZE(check_addrs); i++) {
 118                 ram_check(check_addrs[i].lo, check_addrs[i].hi);
 119         }
 120 #endif
 121
 122         if (bist == 0)
 123                 early_mtrr_init();
 124
 125         //dump_pci_devices();
 126 }