src/mainboard/tyan/s2895/romstage.c

   1 #include <stdint.h>
   2 #include <string.h>
   3 #include <device/pci_def.h>
   4 #include <arch/io.h>
   5 #include <device/pnp_def.h>
   6 #include <arch/romcc_io.h>
   7 #include <cpu/x86/lapic.h>
   8 #include <pc80/mc146818rtc.h>
   9 #include <console/console.h>
  10 #include <lib.h>
  11 #include <spd.h>
  12 #include <cpu/amd/model_fxx_rev.h>
  13 #include "northbridge/amd/amdk8/incoherent_ht.c"
  14 #include "southbridge/nvidia/ck804/ck804_early_smbus.h"
  15 #include "northbridge/amd/amdk8/raminit.h"
  16 #include "cpu/amd/model_fxx/apic_timer.c"
  17 #include "lib/delay.c"
  18 #include "cpu/x86/lapic/boot_cpu.c"
  19 #include "northbridge/amd/amdk8/reset_test.c"
  20 #include "superio/smsc/lpc47b397/lpc47b397_early_serial.c"
  21 #include "superio/smsc/lpc47b397/lpc47b397_early_gpio.c"
  22 #include "cpu/x86/bist.h"
  23 #include "northbridge/amd/amdk8/debug.c"
  24 #include <cpu/amd/mtrr.h>
  25 #include "cpu/x86/mtrr/earlymtrr.c"
  26 #include "northbridge/amd/amdk8/setup_resource_map.c"
  27
  28 #define SERIAL_DEV PNP_DEV(0x2e, LPC47B397_SP1)
  29 #define SUPERIO_GPIO_DEV PNP_DEV(0x2e, LPC47B397_RT)
  30 #define SUPERIO_GPIO_IO_BASE 0x400
  31
  32 static void memreset_setup(void) { }
  33 static void memreset(int controllers, const struct mem_controller *ctrl) { }
  34 static void activate_spd_rom(const struct mem_controller *ctrl) { }
  35
  36 static void sio_gpio_setup(void)
  37 {
  38         unsigned value;
  39
  40         /*Enable onboard scsi*/
  41         lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x2c,
  42           (1<<7)|(0<<2)|(0<<1)|(0<<0)); // GP21, offset 0x2c, DISABLE_SCSI_L
  43         value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x4c);
  44         lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x4c, (value|(1<<1)));
  45 }
  46
  47 static inline int spd_read_byte(unsigned device, unsigned address)
  48 {
  49         return smbus_read_byte(device, address);
  50 }
  51
  52 #include "northbridge/amd/amdk8/raminit.c"
  53 #include "northbridge/amd/amdk8/coherent_ht.c"
  54 #include "lib/generic_sdram.c"
  55 #include "resourcemap.c"
  56 #include "cpu/amd/dualcore/dualcore.c"
  57 #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
  58
  59 //set GPIO to input mode
  60 #define CK804_MB_SETUP \
  61         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 5, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M9,GPIO6, PCIXB2_PRSNT1_L*/  \
  62         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXB2_PRSNT2_L*/ \
  63         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/  \
  64         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 7, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M5,GPIO8, PCIXA_PRSNT2_L*/   \
  65         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/  \
  66         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/
  67
  68 #include "southbridge/nvidia/ck804/ck804_early_setup_car.c"
  69 #include "cpu/amd/car/post_cache_as_ram.c"
  70 #include "cpu/amd/model_fxx/init_cpus.c"
  71 #include "northbridge/amd/amdk8/early_ht.c"
  72
  73 static void sio_setup(void)
  74 {
  75         unsigned value;
  76         u32 dword;
  77         u8 byte;
  78
  79         pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1, 0), 0xac, 0x047f0400);
  80
  81         byte = pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
  82         byte |= 0x20;
  83         pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte);
  84
  85         dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0);
  86         dword |= (1<<29)|(1<<0);
  87         pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
  88
  89         dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1, 0), 0xa4);
  90         dword |= (1<<16);
  91         pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa4, dword);
  92
  93         lpc47b397_enable_serial(SUPERIO_GPIO_DEV, SUPERIO_GPIO_IO_BASE);
  94         value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x77);
  95         value &= 0xbf;
  96         lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x77, value);
  97 }
  98
  99 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 100 {
 101         static const u16 spd_addr [] = {
 102                 DIMM0, DIMM2, 0, 0,
 103                 DIMM1, DIMM3, 0, 0,
 104                 DIMM4, DIMM6, 0, 0,
 105                 DIMM5, DIMM7, 0, 0,
 106         };
 107
 108         int needs_reset;
 109         unsigned bsp_apicid = 0, nodes;
 110         struct mem_controller ctrl[8];
 111
 112         if (!cpu_init_detectedx && boot_cpu()) {
 113                 /* Nothing special needs to be done to find bus 0 */
 114                 /* Allow the HT devices to be found */
 115                 enumerate_ht_chain();
 116                 sio_setup();
 117         }
 118
 119         if (bist == 0)
 120                 bsp_apicid = init_cpus(cpu_init_detectedx);
 121
 122         lpc47b397_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 123         uart_init();
 124         console_init();
 125
 126         /* Halt if there was a built in self test failure */
 127         report_bist_failure(bist);
 128
 129         sio_gpio_setup();
 130
 131         setup_mb_resource_map();
 132
 133         needs_reset = setup_coherent_ht_domain();
 134
 135         wait_all_core0_started();
 136
 137         // It is said that we should start core1 after all core0 launched
 138         start_other_cores();
 139         wait_all_other_cores_started(bsp_apicid);
 140
 141         needs_reset |= ht_setup_chains_x();
 142         needs_reset |= ck804_early_setup_x();
 143         if (needs_reset) {
 144                 printk(BIOS_INFO, "ht reset -\n");
 145                 soft_reset();
 146         }
 147
 148         allow_all_aps_stop(bsp_apicid);
 149
 150         nodes = get_nodes();
 151         //It's the time to set ctrl now;
 152         fill_mem_ctrl(nodes, ctrl, spd_addr);
 153
 154         enable_smbus();
 155
 156         memreset_setup();
 157         sdram_initialize(nodes, ctrl);
 158
 159         post_cache_as_ram();
 160 }