2 * This file is part of the coreboot project.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 #if CONFIG_K8_REV_F_SUPPORT == 1
20 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
25 #include <device/pci_def.h>
26 #include <device/pci_ids.h>
28 #include <device/pnp_def.h>
29 #include <arch/romcc_io.h>
30 #include <cpu/x86/lapic.h>
31 #include <pc80/mc146818rtc.h>
32 #include <console/console.h>
35 #include <cpu/amd/model_fxx_rev.h>
36 #include "southbridge/nvidia/mcp55/mcp55_early_smbus.c" // for enable the FAN
37 #include "northbridge/amd/amdk8/raminit.h"
38 #include "cpu/amd/model_fxx/apic_timer.c"
39 #include "lib/delay.c"
40 #include "cpu/x86/lapic/boot_cpu.c"
41 #include "northbridge/amd/amdk8/reset_test.c"
42 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
43 #include "superio/winbond/w83627hf/w83627hf_early_init.c"
44 #include "cpu/x86/bist.h"
45 #include "northbridge/amd/amdk8/debug.c"
46 #include "cpu/x86/mtrr/earlymtrr.c"
47 #include "northbridge/amd/amdk8/setup_resource_map.c"
48 #include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
50 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
52 static void memreset(int controllers, const struct mem_controller *ctrl)
56 static inline void dump_smbus_registers(void)
61 for (device = 1; device < 0x80; device++) {
63 if (smbus_read_byte(device, 0) < 0)
65 printk(BIOS_DEBUG, "smbus: %02x", device);
66 for (j = 0; j < 256; j++) {
69 status = smbus_read_byte(device, j);
74 printk(BIOS_DEBUG, "\n%02x: ", j);
77 printk(BIOS_DEBUG, "%02x ", byte);
83 static inline void activate_spd_rom(const struct mem_controller *ctrl)
86 /* We don't do any switching yet. */
87 #define SMBUS_SWITCH1 0x48
88 #define SMBUS_SWITCH2 0x49
89 unsigned device=(ctrl->channel0[0])>>8;
90 smbus_send_byte(SMBUS_SWITCH1, device);
91 smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f);
96 static int smbus_send_byte_one(unsigned device, unsigned char val)
98 return do_smbus_send_byte(SMBUS1_IO_BASE, device, val);
101 static inline void change_i2c_mux(unsigned device)
103 #define SMBUS_SWITCH1 0x48
104 #define SMBUS_SWITHC2 0x49
105 smbus_send_byte(SMBUS_SWITCH1, device & 0x0f);
106 smbus_send_byte_one(SMBUS_SWITCH2, (device >> 4) & 0x0f);
108 print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\n");
109 dump_smbus_registers();
110 ret = smbus_send_byte(SMBUS_SWITCH1, device);
111 print_debug("change_i2c_mux ret="); print_debug_hex32(ret); print_debug("\n");
112 dump_smbus_registers();
113 ret = smbus_send_byte_one(SMBUS_SWITCH2, device);
114 print_debug("change_i2c_mux ret="); print_debug_hex32(ret); print_debug("\n");
115 dump_smbus_registers();
119 static inline int spd_read_byte(unsigned device, unsigned address)
121 return smbus_read_byte(device, address);
124 #include "northbridge/amd/amdk8/amdk8_f.h"
125 #include "northbridge/amd/amdk8/incoherent_ht.c"
126 #include "northbridge/amd/amdk8/coherent_ht.c"
127 #include "northbridge/amd/amdk8/raminit_f.c"
128 #include "lib/generic_sdram.c"
129 #include "resourcemap.c"
130 #include "cpu/amd/dualcore/dualcore.c"
131 #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
132 #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
133 #include "cpu/amd/car/post_cache_as_ram.c"
134 #include "cpu/amd/model_fxx/init_cpus.c"
135 #include "cpu/amd/model_fxx/fidvid.c"
136 #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
137 #include "northbridge/amd/amdk8/early_ht.c"
139 static void sio_setup(void)
145 // smbusx_write_byte(1, (0x58>>1), 0, 0x80); /* select bank0 */
146 smbusx_write_byte(1, (0x58 >> 1), 0xb1, 0xff); /* set FAN ctrl to DC mode */
148 byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0x7b);
150 pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0x7b, byte);
152 dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa0);
154 pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa0, dword);
156 dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa4);
158 pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa4, dword);
161 /* We have no idea where the SMBUS switch is. This doesn't do anything ATM. */
165 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
167 /* The SPD is being read from the CPU1 (marked CPU2 on the board) and we
168 don't know how to switch the SMBus to decode the CPU0 SPDs. So, The
169 memory on each CPU must be an exact match.
171 static const uint16_t spd_addr[] = {
173 RC0 | DIMM0, RC0 | DIMM2,
174 RC0 | DIMM4, RC0 | DIMM6,
175 RC0 | DIMM1, RC0 | DIMM3,
176 RC0 | DIMM5, RC0 | DIMM7,
178 RC1 | DIMM0, RC1 | DIMM2,
179 RC1 | DIMM4, RC1 | DIMM6,
180 RC1 | DIMM1, RC1 | DIMM3,
181 RC1 | DIMM5, RC1 | DIMM7,
184 struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
185 + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
188 unsigned bsp_apicid = 0;
190 if (!cpu_init_detectedx && boot_cpu()) {
191 /* Nothing special needs to be done to find bus 0 */
192 /* Allow the HT devices to be found */
194 enumerate_ht_chain();
198 /* Setup the mcp55 */
203 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
206 pnp_enter_ext_func_mode(SERIAL_DEV);
207 pnp_write_config(SERIAL_DEV, 0x24, 0x84 | (1 << 6));
208 w83627hf_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE);
209 pnp_exit_ext_func_mode(SERIAL_DEV);
214 /* Halt if there was a built in self test failure */
215 report_bist_failure(bist);
217 printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
219 setup_mb_resource_map();
221 print_debug("bsp_apicid=");
222 print_debug_hex8(bsp_apicid);
225 #if CONFIG_MEM_TRAIN_SEQ == 1
226 set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
228 /* dump_smbus_registers(); */
229 setup_coherent_ht_domain(); // routing table and start other core0
231 wait_all_core0_started();
232 #if CONFIG_LOGICAL_CPUS==1
233 // It is said that we should start core1 after all core0 launched
234 /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
235 * So here need to make sure last core0 is started, esp for two way system,
236 * (there may be apic id conflicts in that case)
239 wait_all_other_cores_started(bsp_apicid);
242 /* it will set up chains and store link pair for optimization later */
243 ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
245 #if CONFIG_SET_FIDVID
249 msr = rdmsr(0xc0010042);
250 print_debug("begin msr fid, vid ");
251 print_debug_hex32(msr.hi);
252 print_debug_hex32(msr.lo);
259 enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
261 init_fidvid_bsp(bsp_apicid);
263 // show final fid and vid
266 msr = rdmsr(0xc0010042);
267 print_debug("end msr fid, vid ");
268 print_debug_hex32(msr.hi);
269 print_debug_hex32(msr.lo);
275 init_timer(); /* Need to use TMICT to synconize FID/VID. */
277 needs_reset |= optimize_link_coherent_ht();
278 needs_reset |= optimize_link_incoherent_ht(sysinfo);
279 needs_reset |= mcp55_early_setup_x();
281 // fidvid change will issue one LDTSTOP and the HT change will be effective too
283 print_info("ht reset -\n");
287 allow_all_aps_stop(bsp_apicid);
289 //It's the time to set ctrl in sysinfo now;
290 fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
292 enable_smbus(); /* enable in sio_setup */
294 /* all ap stopped? */
296 sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
298 post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now