src/mainboard/tyan/s4880/romstage.c

   1 #include <stdint.h>
   2 #include <string.h>
   3 #include <device/pci_def.h>
   4 #include <arch/io.h>
   5 #include <device/pnp_def.h>
   6 #include <arch/romcc_io.h>
   7 #include <cpu/x86/lapic.h>
   8 #include <stdlib.h>
   9 #include <pc80/mc146818rtc.h>
  10 #include <console/console.h>
  11 #include <lib.h>
  12 #include <cpu/amd/model_fxx_rev.h>
  13 #include "northbridge/amd/amdk8/incoherent_ht.c"
  14 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  15 #include "northbridge/amd/amdk8/raminit.h"
  16 #include "cpu/amd/model_fxx/apic_timer.c"
  17 #include "lib/delay.c"
  18 #include "cpu/x86/lapic/boot_cpu.c"
  19 #include "northbridge/amd/amdk8/reset_test.c"
  20 #include "northbridge/amd/amdk8/debug.c"
  21 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  22 #include "cpu/x86/mtrr/earlymtrr.c"
  23 #include "cpu/x86/bist.h"
  24 #include "northbridge/amd/amdk8/setup_resource_map.c"
  25 #include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
  26
  27 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  28
  29 static void memreset_setup(void)
  30 {
  31    if (is_cpu_pre_c0())
  32         outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=0
  33    else
  34         outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=1
  35    outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
  36 }
  37
  38 static void memreset(int controllers, const struct mem_controller *ctrl)
  39 {
  40    if (is_cpu_pre_c0()) {
  41         udelay(800);
  42         outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
  43         udelay(90);
  44    }
  45 }
  46
  47 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  48 {
  49 #define SMBUS_HUB 0x18
  50         unsigned device=(ctrl->channel0[0])>>8;
  51         smbus_write_byte(SMBUS_HUB, 0x01, device);
  52         smbus_write_byte(SMBUS_HUB, 0x03, 0);
  53 }
  54
  55 #if 0
  56 static inline void change_i2c_mux(unsigned device)
  57 {
  58 #define SMBUS_HUB 0x18
  59         int ret;
  60         print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\n");
  61         ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
  62         print_debug("change_i2c_mux 1 ret="); print_debug_hex32(ret); print_debug("\n");
  63         ret = smbus_write_byte(SMBUS_HUB, 0x03, 0);
  64         print_debug("change_i2c_mux 2 ret="); print_debug_hex32(ret); print_debug("\n");
  65 }
  66 #endif
  67
  68 static inline int spd_read_byte(unsigned device, unsigned address)
  69 {
  70         return smbus_read_byte(device, address);
  71 }
  72
  73 #include "northbridge/amd/amdk8/raminit.c"
  74 #include "northbridge/amd/amdk8/coherent_ht.c"
  75 #include "lib/generic_sdram.c"
  76 #include "resourcemap.c"
  77 #include "cpu/amd/dualcore/dualcore.c"
  78 #include <spd.h>
  79 #include "cpu/amd/car/post_cache_as_ram.c"
  80 #include "cpu/amd/model_fxx/init_cpus.c"
  81 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
  82 #include "northbridge/amd/amdk8/early_ht.c"
  83
  84 #define RC0 ((1<<2)<<8)
  85 #define RC1 ((1<<1)<<8)
  86 #define RC2 ((1<<4)<<8)
  87 #define RC3 ((1<<3)<<8)
  88
  89 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
  90 {
  91         static const struct mem_controller cpu[] = {
  92                 {
  93                         .node_id = 0,
  94                         .f0 = PCI_DEV(0, 0x18, 0),
  95                         .f1 = PCI_DEV(0, 0x18, 1),
  96                         .f2 = PCI_DEV(0, 0x18, 2),
  97                         .f3 = PCI_DEV(0, 0x18, 3),
  98                         .channel0 = { RC0|DIMM0, RC0|DIMM2, 0, 0 },
  99                         .channel1 = { RC0|DIMM1, RC0|DIMM3, 0, 0 },
 100                 },
 101 #if CONFIG_MAX_PHYSICAL_CPUS > 1
 102                 {
 103                         .node_id = 1,
 104                         .f0 = PCI_DEV(0, 0x19, 0),
 105                         .f1 = PCI_DEV(0, 0x19, 1),
 106                         .f2 = PCI_DEV(0, 0x19, 2),
 107                         .f3 = PCI_DEV(0, 0x19, 3),
 108                         .channel0 = { RC1|DIMM0, RC1|DIMM2 , 0, 0 },
 109                         .channel1 = { RC1|DIMM1, RC1|DIMM3 , 0, 0 },
 110
 111                 },
 112 #endif
 113 #if CONFIG_MAX_PHYSICAL_CPUS > 2
 114                 {
 115                         .node_id = 2,
 116                         .f0 = PCI_DEV(0, 0x1a, 0),
 117                         .f1 = PCI_DEV(0, 0x1a, 1),
 118                         .f2 = PCI_DEV(0, 0x1a, 2),
 119                         .f3 = PCI_DEV(0, 0x1a, 3),
 120                         .channel0 = { RC2|DIMM0, RC2|DIMM2, 0, 0 },
 121                         .channel1 = { RC2|DIMM1, RC2|DIMM3, 0, 0 },
 122
 123                 },
 124                 {
 125                         .node_id = 3,
 126                         .f0 = PCI_DEV(0, 0x1b, 0),
 127                         .f1 = PCI_DEV(0, 0x1b, 1),
 128                         .f2 = PCI_DEV(0, 0x1b, 2),
 129                         .f3 = PCI_DEV(0, 0x1b, 3),
 130                         .channel0 = { RC3|DIMM0, RC3|DIMM2, 0, 0 },
 131                         .channel1 = { RC3|DIMM1, RC3|DIMM3, 0, 0 },
 132
 133                 },
 134 #endif
 135         };
 136
 137         int needs_reset;
 138
 139         if (!cpu_init_detectedx && boot_cpu()) {
 140                 /* Nothing special needs to be done to find bus 0 */
 141                 /* Allow the HT devices to be found */
 142                 enumerate_ht_chain();
 143                 amd8111_enable_rom();
 144         }
 145
 146         if (bist == 0)
 147                 init_cpus(cpu_init_detectedx);
 148
 149         w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 150         uart_init();
 151         console_init();
 152
 153         /* Halt if there was a built in self test failure */
 154         report_bist_failure(bist);
 155
 156         setup_s4880_resource_map();
 157
 158         needs_reset = setup_coherent_ht_domain();
 159
 160 #if CONFIG_LOGICAL_CPUS==1
 161         // It is said that we should start core1 after all core0 launched
 162         start_other_cores();
 163 #endif
 164         // automatically set that for you, but you might meet tight space
 165         needs_reset |= ht_setup_chains_x();
 166
 167         if (needs_reset) {
 168                 print_info("ht reset -\n");
 169                 soft_reset();
 170         }
 171
 172         enable_smbus();
 173
 174         memreset_setup();
 175         sdram_initialize(ARRAY_SIZE(cpu), cpu);
 176
 177         post_cache_as_ram();
 178 }