src/mainboard/tyan/s2891/romstage.c

   1 #include <stdint.h>
   2 #include <string.h>
   3 #include <device/pci_def.h>
   4 #include <arch/io.h>
   5 #include <device/pnp_def.h>
   6 #include <arch/romcc_io.h>
   7 #include <cpu/x86/lapic.h>
   8 #include <pc80/mc146818rtc.h>
   9 #include <console/console.h>
  10 #include <lib.h>
  11 #include <spd.h>
  12 #include <cpu/amd/model_fxx_rev.h>
  13 #include "northbridge/amd/amdk8/incoherent_ht.c"
  14 #include "southbridge/nvidia/ck804/ck804_early_smbus.h"
  15 #include "northbridge/amd/amdk8/raminit.h"
  16 #include "cpu/amd/model_fxx/apic_timer.c"
  17 #include "lib/delay.c"
  18 #include "cpu/x86/lapic/boot_cpu.c"
  19 #include "northbridge/amd/amdk8/reset_test.c"
  20 #include "northbridge/amd/amdk8/debug.c"
  21 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  22 #include "cpu/x86/mtrr/earlymtrr.c"
  23 #include "cpu/x86/bist.h"
  24 #include "northbridge/amd/amdk8/setup_resource_map.c"
  25
  26 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  27
  28 static void memreset_setup(void) { }
  29 static void memreset(int controllers, const struct mem_controller *ctrl) { }
  30 static void activate_spd_rom(const struct mem_controller *ctrl) { }
  31
  32 static inline int spd_read_byte(unsigned device, unsigned address)
  33 {
  34         return smbus_read_byte(device, address);
  35 }
  36
  37 #include "northbridge/amd/amdk8/raminit.c"
  38 #include "northbridge/amd/amdk8/coherent_ht.c"
  39 #include "lib/generic_sdram.c"
  40 #include "resourcemap.c"
  41 #include "cpu/amd/dualcore/dualcore.c"
  42 #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
  43 #include "southbridge/nvidia/ck804/ck804_early_setup.c"
  44 #include "cpu/amd/car/post_cache_as_ram.c"
  45 #include "cpu/amd/model_fxx/init_cpus.c"
  46 #include "northbridge/amd/amdk8/early_ht.c"
  47
  48 static void sio_setup(void)
  49 {
  50         uint32_t dword;
  51         uint8_t byte;
  52
  53         /* subject decoding*/
  54         byte = pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
  55         byte |= 0x20;
  56         pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte);
  57
  58         /* LPC Positive Decode 0 */
  59         dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0);
  60         /* Serial 0, Serial 1 */
  61         dword |= (1<<0) | (1<<1);
  62         pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
  63
  64 #if 1
  65         /* s2891 has onboard LPC port 80 */
  66         /*Hope I can enable port 80 here
  67         It will decode port 80 to LPC, If you are using PCI post code you can not do this */
  68         dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa4);
  69         dword |= (1<<16);
  70         pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa4, dword);
  71 #endif
  72 }
  73
  74 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
  75 {
  76         static const uint16_t spd_addr [] = {
  77                 DIMM0, DIMM2, 0, 0,
  78                 DIMM1, DIMM3, 0, 0,
  79 #if CONFIG_MAX_PHYSICAL_CPUS > 1
  80                 DIMM4, DIMM6, 0, 0,
  81                 DIMM5, DIMM7, 0, 0,
  82 #endif
  83         };
  84
  85         int needs_reset;
  86         unsigned bsp_apicid = 0, nodes;
  87         struct mem_controller ctrl[8];
  88
  89         if (!cpu_init_detectedx && boot_cpu()) {
  90                 /* Nothing special needs to be done to find bus 0 */
  91                 /* Allow the HT devices to be found */
  92                 enumerate_ht_chain();
  93                 sio_setup();
  94         }
  95
  96         if (bist == 0)
  97                 bsp_apicid = init_cpus(cpu_init_detectedx);
  98
  99 //      post_code(0x32);
 100
 101         w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 102         uart_init();
 103         console_init();
 104
 105         /* Halt if there was a built in self test failure */
 106         report_bist_failure(bist);
 107
 108         setup_s2891_resource_map();
 109 #if 0
 110         dump_pci_device(PCI_DEV(0, 0x18, 0));
 111         dump_pci_device(PCI_DEV(0, 0x19, 0));
 112 #endif
 113
 114         needs_reset = setup_coherent_ht_domain();
 115
 116         wait_all_core0_started();
 117 #if CONFIG_LOGICAL_CPUS==1
 118         // It is said that we should start core1 after all core0 launched
 119         start_other_cores();
 120         wait_all_other_cores_started(bsp_apicid);
 121 #endif
 122
 123         needs_reset |= ht_setup_chains_x();
 124         needs_reset |= ck804_early_setup_x();
 125         if (needs_reset) {
 126                 printk(BIOS_INFO, "ht reset -\n");
 127                 soft_reset();
 128         }
 129
 130         allow_all_aps_stop(bsp_apicid);
 131
 132         nodes = get_nodes();
 133         //It's the time to set ctrl now;
 134         fill_mem_ctrl(nodes, ctrl, spd_addr);
 135
 136         enable_smbus();
 137 #if 0
 138         dump_spd_registers(&cpu[0]);
 139         dump_smbus_registers();
 140 #endif
 141
 142         memreset_setup();
 143         sdram_initialize(nodes, ctrl);
 144
 145 #if 0
 146         print_pci_devices();
 147         dump_pci_devices();
 148 #endif
 149
 150         post_cache_as_ram();
 151 }