2 * This file is part of the coreboot project.
4 * Copyright (C) 2008-2010 Joseph Smith <joe@settoplinux.org>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
23 #include <device/pci_def.h>
25 #include <device/pnp_def.h>
26 #include <arch/romcc_io.h>
28 #include "pc80/udelay_io.c"
29 #include <console/console.h>
31 #include "superio/smsc/smscsuperio/smscsuperio_early_serial.c"
32 #include "northbridge/intel/i82830/raminit.h"
33 #include "northbridge/intel/i82830/memory_initialized.c"
34 #include "southbridge/intel/i82801dx/i82801dx.h"
35 #include "southbridge/intel/i82801dx/i82801dx_reset.c"
36 #include "cpu/x86/bist.h"
37 #include "spd_table.h"
39 #include "southbridge/intel/i82801dx/i82801dx_early_smbus.c"
40 #include "southbridge/intel/i82801dx/i82801dx_tco_timer.c"
42 #define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1)
45 * The onboard 64MB PC133 memory does not have a SPD EEPROM so the
46 * values have to be set manually, the SO-DIMM socket is located in
47 * socket0 (0x50/DIMM0), and the onboard memory is located in socket1
50 static inline int spd_read_byte(unsigned device, unsigned address)
54 if (device == DIMM0) {
55 return smbus_read_byte(device, address);
56 } else if (device == DIMM1) {
57 for (i = 0; i < ARRAY_SIZE(spd_table); i++) {
58 if (spd_table[i].address == address)
59 return spd_table[i].data;
61 return 0xFF; /* Return 0xFF when address is not found. */
63 return 0xFF; /* Return 0xFF on any failures. */
67 #include "northbridge/intel/i82830/raminit.c"
70 * Setup mainboard specific registers pre raminit.
72 static void mb_early_setup(void)
74 /* - Hub Interface to PCI Bridge Registers - */
75 /* 12-Clock Retry Enable */
76 pci_write_config16(PCI_DEV(0, 0x1e, 0), 0x50, 0x1402);
77 /* Master Latency Timer Count */
78 pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20);
79 /* I/O Address Base */
80 pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1c, 0xf0);
82 /* - LPC Interface Bridge Registers - */
83 /* Delayed Transaction Enable */
84 pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xd0, 0x00000002);
85 /* Disable the TCO Timer system reboot feature */
86 pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xd4, 0x02);
87 /* CPU Frequency Strap */
88 pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xd5, 0x02);
89 /* ACPI base address and enable Resource Indicator */
90 pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, (PMBASE_ADDR | 1));
91 /* Enable the SMBUS */
93 /* ACPI base address and disable Resource Indicator */
94 pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, (PMBASE_ADDR));
96 pci_write_config8(PCI_DEV(0, 0x1f, 0), ACPI_CNTL, 0x10);
99 void main(unsigned long bist)
102 if (memory_initialized())
106 /* Set southbridge and superio gpios */
109 smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
113 /* Halt if there was a built in self test failure. */
114 report_bist_failure(bist);
116 /* disable TCO timers */
117 i82801dx_halt_tco_timer();
119 /* Setup mainboard specific registers */
122 /* Initialize memory */
126 /* ram_check(0, 640 * 1024); */
127 /* ram_check(64512 * 1024, 65536 * 1024); */