src/mainboard/kontron/kt690/romstage.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2008 Advanced Micro Devices, Inc.
   5  * Copyright (C) 2009 coresystems GmbH
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  19  */
  20
  21 #define RC0 (6<<8)
  22 #define RC1 (7<<8)
  23
  24 #define SMBUS_HUB 0x71
  25
  26 #include <stdint.h>
  27 #include <string.h>
  28 #include <device/pci_def.h>
  29 #include <arch/io.h>
  30 #include <device/pnp_def.h>
  31 #include <arch/romcc_io.h>
  32 #include <cpu/x86/lapic.h>
  33 #include <pc80/mc146818rtc.h>
  34 #include <console/console.h>
  35 #include <cpu/amd/model_fxx_rev.h>
  36 #include "northbridge/amd/amdk8/raminit.h"
  37 #include "cpu/amd/model_fxx/apic_timer.c"
  38 #include "lib/delay.c"
  39 #include <spd.h>
  40 #include "cpu/x86/lapic/boot_cpu.c"
  41 #include "northbridge/amd/amdk8/reset_test.c"
  42 #include "northbridge/amd/amdk8/debug.c"
  43 #include "superio/winbond/w83627dhg/w83627dhg_early_serial.c"
  44 #include <usbdebug.h>
  45 #include <cpu/amd/mtrr.h>
  46 #include "cpu/x86/bist.h"
  47 #include "northbridge/amd/amdk8/setup_resource_map.c"
  48 #include "southbridge/amd/rs690/rs690_early_setup.c"
  49 #include "southbridge/amd/sb600/sb600_early_setup.c"
  50
  51 static void memreset(int controllers, const struct mem_controller *ctrl) { }
  52 static void activate_spd_rom(const struct mem_controller *ctrl) { }
  53
  54 static inline int spd_read_byte(u32 device, u32 address)
  55 {
  56         return smbus_read_byte(device, address);
  57 }
  58
  59 #include "northbridge/amd/amdk8/amdk8.h"
  60 #include "northbridge/amd/amdk8/incoherent_ht.c"
  61 #include "northbridge/amd/amdk8/raminit_f.c"
  62 #include "northbridge/amd/amdk8/coherent_ht.c"
  63 #include "lib/generic_sdram.c"
  64 #include "resourcemap.c"
  65 #include "cpu/amd/dualcore/dualcore.c"
  66 #include "cpu/amd/car/post_cache_as_ram.c"
  67 #include "cpu/amd/model_fxx/init_cpus.c"
  68 #include "cpu/amd/model_fxx/fidvid.c"
  69 #include "northbridge/amd/amdk8/early_ht.c"
  70
  71 #define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1)
  72
  73 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
  74 {
  75         static const u16 spd_addr[] = { DIMM0, 0, 0, 0, DIMM1, 0, 0, 0, };
  76         int needs_reset = 0;
  77         u32 bsp_apicid = 0;
  78         msr_t msr;
  79         struct cpuid_result cpuid1;
  80         struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
  81
  82         if (!cpu_init_detectedx && boot_cpu()) {
  83                 /* Nothing special needs to be done to find bus 0 */
  84                 /* Allow the HT devices to be found */
  85                 enumerate_ht_chain();
  86                 /* sb600_lpc_port80(); */
  87                 sb600_pci_port80();
  88         }
  89
  90         if (bist == 0)
  91                 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
  92
  93         enable_rs690_dev8();
  94         sb600_lpc_init();
  95
  96         w83627dhg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
  97         uart_init();
  98
  99 #if CONFIG_USBDEBUG
 100         sb600_enable_usbdebug(0);
 101         early_usbdebug_init();
 102 #endif
 103
 104         console_init();
 105
 106         /* Halt if there was a built in self test failure */
 107         report_bist_failure(bist);
 108         printk(BIOS_DEBUG, "bsp_apicid=0x%x\n", bsp_apicid);
 109
 110         setup_kt690_resource_map();
 111
 112         setup_coherent_ht_domain();
 113
 114 #if CONFIG_LOGICAL_CPUS==1
 115         /* It is said that we should start core1 after all core0 launched */
 116         wait_all_core0_started();
 117         start_other_cores();
 118 #endif
 119         wait_all_aps_started(bsp_apicid);
 120
 121         ht_setup_chains_x(sysinfo);
 122
 123         /* run _early_setup before soft-reset. */
 124         rs690_early_setup();
 125         sb600_early_setup();
 126
 127         /* Check to see if processor is capable of changing FIDVID  */
 128         /* otherwise it will throw a GP# when reading FIDVID_STATUS */
 129         cpuid1 = cpuid(0x80000007);
 130         if ((cpuid1.edx & 0x6) == 0x6) {
 131                 /* Read FIDVID_STATUS */
 132                 msr=rdmsr(0xc0010042);
 133                 printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
 134
 135                 enable_fid_change();
 136                 enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
 137                 init_fidvid_bsp(bsp_apicid);
 138
 139                 /* show final fid and vid */
 140                 msr=rdmsr(0xc0010042);
 141                 printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
 142         } else {
 143                 printk(BIOS_DEBUG, "Changing FIDVID not supported\n");
 144                 printk(BIOS_SPEW, "... because cpuid returned %08x\n", cpuid1.edx);
 145         }
 146
 147         needs_reset = optimize_link_coherent_ht();
 148         needs_reset |= optimize_link_incoherent_ht(sysinfo);
 149         rs690_htinit();
 150         printk(BIOS_DEBUG, "needs_reset=0x%x\n", needs_reset);
 151
 152         if (needs_reset) {
 153                 print_info("ht reset -\n");
 154                 soft_reset();
 155         }
 156
 157         allow_all_aps_stop(bsp_apicid);
 158
 159         /* It's the time to set ctrl now; */
 160         printk(BIOS_DEBUG, "sysinfo->nodes: %2x  sysinfo->ctrl: %p  spd_addr: %p\n",
 161                      sysinfo->nodes, sysinfo->ctrl, spd_addr);
 162         fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 163         sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 164
 165         rs690_before_pci_init();
 166         sb600_before_pci_init();
 167
 168         post_cache_as_ram();
 169 }