2 * This file is part of the coreboot project.
4 * Copyright (C) 2007 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 #include <device/pci_def.h>
24 #include <device/pnp_def.h>
25 #include <arch/romcc_io.h>
28 #include <console/console.h>
29 #include "cpu/x86/bist.h"
30 #include "cpu/x86/msr.h"
31 #include <cpu/amd/lxdef.h>
32 #include <cpu/amd/geode_post_code.h>
33 #include "southbridge/amd/cs5536/cs5536.h"
34 #include "spd_table.h"
36 #include "southbridge/amd/cs5536/cs5536_early_smbus.c"
37 #include "southbridge/amd/cs5536/cs5536_early_setup.c"
39 static int spd_read_byte(unsigned device, unsigned address)
43 if (device == DIMM0) {
44 for (i=0; i < (ARRAY_SIZE(spd_table)); i++) {
45 if (spd_table[i].address == address) {
46 return spd_table[i].data;
51 /* returns 0xFF on any failures */
55 #define ManualConf 0 /* Do automatic strapped PLL config */
56 /* CPU and GLIU mult/div 500/266*/
57 #define PLLMSRhi 0x0000039C /* 33MHz PCI, 0x000003DD for 66MHz PCI */
58 /* Hold Count - how long we will sit in reset */
59 #define PLLMSRlo 0x00DE6000
61 #include "northbridge/amd/lx/raminit.h"
62 #include "northbridge/amd/lx/pll_reset.c"
63 #include "northbridge/amd/lx/raminit.c"
64 #include "lib/generic_sdram.c"
65 #include "cpu/amd/model_lx/cpureginit.c"
66 #include "cpu/amd/model_lx/syspreinit.c"
67 #include "cpu/amd/model_lx/msrinit.c"
69 static void mb_gpio_init(void)
71 /* Early mainboard specific GPIO setup */
74 void main(unsigned long bist)
79 static const struct mem_controller memctrl[] = {
80 {.channel0 = {DIMM0, DIMM1}}
88 /* NOTE: must do this AFTER the early_setup!
89 * it is counting on some early MSR setup
92 /* cs5536_disable_internal_uart disable them. Set them up now... */
93 cs5536_setup_onchipuart(2); /* dbe61 uses UART2 as COM1 */
94 /* set address to 3F8 */
95 msr = rdmsr(MDD_LEG_IO);
97 wrmsr(MDD_LEG_IO, msr);
103 /* Halt if there was a built in self test failure */
104 report_bist_failure(bist);
106 pll_reset(ManualConf);
108 cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);
110 sdram_initialize(1, memctrl);
112 /* Dump memory configuratation */
114 msr = rdmsr(MC_CF07_DATA);
115 print_debug("MC_CF07_DATA: ");
116 print_debug_hex32(MC_CF07_DATA);
117 print_debug(" value is: ");
118 print_debug_hex32(msr.hi);
120 print_debug_hex32(msr.lo);
123 msr = rdmsr(MC_CF1017_DATA);
124 print_debug("MC_CF1017_DATA: ");
125 print_debug_hex32(MC_CF1017_DATA);
126 print_debug(" value is: ");
127 print_debug_hex32(msr.hi);
129 print_debug_hex32(msr.lo);
132 msr = rdmsr(MC_CF8F_DATA);
133 print_debug("MC_CF8F_DATA: ");
134 print_debug_hex32(MC_CF8F_DATA);
135 print_debug(" value is: ");
136 print_debug_hex32(msr.hi);
138 print_debug_hex32(msr.lo);
139 msr = rdmsr(MC_CF8F_DATA);
144 // ram_check(0x00000000, 640 * 1024);
145 // ram_check(1024 * 1024, 2 * 1024 * 1024);