2 * This file is part of the coreboot project.
4 * Copyright (C) 2007 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
23 #include <device/pci_def.h>
25 #include <device/pnp_def.h>
26 #include <arch/romcc_io.h>
28 #include <console/console.h>
30 #include "cpu/x86/bist.h"
31 #include "cpu/x86/msr.h"
32 #include <cpu/amd/lxdef.h>
33 #include <cpu/amd/geode_post_code.h>
34 #include "southbridge/amd/cs5536/cs5536.h"
36 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
38 /* The ALIX.2D has no SMBus; the setup is hard-wired. */
39 static void cs5536_enable_smbus(void)
43 #include "southbridge/amd/cs5536/cs5536_early_setup.c"
45 /* The part is a Hynix hy5du121622ctp-d43.
47 * HY 5D U 12 16 2 2 C <blank> T <blank> P D43
50 * VDD 2.5 VDDQ 2.5 (U)
51 * 512M 8K REFRESH (12)
56 * Normal Power Consumption (<blank> )
58 * Single Die (<blank>)
63 static const u8 spdbytes[] = {
64 [SPD_ACCEPTABLE_CAS_LATENCIES] = 0x10,
65 [SPD_BANK_DENSITY] = 0x40,
66 [SPD_DEVICE_ATTRIBUTES_GENERAL] = 0xff,
67 [SPD_MEMORY_TYPE] = 7,
68 [SPD_MIN_CYCLE_TIME_AT_CAS_MAX] = 10, /* A guess for the tRAC value */
69 [SPD_MODULE_ATTRIBUTES] = 0xff, /* FIXME later when we figure out. */
70 [SPD_NUM_BANKS_PER_SDRAM] = 4,
71 [SPD_PRIMARY_SDRAM_WIDTH] = 8,
72 [SPD_NUM_DIMM_BANKS] = 1, /* ALIX1.C is 1 bank. */
73 [SPD_NUM_COLUMNS] = 0xa,
76 [SPD_SDRAM_CYCLE_TIME_2ND] = 60,
77 [SPD_SDRAM_CYCLE_TIME_3RD] = 75,
85 static u8 spd_read_byte(u8 device, u8 address)
87 print_debug("spd_read_byte dev ");
88 print_debug_hex8(device);
90 if (device != DIMM0) {
91 print_debug(" returns 0xff\n");
95 print_debug(" addr ");
96 print_debug_hex8(address);
97 print_debug(" returns ");
98 print_debug_hex8(spdbytes[address]);
101 return spdbytes[address];
104 #define ManualConf 0 /* Do automatic strapped PLL config */
105 #define PLLMSRhi 0x00001490 /* Manual settings for the PLL */
106 #define PLLMSRlo 0x02000030
108 #include "northbridge/amd/lx/raminit.h"
109 #include "northbridge/amd/lx/pll_reset.c"
110 #include "northbridge/amd/lx/raminit.c"
111 #include "lib/generic_sdram.c"
112 #include "cpu/amd/model_lx/cpureginit.c"
113 #include "cpu/amd/model_lx/syspreinit.c"
114 #include "cpu/amd/model_lx/msrinit.c"
116 /** Early mainboard specific GPIO setup. */
117 static void mb_gpio_init(void)
120 * Enable LEDs GPIO outputs to light up the leds
121 * This is how the original tinyBIOS sets them after boot.
122 * Info: GPIO_IO_BASE, 0x6100, is only valid before PCI init, so it
123 * may be used here, but not after PCI Init.
124 * Note: Prior to a certain release, Linux used a hardwired 0x6100 in the
125 * leds-alix2.c driver. Coreboot dynamically assigns this space,
126 * so the driver does not work anymore.
127 * Good workaround: use the newer driver
128 * Ugly workaround: $ wrmsr 0x5140000C 0xf00100006100
129 * This resets the GPIO I/O space to 0x6100.
130 * This may break other things, though.
132 outl(1 << 6, GPIO_IO_BASE + GPIOL_OUTPUT_ENABLE);
133 outl(1 << 9, GPIO_IO_BASE + GPIOH_OUTPUT_ENABLE);
134 outl(1 << 11, GPIO_IO_BASE + GPIOH_OUTPUT_ENABLE);
136 /* outl(1 << 6, GPIO_IO_BASE + GPIOL_OUTPUT_VALUE); */ /* Led 1 enabled */
137 outl(1 << 9, GPIO_IO_BASE + GPIOH_OUTPUT_VALUE); /* Led 2 disabled */
138 outl(1 << 11, GPIO_IO_BASE + GPIOH_OUTPUT_VALUE); /* Led 3 disabled */
141 void main(unsigned long bist)
143 static const struct mem_controller memctrl[] = {
144 {.channel0 = {DIMM0}},
152 cs5536_early_setup();
154 /* NOTE: Must do this AFTER cs5536_early_setup()!
155 * It is counting on some early MSR setup for the CS5536.
157 cs5536_setup_onchipuart(1);
162 /* Halt if there was a built in self test failure */
163 report_bist_failure(bist);
165 pll_reset(ManualConf);
167 cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);
169 sdram_initialize(1, memctrl);
172 /* Enable this only if you are having questions. */
173 /* ram_check(0, 640 * 1024); */
175 /* Switch from Cache as RAM to real RAM.
177 * There are two ways we could think about this.
179 * 1. If we are using the romstage.inc ROMCC way, the stack is
180 * going to be re-setup in the code following this code. Just
181 * wbinvd the stack to clear the cache tags. We don't care
182 * where the stack used to be.
184 * 2. This file is built as a normal .c -> .o and linked in
185 * etc. The stack might be used to return etc. That means we
186 * care about what is in the stack. If we are smart we set
187 * the CAR stack to the same location as the rest of
188 * coreboot. If that is the case we can just do a wbinvd.
189 * The stack will be written into real RAM that is now setup
190 * and we continue like nothing happened. If the stack is
191 * located somewhere other than where LB would like it, you
192 * need to write some code to do a copy from cache to RAM
194 * We use method 1 on Norwich and on this board too.
197 print_err("POST 02\n");
199 print_err("Past wbinvd\n");
201 /* We are finding the return does not work on this board. Explicitly
202 * call the label that is after the call to us. This is gross, but
203 * sometimes at this level it is the only way out.
205 void done_cache_as_ram_main(void);
206 done_cache_as_ram_main();