2 * This file is part of the coreboot project.
4 * Copyright (C) 2010 Advanced Micro Devices, Inc.
5 * Copyright (C) 2010 Rudolf Marek <r.marek@assembler.cz>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
24 #define SMBUS_HUB 0x71
28 #include <device/pci_def.h>
30 #include <device/pnp_def.h>
31 #include <arch/romcc_io.h>
32 #include <cpu/x86/lapic.h>
33 #include <pc80/mc146818rtc.h>
34 #include <console/console.h>
35 #include <cpu/amd/model_fxx_rev.h>
36 #include "northbridge/amd/amdk8/raminit.h"
37 #include "cpu/amd/model_fxx/apic_timer.c"
38 #include "lib/delay.c"
40 #include "cpu/x86/lapic/boot_cpu.c"
41 #include "northbridge/amd/amdk8/reset_test.c"
42 #include "superio/winbond/w83627dhg/w83627dhg_early_serial.c"
44 #include "cpu/x86/mtrr/earlymtrr.c"
45 #include "cpu/x86/bist.h"
46 #include "northbridge/amd/amdk8/setup_resource_map.c"
47 #include "southbridge/amd/rs780/rs780_early_setup.c"
48 #include "southbridge/amd/sb700/sb700_early_setup.c"
49 #include "northbridge/amd/amdk8/debug.c" /* After sb700_early_setup.c! */
51 #define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1)
52 #define GPIO6_DEV PNP_DEV(0x2e, W83627DHG_GPIO6)
53 #define GPIO2345_DEV PNP_DEV(0x2e, W83627DHG_GPIO2345)
55 static void memreset(int controllers, const struct mem_controller *ctrl) { }
56 static void activate_spd_rom(const struct mem_controller *ctrl) { }
58 static inline int spd_read_byte(u32 device, u32 address)
60 return smbus_read_byte(device, address);
63 #include "northbridge/amd/amdk8/amdk8.h"
64 #include "northbridge/amd/amdk8/incoherent_ht.c"
65 #include "northbridge/amd/amdk8/raminit.c"
66 #include "northbridge/amd/amdk8/coherent_ht.c"
67 #include "lib/generic_sdram.c"
68 #include "resourcemap.c"
69 #include "cpu/amd/dualcore/dualcore.c"
70 #include "cpu/amd/car/post_cache_as_ram.c"
71 #include "cpu/amd/model_fxx/init_cpus.c"
72 #include "cpu/amd/model_fxx/fidvid.c"
73 #include "northbridge/amd/amdk8/early_ht.c"
75 static void sio_init(void)
79 pnp_enter_ext_func_mode(GPIO2345_DEV);
80 pnp_set_logical_device(GPIO2345_DEV);
82 /* Pin 119 ~ 120 GP21, GP20 */
83 reg = pnp_read_config(GPIO2345_DEV, 0x29);
84 pnp_write_config(GPIO2345_DEV, 0x29, (reg | 2));
86 /* todo document this */
87 pnp_write_config(GPIO2345_DEV, 0x2c, 0x1);
88 pnp_write_config(GPIO2345_DEV, 0x2d, 0x1);
90 //idx 30 e0 e1 e2 e3 e4 e5 e6 e7 e8 e9 f0 f1 f2 f3 f4 f5 f6 f7 fe
91 //val 07 XX XX XX f6 0e 00 00 00 00 ff d6 96 00 40 d0 83 00 00 07
93 //GPO20 - 1 = 1.82 0 = 1.92 sideport voltage
94 //mGPUV GPO40 | GPO41 | GPIO23 - 000 - 1.45V step 0.05 -- 111 - 1.10V
95 //DDR voltage 44 45 46
97 /* GPO20 - sideport voltage GPO23 - mgpuV */
98 pnp_write_config(GPIO2345_DEV, 0x30, 0x07); /* Enable GPIO 2,3,4. */
99 pnp_write_config(GPIO2345_DEV, 0xe3, 0xf6); /* dir of GPIO2 11110110*/
100 pnp_write_config(GPIO2345_DEV, 0xe4, 0x0e); /* data */
101 pnp_write_config(GPIO2345_DEV, 0xe5, 0x00); /* No inversion */
103 /* GPO30 GPO33 GPO35 */
104 //GPO35 - loadline control 0 - enabled
107 pnp_write_config(GPIO2345_DEV, 0xf0, 0xd6); /* dir of GPIO3 11010110*/
108 pnp_write_config(GPIO2345_DEV, 0xf1, 0x96); /* data */
109 pnp_write_config(GPIO2345_DEV, 0xf2, 0x00); /* No inversion */
111 /* GPO40 GPO41 GPO42 GPO43 PO45 */
112 pnp_write_config(GPIO2345_DEV, 0xf4, 0xd0); /* dir of GPIO4 11010000 */
113 pnp_write_config(GPIO2345_DEV, 0xf5, 0x83); /* data */
114 pnp_write_config(GPIO2345_DEV, 0xf6, 0x00); /* No inversion */
116 pnp_write_config(GPIO2345_DEV, 0xf7, 0x00); /* MFC */
117 pnp_write_config(GPIO2345_DEV, 0xf8, 0x00); /* MFC */
118 pnp_write_config(GPIO2345_DEV, 0xfe, 0x07); /* trig type */
119 pnp_exit_ext_func_mode(GPIO2345_DEV);
122 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
124 static const u16 spd_addr[] = { DIMM0, 0, 0, 0, DIMM1, 0, 0, 0, };
128 struct cpuid_result cpuid1;
129 struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
131 if (!cpu_init_detectedx && boot_cpu()) {
132 /* Nothing special needs to be done to find bus 0 */
133 /* Allow the HT devices to be found */
134 enumerate_ht_chain();
135 /* sb700_lpc_port80(); */
140 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
146 w83627dhg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
150 sb700_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
151 early_usbdebug_init();
156 /* Halt if there was a built in self test failure */
157 report_bist_failure(bist);
158 printk(BIOS_DEBUG, "bsp_apicid=0x%x\n", bsp_apicid);
160 setup_939a785gmh_resource_map();
162 setup_coherent_ht_domain();
164 #if CONFIG_LOGICAL_CPUS==1
165 /* It is said that we should start core1 after all core0 launched */
166 wait_all_core0_started();
169 wait_all_aps_started(bsp_apicid);
171 ht_setup_chains_x(sysinfo);
173 /* run _early_setup before soft-reset. */
177 /* Check to see if processor is capable of changing FIDVID */
178 /* otherwise it will throw a GP# when reading FIDVID_STATUS */
179 cpuid1 = cpuid(0x80000007);
180 if ((cpuid1.edx & 0x6) == 0x6) {
181 /* Read FIDVID_STATUS */
182 msr=rdmsr(0xc0010042);
183 printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
186 enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
187 init_fidvid_bsp(bsp_apicid);
189 /* show final fid and vid */
190 msr=rdmsr(0xc0010042);
191 printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
193 printk(BIOS_DEBUG, "Changing FIDVID not supported\n");
196 needs_reset = optimize_link_coherent_ht();
197 needs_reset |= optimize_link_incoherent_ht(sysinfo);
199 printk(BIOS_DEBUG, "needs_reset=0x%x\n", needs_reset);
202 print_info("ht reset -\n");
206 allow_all_aps_stop(bsp_apicid);
208 /* It's the time to set ctrl now; */
209 printk(BIOS_DEBUG, "sysinfo->nodes: %2x sysinfo->ctrl: %p spd_addr: %p\n",
210 sysinfo->nodes, sysinfo->ctrl, spd_addr);
211 fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
212 sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
214 rs780_before_pci_init();
215 sb700_before_pci_init();