2 * This file is part of the coreboot project.
4 * Copyright (C) 2006 Tyan
5 * Copyright (C) 2006 AMD
6 * Written by Yinghai Lu <yinghailu@gmail.com> for Tyan and AMD.
8 * Copyright (C) 2006 MSI
9 * Written by bxshi <bingxunshi@gmail.com> for MSI.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 #include <device/pci_def.h>
29 #include <device/pci_ids.h>
31 #include <device/pnp_def.h>
32 #include <arch/romcc_io.h>
33 #include <cpu/x86/lapic.h>
34 #include <pc80/mc146818rtc.h>
35 #include <console/console.h>
36 #include <cpu/amd/model_fxx_rev.h>
37 #include "southbridge/broadcom/bcm5785/bcm5785_early_smbus.c"
38 #include "southbridge/broadcom/bcm5785/bcm5785_enable_rom.c"
39 #include "northbridge/amd/amdk8/raminit.h"
40 #include "cpu/amd/model_fxx/apic_timer.c"
41 #include "lib/delay.c"
43 #include "cpu/x86/lapic/boot_cpu.c"
44 #include "northbridge/amd/amdk8/reset_test.c"
45 #include "northbridge/amd/amdk8/debug.c"
46 #include "superio/nsc/pc87417/pc87417_early_serial.c"
47 #include "cpu/x86/mtrr/earlymtrr.c"
48 #include "cpu/x86/bist.h"
49 #include "northbridge/amd/amdk8/setup_resource_map.c"
50 #include "southbridge/broadcom/bcm5785/bcm5785_early_setup.c"
52 #define SERIAL_DEV PNP_DEV(0x2e, PC87417_SP1)
53 #define RTC_DEV PNP_DEV(0x2e, PC87417_RTC)
55 static void memreset(int controllers, const struct mem_controller *ctrl)
59 static inline void activate_spd_rom(const struct mem_controller *ctrl)
61 #define SMBUS_SWITCH1 0x70
62 #define SMBUS_SWITCH2 0x72
63 unsigned device = (ctrl->channel0[0]) >> 8;
64 smbus_send_byte(SMBUS_SWITCH1, device & 0x0f);
65 smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f );
69 static inline void change_i2c_mux(unsigned device)
71 #define SMBUS_SWITCH1 0x70
72 #define SMBUS_SWITCH2 0x72
73 smbus_send_byte(SMBUS_SWITCH1, device & 0x0f);
74 smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f );
78 static inline int spd_read_byte(unsigned device, unsigned address)
80 return smbus_read_byte(device, address);
83 #include "northbridge/amd/amdk8/amdk8_f.h"
84 #include "northbridge/amd/amdk8/incoherent_ht.c"
85 #include "northbridge/amd/amdk8/coherent_ht.c"
86 #include "northbridge/amd/amdk8/raminit_f.c"
87 #include "lib/generic_sdram.c"
88 #include "resourcemap.c" /* msi does not want the default */
89 #include "cpu/amd/dualcore/dualcore.c"
91 #include "cpu/amd/car/post_cache_as_ram.c"
92 #include "cpu/amd/model_fxx/init_cpus.c"
93 #include "cpu/amd/model_fxx/fidvid.c"
94 #include "northbridge/amd/amdk8/early_ht.c"
99 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
101 static const uint16_t spd_addr[] = {
103 RC0|DIMM0, RC0|DIMM2, RC0|DIMM4, RC0|DIMM6,
104 RC0|DIMM1, RC0|DIMM3, RC0|DIMM5, RC0|DIMM7,
106 RC1|DIMM0, RC1|DIMM2, RC1|DIMM4, RC1|DIMM6,
107 RC1|DIMM1, RC1|DIMM3, RC1|DIMM5, RC1|DIMM7,
110 struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE +
111 CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
114 unsigned bsp_apicid = 0;
116 if (!cpu_init_detectedx && boot_cpu()) {
117 /* Nothing special needs to be done to find bus 0 */
118 /* Allow the HT devices to be found */
120 enumerate_ht_chain();
122 bcm5785_enable_rom();
124 bcm5785_enable_lpc();
127 pc87417_enable_dev(RTC_DEV);
131 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
136 pc87417_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
140 // dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
142 /* Halt if there was a built in self test failure */
143 report_bist_failure(bist);
145 printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
147 setup_ms9185_resource_map();
149 dump_pci_device(PCI_DEV(0, 0x18, 0));
150 dump_pci_device(PCI_DEV(0, 0x19, 0));
153 print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
155 setup_coherent_ht_domain();
157 wait_all_core0_started();
158 #if CONFIG_LOGICAL_CPUS==1
159 // It is said that we should start core1 after all core0 launched
160 /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
161 * So here need to make sure last core0 is started, esp for two way system,
162 * (there may be apic id conflicts in that case)
165 //bx_a010- wait_all_other_cores_started(bsp_apicid);
168 /* it will set up chains and store link pair for optimization later */
169 ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
171 bcm5785_early_setup();
174 //it your CPU min fid is 1G, you can change HT to 1G and FID to max one time.
175 needs_reset = optimize_link_coherent_ht();
176 needs_reset |= optimize_link_incoherent_ht(sysinfo);
179 #if CONFIG_SET_FIDVID
183 msr=rdmsr(0xc0010042);
184 print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
190 enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
192 init_fidvid_bsp(bsp_apicid);
194 // show final fid and vid
197 msr=rdmsr(0xc0010042);
198 print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
204 needs_reset = optimize_link_coherent_ht();
205 needs_reset |= optimize_link_incoherent_ht(sysinfo);
207 // fidvid change will issue one LDTSTOP and the HT change will be effective too
209 print_info("ht reset -\n");
213 allow_all_aps_stop(bsp_apicid);
215 //It's the time to set ctrl in sysinfo now;
216 fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
223 activate_spd_rom(sysinfo->ctrl+i);
224 dump_smbus_registers();
230 for(i=1;i<256;i<<=1) {
232 dump_smbus_registers();
236 //do we need apci timer, tsc...., only debug need it for better output
237 /* all ap stopped? */
238 // init_timer(); // Need to use TMICT to synconize FID/VID
240 sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
247 // dump_pci_devices();
248 dump_pci_device_index_wait(PCI_DEV(0, 0x18, 2), 0x98);
249 dump_pci_device_index_wait(PCI_DEV(0, 0x19, 2), 0x98);