3 #include <device/pci_def.h>
5 #include <device/pnp_def.h>
6 #include <arch/romcc_io.h>
7 #include <cpu/x86/lapic.h>
8 #include <pc80/mc146818rtc.h>
9 #include <console/console.h>
11 #include <cpu/amd/model_fxx_rev.h>
12 #include "northbridge/amd/amdk8/incoherent_ht.c"
13 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
14 #include "northbridge/amd/amdk8/raminit.h"
15 #include "cpu/amd/model_fxx/apic_timer.c"
16 #include "lib/delay.c"
17 #include "cpu/x86/lapic/boot_cpu.c"
18 #include "northbridge/amd/amdk8/reset_test.c"
19 #include "northbridge/amd/amdk8/debug.c"
20 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
21 #include "cpu/x86/mtrr/earlymtrr.c"
22 #include "cpu/x86/bist.h"
23 #include "northbridge/amd/amdk8/setup_resource_map.c"
24 #include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
26 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
28 static void memreset_setup(void)
30 if (is_cpu_pre_c0()) {
31 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0
34 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1
36 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
39 static void memreset(int controllers, const struct mem_controller *ctrl)
41 if (is_cpu_pre_c0()) {
43 outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
47 static inline void activate_spd_rom(const struct mem_controller *ctrl)
49 #define SMBUS_HUB 0x18
51 unsigned device=(ctrl->channel0[0])>>8;
52 /* the very first write always get COL_STS=1 and ABRT_STS=1, so try another time*/
55 ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
56 } while ((ret!=0) && (i-->0));
58 smbus_write_byte(SMBUS_HUB, 0x03, 0);
61 static inline void change_i2c_mux(unsigned device)
63 #define SMBUS_HUB 0x18
65 print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\n");
68 ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
69 print_debug("change_i2c_mux 1 ret="); print_debug_hex32(ret); print_debug("\n");
70 } while ((ret!=0) && (i-->0));
71 ret = smbus_write_byte(SMBUS_HUB, 0x03, 0);
72 print_debug("change_i2c_mux 2 ret="); print_debug_hex32(ret); print_debug("\n");
76 static inline int spd_read_byte(unsigned device, unsigned address)
78 return smbus_read_byte(device, address);
81 #include "northbridge/amd/amdk8/raminit.c"
82 #include "northbridge/amd/amdk8/coherent_ht.c"
83 #include "lib/generic_sdram.c"
84 #include "resourcemap.c" /* tyan does not want the default */
85 #include "cpu/amd/dualcore/dualcore.c"
87 #include "cpu/amd/car/post_cache_as_ram.c"
88 #include "cpu/amd/model_fxx/init_cpus.c"
89 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
90 #include "northbridge/amd/amdk8/early_ht.c"
92 #define RC0 ((1<<2)<<8)
93 #define RC1 ((1<<1)<<8)
94 #define RC2 ((1<<4)<<8)
95 #define RC3 ((1<<3)<<8)
97 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
99 static const uint16_t spd_addr [] = {
100 RC0|DIMM0, RC0|DIMM2, 0, 0,
101 RC0|DIMM1, RC0|DIMM3, 0, 0,
102 #if CONFIG_MAX_PHYSICAL_CPUS > 1
103 RC1|DIMM0, RC1|DIMM2, 0, 0,
104 RC1|DIMM1, RC1|DIMM3, 0, 0,
106 #if CONFIG_MAX_PHYSICAL_CPUS > 2
107 RC2|DIMM0, RC2|DIMM2, 0, 0,
108 RC2|DIMM1, RC2|DIMM3, 0, 0,
109 RC3|DIMM0, RC3|DIMM2, 0, 0,
110 RC3|DIMM1, RC3|DIMM3, 0, 0,
115 unsigned bsp_apicid = 0;
117 struct mem_controller ctrl[8];
120 if (!cpu_init_detectedx && boot_cpu()) {
121 /* Nothing special needs to be done to find bus 0 */
122 /* Allow the HT devices to be found */
124 enumerate_ht_chain();
126 amd8111_enable_rom();
130 bsp_apicid = init_cpus(cpu_init_detectedx);
134 w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
138 /* Halt if there was a built in self test failure */
139 report_bist_failure(bist);
141 setup_s4882_resource_map();
143 needs_reset = setup_coherent_ht_domain();
145 wait_all_core0_started();
146 #if CONFIG_LOGICAL_CPUS==1
147 // It is said that we should start core1 after all core0 launched
149 wait_all_other_cores_started(bsp_apicid);
152 // automatically set that for you, but you might meet tight space
153 needs_reset |= ht_setup_chains_x();
156 print_info("ht reset -\n");
160 allow_all_aps_stop(bsp_apicid);
163 //It's the time to set ctrl now;
164 fill_mem_ctrl(nodes, ctrl, spd_addr);
169 sdram_initialize(nodes, ctrl);