1 #if CONFIG_K8_REV_F_SUPPORT == 1
2 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
7 #include <device/pci_def.h>
8 #include <device/pci_ids.h>
10 #include <device/pnp_def.h>
11 #include <arch/romcc_io.h>
12 #include <cpu/x86/lapic.h>
13 #include <pc80/mc146818rtc.h>
14 #include <console/console.h>
15 #include <cpu/amd/model_fxx_rev.h>
16 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
17 #include "northbridge/amd/amdk8/raminit.h"
18 #include "cpu/amd/model_fxx/apic_timer.c"
19 #include "cpu/x86/lapic/boot_cpu.c"
20 #include "northbridge/amd/amdk8/reset_test.c"
21 #include "cpu/x86/bist.h"
22 #include "lib/delay.c"
23 #include "northbridge/amd/amdk8/debug.c"
24 #include "cpu/x86/mtrr/earlymtrr.c"
25 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
26 #include "northbridge/amd/amdk8/setup_resource_map.c"
27 #include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
29 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
32 * GPIO28 of 8111 will control H0_MEMRESET_L
33 * GPIO29 of 8111 will control H1_MEMRESET_L
35 static void memreset_setup(void)
37 if (is_cpu_pre_c0()) {
38 /* Set the memreset low */
39 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
40 /* Ensure the BIOS has control of the memory lines */
41 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
43 /* Ensure the CPU has controll of the memory lines */
44 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
48 static void memreset(int controllers, const struct mem_controller *ctrl)
50 if (is_cpu_pre_c0()) {
52 /* Set memreset_high */
53 outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
58 static inline void activate_spd_rom(const struct mem_controller *ctrl)
62 static inline int spd_read_byte(unsigned device, unsigned address)
64 return smbus_read_byte(device, address);
67 #include "northbridge/amd/amdk8/amdk8.h"
68 #include "northbridge/amd/amdk8/incoherent_ht.c"
69 #include "northbridge/amd/amdk8/coherent_ht.c"
70 #include "northbridge/amd/amdk8/raminit.c"
71 #include "lib/generic_sdram.c"
72 #include "northbridge/amd/amdk8/resourcemap.c" /* tyan does not want the default */
73 #include "cpu/amd/dualcore/dualcore.c"
75 #include "cpu/amd/car/post_cache_as_ram.c"
76 #include "cpu/amd/model_fxx/init_cpus.c"
77 #include "cpu/amd/model_fxx/fidvid.c"
78 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
79 #include "northbridge/amd/amdk8/early_ht.c"
81 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
83 static const uint16_t spd_addr[] = {
93 struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
94 + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
97 unsigned bsp_apicid = 0;
99 if (!cpu_init_detectedx && boot_cpu()) {
100 /* Nothing special needs to be done to find bus 0 */
101 /* Allow the HT devices to be found */
103 enumerate_ht_chain();
105 /* Setup the rom access for 4M */
106 amd8111_enable_rom();
110 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
113 w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
117 /* Halt if there was a built in self test failure */
118 report_bist_failure(bist);
120 printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
122 setup_default_resource_map();
124 print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
126 #if CONFIG_MEM_TRAIN_SEQ == 1
127 set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
129 setup_coherent_ht_domain(); // routing table and start other core0
131 wait_all_core0_started();
132 #if CONFIG_LOGICAL_CPUS==1
133 // It is said that we should start core1 after all core0 launched
134 /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
135 * So here need to make sure last core0 is started, esp for two way system,
136 * (there may be apic id conflicts in that case)
139 wait_all_other_cores_started(bsp_apicid);
142 /* it will set up chains and store link pair for optimization later */
143 ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
145 #if CONFIG_SET_FIDVID
149 msr=rdmsr(0xc0010042);
150 print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
156 enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
158 init_fidvid_bsp(bsp_apicid);
160 // show final fid and vid
163 msr=rdmsr(0xc0010042);
164 print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
169 needs_reset = optimize_link_coherent_ht();
170 needs_reset |= optimize_link_incoherent_ht(sysinfo);
172 // fidvid change will issue one LDTSTOP and the HT change will be effective too
174 print_info("ht reset -\n");
175 soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn);
178 allow_all_aps_stop(bsp_apicid);
180 //It's the time to set ctrl in sysinfo now;
181 fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
186 dump_smbus_registers();
191 //do we need apci timer, tsc...., only debug need it for better output
192 /* all ap stopped? */
193 init_timer(); // Need to use TMICT to synconize FID/VID
194 sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
200 post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now