2 * This file is part of the coreboot project.
4 * Copyright (C) 2006 AMD
5 * (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
6 * Copyright (C) 2006 MSI
7 * (Written by Bingxun Shi <bingxunshi@gmail.com> for MSI)
8 * Copyright (C) 2008 Rudolf Marek <r.marek@assembler.cz>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
25 unsigned int get_sbdn(unsigned bus);
27 #if CONFIG_K8_REV_F_SUPPORT == 1
28 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
33 #include <device/pci_def.h>
35 #include <device/pnp_def.h>
36 #include <arch/romcc_io.h>
37 #include <cpu/amd/mtrr.h>
38 #include <cpu/x86/lapic.h>
39 #include <pc80/mc146818rtc.h>
40 #include <console/console.h>
41 #include <cpu/amd/model_fxx_rev.h>
42 #include "northbridge/amd/amdk8/raminit.h"
43 #include "cpu/amd/model_fxx/apic_timer.c"
44 #include "lib/delay.c"
45 #include "northbridge/amd/amdk8/reset_test.c"
46 #include "northbridge/amd/amdk8/debug.c"
47 #include "superio/ite/it8712f/it8712f_early_serial.c"
48 #include "southbridge/via/vt8237r/vt8237r_early_smbus.c"
49 #include "cpu/x86/mtrr/earlymtrr.c"
50 #include "cpu/x86/bist.h"
51 #include "northbridge/amd/amdk8/setup_resource_map.c"
54 #define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
55 #define WATCHDOG_DEV PNP_DEV(0x2e, IT8712F_GPIO)
57 #define IT8712F_GPIO_BASE 0x0a20
59 static void memreset(int controllers, const struct mem_controller *ctrl) { }
60 static void activate_spd_rom(const struct mem_controller *ctrl) { }
62 static inline int spd_read_byte(unsigned device, unsigned address)
64 return smbus_read_byte(device, address);
67 // defines S3_NVRAM_EARLY:
68 #include "southbridge/via/k8t890/k8t890_early_car.c"
69 #include "northbridge/amd/amdk8/amdk8.h"
70 #include "northbridge/amd/amdk8/incoherent_ht.c"
71 #include "northbridge/amd/amdk8/coherent_ht.c"
72 #include "northbridge/amd/amdk8/raminit_f.c"
73 #include "lib/generic_sdram.c"
74 #include "cpu/amd/dualcore/dualcore.c"
75 #include "cpu/amd/car/post_cache_as_ram.c"
76 #include "cpu/amd/model_fxx/init_cpus.c"
77 #include "cpu/amd/model_fxx/fidvid.c"
78 #include "northbridge/amd/amdk8/resourcemap.c"
85 print_debug("soft reset\n");
88 tmp = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x4f);
90 /* FIXME from S3 set bit1 to disable USB reset VT8237A/S */
91 pci_write_config8(PCI_DEV(0, 0x11, 0), 0x4f, tmp);
99 unsigned int get_sbdn(unsigned bus)
103 dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA,
104 PCI_DEVICE_ID_VIA_VT8237R_LPC), bus);
105 return (dev >> 15) & 0x1f;
108 struct gpio_init_val {
113 static const struct gpio_init_val gpio_init_data[] = {
114 /* multi-function pin selection */
116 { 0x28, 0x00 }, /* gp46 is infrared receive input */
117 { 0x29, 0x40 }, /* reserved value?!? */
119 { 0x2c, 0x1d }, /* pin91 is VIN7 instead of PCIRSTIN# */
120 /* gpio i/o port base */
121 { 0x62, IT8712F_GPIO_BASE >> 8 },
122 { 0x63, IT8712F_GPIO_BASE & 0xff },
123 /* 0xb8 - 0xbc: gpio pull-up enable */
125 /* 0xc0 - 0xc4: gpio alternate function select */
129 /* 0xc8 - 0xcc: gpio output enable */
137 static void m2v_it8712f_gpio_init(void)
139 const struct gpio_init_val *giv;
141 printk(BIOS_SPEW, "it8712f gpio init...\n");
144 * it8712f gpio config
146 * Most importantly this switches pin 91 from
148 * Note that only PCIRST3# and PCIRST5# are affected
149 * by PCIRSTIN#, the PCIRST1#, PCIRST2#, PCIRST4# are always
150 * direct buffers of #LRESET (low pin count bus reset).
151 * If this is not done All PCIRST are in reset state and the
152 * pcie slots don't initialize.
154 * pci reset handling:
155 * pin 91: VIN7 (alternate PCIRSTIN#)
156 * pin 48: PCIRST5# / gpio port 5 bit 0
157 * pin 84: PCIRST4# / gpio port 1 bit 0
158 * pin 31: PCIRST1# / gpio port 1 bit 4
159 * pin 33: PCIRST2# / gpio port 1 bit 2
160 * pin 34: PCIRST3# / gpio port 1 bit 1
162 * PCIRST[0-5]# are connected as follows:
163 * pcirst1# -> pci bus
164 * pcirst2# -> ide bus
165 * pcirst3# -> pcie devices
166 * pcirst4# -> pcie graphics
167 * pcirst5# -> maybe n/c (untested)
169 * For software control of PCIRST[1-5]#:
170 * 0x2a=0x17 (deselect pcirst# hardwiring, enable 0x25 control)
171 * 0x25=0x17 (select gpio function)
172 * 0xc0=0x17, 0xc8=0x17 gpio port 1 select & output enable
173 * 0xc4=0xc1, 0xcc=0xc1 gpio port 5 select & output enable
175 it8712f_enter_conf();
176 giv = gpio_init_data;
178 printk(BIOS_SPEW, "it8712f gpio: %02x=%02x\n",
179 giv->addr, giv->val);
180 it8712f_sio_write(IT8712F_GPIO, giv->addr, giv->val);
185 printk(BIOS_INFO, "it8712f gpio: Setting DDR2 voltage to 1.80V\n");
187 * upper two bits of gpio_base+4 control ddr2 voltage:
193 * The lower six bits are inputs and normally read back as 1
194 * (except bit 2, which seems rather random).
196 outb(0xff, IT8712F_GPIO_BASE+4);
199 static void m2v_bus_init(void)
203 printk(BIOS_SPEW, "m2v_bus_init\n");
205 dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
206 PCI_DEVICE_ID_VIA_K8T890CF_0), 0);
207 pci_write_config8(dev, K8T890_MULTIPLE_FN_EN, 0x01);
209 dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
210 PCI_DEVICE_ID_VIA_K8T890CF_5), 0);
213 * 6 | 0: hide scratch register function 0:0.6 (we don't use it)
214 * 5 | 1: enable pcie bridge 0:2.0
215 * 4 | 0: hide pcie bridge 0:3.3 (not connected)
216 * 3 | 1: enable pcie bridge 0:3.2
217 * 2 | 1: enable pcie bridge 0:3.1
218 * 1 | 1: enable pcie bridge 0:3.0
220 pci_write_config8(dev, 0xf0, 0x2e);
223 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
225 static const uint16_t spd_addr[] = {
233 unsigned bsp_apicid = 0;
235 struct sys_info *sysinfo =
236 (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
238 it8712f_24mhz_clkin();
239 it8712f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
240 it8712f_kill_watchdog();
245 m2v_it8712f_gpio_init();
247 printk(BIOS_INFO, "now booting... \n");
250 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
252 /* Halt if there was a built in self test failure. */
253 report_bist_failure(bist);
254 setup_default_resource_map();
255 setup_coherent_ht_domain();
256 wait_all_core0_started();
258 printk(BIOS_INFO, "now booting... All core 0 started\n");
260 #if CONFIG_LOGICAL_CPUS==1
261 /* It is said that we should start core1 after all core0 launched. */
263 wait_all_other_cores_started(bsp_apicid);
266 ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. */
268 needs_reset = optimize_link_coherent_ht();
269 print_debug_hex8(needs_reset);
270 needs_reset |= optimize_link_incoherent_ht(sysinfo);
271 print_debug_hex8(needs_reset);
272 needs_reset |= k8t890_early_setup_ht();
273 print_debug_hex8(needs_reset);
276 printk(BIOS_DEBUG, "ht reset -\n");
278 printk(BIOS_DEBUG, "FAILED!\n");
281 /* the HT settings needs to be OK, because link freq chnage may cause HT disconnect */
282 /* allow LDT STOP asserts */
283 vt8237_sb_enable_fid_vid();
286 print_debug("after enable_fid_change\n");
288 init_fidvid_bsp(bsp_apicid);
290 /* Stop the APs so we can start them later in init. */
291 allow_all_aps_stop(bsp_apicid);
293 /* It's the time to set ctrl now. */
294 fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
296 sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);