3 #include <device/pci_def.h>
5 #include <device/pnp_def.h>
6 #include <arch/romcc_io.h>
7 #include <cpu/x86/lapic.h>
8 #include <pc80/mc146818rtc.h>
9 #include <console/console.h>
12 #include <cpu/amd/model_fxx_rev.h>
13 #include "northbridge/amd/amdk8/incoherent_ht.c"
14 #include "southbridge/nvidia/ck804/ck804_early_smbus.h"
15 #include "northbridge/amd/amdk8/raminit.h"
16 #include "cpu/amd/model_fxx/apic_timer.c"
17 #include "lib/delay.c"
18 #include "cpu/x86/lapic/boot_cpu.c"
19 #include "northbridge/amd/amdk8/reset_test.c"
20 #include "northbridge/amd/amdk8/debug.c"
21 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
22 #include "cpu/x86/mtrr/earlymtrr.c"
23 #include "cpu/x86/bist.h"
24 #include "northbridge/amd/amdk8/setup_resource_map.c"
26 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
28 static void memreset_setup(void)
32 static void memreset(int controllers, const struct mem_controller *ctrl)
36 static inline void activate_spd_rom(const struct mem_controller *ctrl)
41 static inline int spd_read_byte(unsigned device, unsigned address)
43 return smbus_read_byte(device, address);
46 #include "northbridge/amd/amdk8/raminit.c"
47 #include "northbridge/amd/amdk8/coherent_ht.c"
48 #include "lib/generic_sdram.c"
49 #include "resourcemap.c" /* tyan does not want the default */
50 #include "cpu/amd/dualcore/dualcore.c"
51 #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
52 #include "southbridge/nvidia/ck804/ck804_early_setup.c"
53 #include "cpu/amd/car/post_cache_as_ram.c"
54 #include "cpu/amd/model_fxx/init_cpus.c"
55 #include "northbridge/amd/amdk8/early_ht.c"
57 static void sio_setup(void)
63 byte = pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
65 pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte);
67 /* LPC Positive Decode 0 */
68 dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0);
69 /* Serial 0, Serial 1 */
70 dword |= (1<<0) | (1<<1);
71 pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
74 /* s2891 has onboard LPC port 80 */
75 /*Hope I can enable port 80 here
76 It will decode port 80 to LPC, If you are using PCI post code you can not do this */
77 dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa4);
79 pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa4, dword);
83 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
85 static const uint16_t spd_addr [] = {
88 #if CONFIG_MAX_PHYSICAL_CPUS > 1
95 unsigned bsp_apicid = 0;
97 struct mem_controller ctrl[8];
100 if (!cpu_init_detectedx && boot_cpu()) {
101 /* Nothing special needs to be done to find bus 0 */
102 /* Allow the HT devices to be found */
104 enumerate_ht_chain();
110 bsp_apicid = init_cpus(cpu_init_detectedx);
115 w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
119 /* Halt if there was a built in self test failure */
120 report_bist_failure(bist);
122 setup_s2891_resource_map();
124 dump_pci_device(PCI_DEV(0, 0x18, 0));
125 dump_pci_device(PCI_DEV(0, 0x19, 0));
128 needs_reset = setup_coherent_ht_domain();
130 wait_all_core0_started();
131 #if CONFIG_LOGICAL_CPUS==1
132 // It is said that we should start core1 after all core0 launched
134 wait_all_other_cores_started(bsp_apicid);
137 needs_reset |= ht_setup_chains_x();
139 needs_reset |= ck804_early_setup_x();
142 printk(BIOS_INFO, "ht reset -\n");
146 allow_all_aps_stop(bsp_apicid);
149 //It's the time to set ctrl now;
150 fill_mem_ctrl(nodes, ctrl, spd_addr);
154 dump_spd_registers(&cpu[0]);
157 dump_smbus_registers();
161 sdram_initialize(nodes, ctrl);