src/mainboard/tyan/s2892/romstage.c

   1 #include <stdint.h>
   2 #include <string.h>
   3 #include <device/pci_def.h>
   4 #include <arch/io.h>
   5 #include <device/pnp_def.h>
   6 #include <arch/romcc_io.h>
   7 #include <cpu/x86/lapic.h>
   8 #include <pc80/mc146818rtc.h>
   9 #include <console/console.h>
  10 #include <lib.h>
  11 #include <spd.h>
  12 #include <cpu/amd/model_fxx_rev.h>
  13 #include "northbridge/amd/amdk8/incoherent_ht.c"
  14 #include "southbridge/nvidia/ck804/ck804_early_smbus.h"
  15 #include "northbridge/amd/amdk8/raminit.h"
  16 #include "cpu/amd/model_fxx/apic_timer.c"
  17 #include "lib/delay.c"
  18 #include "cpu/x86/lapic/boot_cpu.c"
  19 #include "northbridge/amd/amdk8/reset_test.c"
  20 #include "northbridge/amd/amdk8/debug.c"
  21 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  22 #include "cpu/x86/mtrr/earlymtrr.c"
  23 #include "cpu/x86/bist.h"
  24 #include "northbridge/amd/amdk8/setup_resource_map.c"
  25
  26 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  27
  28 static void memreset(int controllers, const struct mem_controller *ctrl) { }
  29 static void activate_spd_rom(const struct mem_controller *ctrl) { }
  30
  31 static inline int spd_read_byte(unsigned device, unsigned address)
  32 {
  33         return smbus_read_byte(device, address);
  34 }
  35
  36 #include "northbridge/amd/amdk8/raminit.c"
  37 #include "northbridge/amd/amdk8/coherent_ht.c"
  38 #include "lib/generic_sdram.c"
  39 #include "resourcemap.c"
  40 #include "cpu/amd/dualcore/dualcore.c"
  41 #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
  42
  43 //set GPIO to input mode
  44 #define CK804_MB_SETUP \
  45         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXA_PRSNT2_L*/ \
  46         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/ \
  47         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/ \
  48         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/ \
  49
  50 #include "southbridge/nvidia/ck804/ck804_early_setup_car.c"
  51 #include "cpu/amd/car/post_cache_as_ram.c"
  52 #include "cpu/amd/model_fxx/init_cpus.c"
  53 #include "northbridge/amd/amdk8/early_ht.c"
  54
  55 static void sio_setup(void)
  56 {
  57         uint32_t dword;
  58         uint8_t byte;
  59
  60         byte = pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
  61         byte |= 0x20;
  62         pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte);
  63
  64         dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0);
  65         dword |= (1<<0);
  66         pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
  67 }
  68
  69 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
  70 {
  71         static const uint16_t spd_addr [] = {
  72                 DIMM0, DIMM2, 0, 0,
  73                 DIMM1, DIMM3, 0, 0,
  74 #if CONFIG_MAX_PHYSICAL_CPUS > 1
  75                 DIMM4, DIMM6, 0, 0,
  76                 DIMM5, DIMM7, 0, 0,
  77 #endif
  78         };
  79
  80         int needs_reset;
  81         unsigned bsp_apicid = 0, nodes;
  82         struct mem_controller ctrl[8];
  83
  84         if (!cpu_init_detectedx && boot_cpu()) {
  85                 /* Nothing special needs to be done to find bus 0 */
  86                 /* Allow the HT devices to be found */
  87                 enumerate_ht_chain();
  88                 sio_setup();
  89         }
  90
  91         if (bist == 0)
  92                 bsp_apicid = init_cpus(cpu_init_detectedx);
  93
  94 //      post_code(0x32);
  95
  96         w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
  97         uart_init();
  98         console_init();
  99
 100         /* Halt if there was a built in self test failure */
 101         report_bist_failure(bist);
 102
 103         setup_mb_resource_map();
 104
 105         needs_reset = setup_coherent_ht_domain();
 106
 107         wait_all_core0_started();
 108 #if CONFIG_LOGICAL_CPUS==1
 109         // It is said that we should start core1 after all core0 launched
 110         start_other_cores();
 111         wait_all_other_cores_started(bsp_apicid);
 112 #endif
 113
 114         needs_reset |= ht_setup_chains_x();
 115         needs_reset |= ck804_early_setup_x();
 116         if (needs_reset) {
 117                 printk(BIOS_INFO, "ht reset -\n");
 118                 soft_reset();
 119         }
 120
 121         allow_all_aps_stop(bsp_apicid);
 122
 123         nodes = get_nodes();
 124         //It's the time to set ctrl now;
 125         fill_mem_ctrl(nodes, ctrl, spd_addr);
 126
 127         enable_smbus();
 128
 129         sdram_initialize(nodes, ctrl);
 130
 131         post_cache_as_ram();
 132 }