2 * This file is part of the coreboot project.
4 * Copyright (C) 2008-2010 Joseph Smith <joe@settoplinux.org>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
23 #include <device/pci_def.h>
25 #include <device/pnp_def.h>
26 #include <arch/romcc_io.h>
28 #include <arch/llshell.h>
29 #include "pc80/udelay_io.c"
30 #include <console/console.h>
32 #include "superio/smsc/smscsuperio/smscsuperio_early_serial.c"
33 #include "northbridge/intel/i82830/raminit.h"
34 #include "northbridge/intel/i82830/memory_initialized.c"
35 #include "southbridge/intel/i82801dx/i82801dx.h"
36 #include "southbridge/intel/i82801dx/i82801dx_reset.c"
37 #include "cpu/x86/bist.h"
38 #include "spd_table.h"
40 #include "southbridge/intel/i82801dx/i82801dx_early_smbus.c"
41 #include "southbridge/intel/i82801dx/i82801dx_tco_timer.c"
43 #define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1)
46 * The onboard 64MB PC133 memory does not have a SPD EEPROM so the
47 * values have to be set manually, the SO-DIMM socket is located in
48 * socket0 (0x50/DIMM0), and the onboard memory is located in socket1
51 static inline int spd_read_byte(unsigned device, unsigned address)
55 if (device == DIMM0) {
56 return smbus_read_byte(device, address);
57 } else if (device == DIMM1) {
58 for (i = 0; i < ARRAY_SIZE(spd_table); i++) {
59 if (spd_table[i].address == address)
60 return spd_table[i].data;
62 return 0xFF; /* Return 0xFF when address is not found. */
64 return 0xFF; /* Return 0xFF on any failures. */
68 #include "northbridge/intel/i82830/raminit.c"
71 * Setup mainboard specific registers pre raminit.
73 static void mb_early_setup(void)
75 /* - Hub Interface to PCI Bridge Registers - */
76 /* 12-Clock Retry Enable */
77 pci_write_config16(PCI_DEV(0, 0x1e, 0), 0x50, 0x1402);
78 /* Master Latency Timer Count */
79 pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20);
80 /* I/O Address Base */
81 pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1c, 0xf0);
83 /* - LPC Interface Bridge Registers - */
84 /* Delayed Transaction Enable */
85 pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xd0, 0x00000002);
86 /* Disable the TCO Timer system reboot feature */
87 pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xd4, 0x02);
88 /* CPU Frequency Strap */
89 pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xd5, 0x02);
90 /* ACPI base address and enable Resource Indicator */
91 pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, (PMBASE_ADDR | 1));
92 /* Enable the SMBUS */
95 pci_write_config8(PCI_DEV(0, 0x1f, 0), ACPI_CNTL, 0x10);
98 void main(unsigned long bist)
101 if (memory_initialized())
105 /* Set southbridge and superio gpios */
108 smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
112 /* Halt if there was a built in self test failure. */
113 report_bist_failure(bist);
115 /* disable TCO timers */
116 i82801dx_halt_tco_timer();
118 /* Setup mainboard specific registers */
121 /* Initialize memory */
128 /* ram_check(0, 640 * 1024); */
129 /* ram_check(64512 * 1024, 65536 * 1024); */