src/mainboard/hp/dl145_g3/romstage.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2006 Tyan
   5  * Copyright (C) 2006 AMD
   6  * Written by Yinghai Lu <yinghailu@gmail.com> for Tyan and AMD.
   7  *
   8  * Copyright (C) 2007 University of Mannheim
   9  * Written by Philipp Degler <pdegler@rumms.uni-mannheim.de> for University of Mannheim
  10  * Copyright (C) 2009 University of Heidelberg
  11  * Written by Mondrian Nuessle <nuessle@uni-heidelberg.de> for University of Heidelberg
  12  *
  13  * This program is free software; you can redistribute it and/or modify
  14  * it under the terms of the GNU General Public License as published by
  15  * the Free Software Foundation; either version 2 of the License, or
  16  * (at your option) any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  * GNU General Public License for more details.
  22  *
  23  * You should have received a copy of the GNU General Public License
  24  * along with this program; if not, write to the Free Software
  25  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  26  */
  27
  28 #if CONFIG_K8_REV_F_SUPPORT == 1
  29 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
  30 #endif
  31
  32 #include <stdint.h>
  33 #include <string.h>
  34 #include <device/pci_def.h>
  35 #include <device/pci_ids.h>
  36 #include <arch/io.h>
  37 #include <device/pnp_def.h>
  38 #include <arch/romcc_io.h>
  39 #include <cpu/x86/lapic.h>
  40 #include <pc80/mc146818rtc.h>
  41 #include <console/console.h>
  42 #include <cpu/amd/model_fxx_rev.h>
  43 #include "southbridge/broadcom/bcm5785/bcm5785_early_smbus.c"
  44 #include "southbridge/broadcom/bcm5785/bcm5785_enable_rom.c"
  45 #include "northbridge/amd/amdk8/raminit.h"
  46 #include "cpu/amd/model_fxx/apic_timer.c"
  47 #include "lib/delay.c"
  48 #include "cpu/x86/lapic/boot_cpu.c"
  49 #include "northbridge/amd/amdk8/reset_test.c"
  50 #include "superio/serverengines/pilot/pilot_early_serial.c"
  51 #include "superio/serverengines/pilot/pilot_early_init.c"
  52 #include "superio/nsc/pc87417/pc87417_early_serial.c"
  53 #include "cpu/x86/bist.h"
  54 #include "northbridge/amd/amdk8/debug.c"
  55 #include "cpu/x86/mtrr/earlymtrr.c"
  56 #include "northbridge/amd/amdk8/setup_resource_map.c"
  57 #include "southbridge/broadcom/bcm5785/bcm5785_early_setup.c"
  58
  59 #define SERIAL_DEV PNP_DEV(0x2e, PILOT_SP1)
  60 #define RTC_DEV PNP_DEV(0x4e, PC87417_RTC)
  61
  62 static void memreset(int controllers, const struct mem_controller *ctrl) { }
  63
  64 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  65 {
  66 #define SMBUS_SWITCH1 0x70
  67 #define SMBUS_SWITCH2 0x72
  68          unsigned device = (ctrl->channel0[0]) >> 8;
  69          smbus_send_byte(SMBUS_SWITCH1, device & 0x0f);
  70          smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f );
  71 }
  72
  73 static inline int spd_read_byte(unsigned device, unsigned address)
  74 {
  75          return smbus_read_byte(device, address);
  76 }
  77
  78 #include "northbridge/amd/amdk8/amdk8_f.h"
  79 #include "northbridge/amd/amdk8/incoherent_ht.c"
  80 #include "northbridge/amd/amdk8/coherent_ht.c"
  81 #include "northbridge/amd/amdk8/raminit_f.c"
  82 #include "lib/generic_sdram.c"
  83 #include <spd.h>
  84 #include "cpu/amd/dualcore/dualcore.c"
  85 #include "cpu/amd/car/post_cache_as_ram.c"
  86 #include "cpu/amd/model_fxx/init_cpus.c"
  87 #include "cpu/amd/model_fxx/fidvid.c"
  88 #include "northbridge/amd/amdk8/early_ht.c"
  89
  90 #if 0
  91 #include "ipmi.c"
  92
  93 static void setup_early_ipmi_serial()
  94 {
  95         unsigned char result;
  96         char channel_access[]={0x06<<2,0x40,0x04,0x80,0x05};
  97         char serialmodem_conf[]={0x0c<<2,0x10,0x04,0x08,0x00,0x0f};
  98         char serial_mux1[]={0x0c<<2,0x12,0x04,0x06};
  99         char serial_mux2[]={0x0c<<2,0x12,0x04,0x03};
 100         char serial_mux3[]={0x0c<<2,0x12,0x04,0x07};
 101
 102 //      earlydbg(0x0d);
 103         //set channel access system only
 104         ipmi_request(5,channel_access);
 105 //      earlydbg(result);
 106 /*
 107         //Set serial/modem config
 108         result=ipmi_request(6,serialmodem_conf);
 109         earlydbg(result);
 110
 111         //Set serial mux 1
 112         result=ipmi_request(4,serial_mux1);
 113         earlydbg(result);
 114
 115         //Set serial mux 2
 116         result=ipmi_request(4,serial_mux2);
 117         earlydbg(result);
 118
 119         //Set serial mux 3
 120         result=ipmi_request(4,serial_mux3);
 121         earlydbg(result);
 122 */
 123 //      earlydbg(0x0e);
 124
 125 }
 126 #endif
 127
 128 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 129 {
 130         static const uint16_t spd_addr[] = {
 131                 // first node
 132                 DIMM0, DIMM2, 0, 0,
 133                 DIMM1, DIMM3, 0, 0,
 134                 // second node
 135                 DIMM4, DIMM6, 0, 0,
 136                 DIMM5, DIMM7, 0, 0,
 137         };
 138
 139         struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
 140                 + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 141         int needs_reset;
 142         unsigned bsp_apicid = 0;
 143
 144         if (!cpu_init_detectedx && boot_cpu()) {
 145                 /* Nothing special needs to be done to find bus 0 */
 146                 /* Allow the HT devices to be found */
 147                 enumerate_ht_chain();
 148                 bcm5785_enable_rom();
 149                 bcm5785_enable_lpc();
 150                 pc87417_enable_dev(RTC_DEV); /* Enable RTC */
 151         }
 152
 153         if (bist == 0)
 154                 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 155
 156         pilot_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 157
 158         uart_init();
 159
 160         /* Halt if there was a built in self test failure */
 161         report_bist_failure(bist);
 162
 163         console_init();
 164 //      setup_early_ipmi_serial();
 165         pilot_early_init(SERIAL_DEV); //config port is being taken from SERIAL_DEV
 166         printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
 167         printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid);
 168
 169 #if CONFIG_MEM_TRAIN_SEQ == 1
 170         set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
 171 #endif
 172         setup_coherent_ht_domain();
 173
 174         wait_all_core0_started();
 175 #if CONFIG_LOGICAL_CPUS==1
 176         // It is said that we should start core1 after all core0 launched
 177         /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
 178          * So here need to make sure last core0 is started, esp for two way system,
 179          * (there may be apic id conflicts in that case)
 180         */
 181         start_other_cores();
 182         wait_all_other_cores_started(bsp_apicid);
 183 #endif
 184
 185         /* it will set up chains and store link pair for optimization later */
 186         ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
 187         bcm5785_early_setup();
 188
 189 #if CONFIG_SET_FIDVID
 190         {
 191                 msr_t msr;
 192                 msr=rdmsr(0xc0010042);
 193                 printk(BIOS_DEBUG, "begin msr fid, vid %08x %08x\n", msr.hi, msr.lo);
 194         }
 195         enable_fid_change();
 196         enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
 197         init_fidvid_bsp(bsp_apicid);
 198         // show final fid and vid
 199         {
 200                 msr_t msr;
 201                 msr=rdmsr(0xc0010042);
 202                 printk(BIOS_DEBUG, "end msr fid, vid %08x %08x\n", msr.hi, msr.lo);
 203         }
 204 #endif
 205
 206         needs_reset = optimize_link_coherent_ht();
 207         needs_reset |= optimize_link_incoherent_ht(sysinfo);
 208
 209         // fidvid change will issue one LDTSTOP and the HT change will be effective too
 210         if (needs_reset) {
 211                 printk(BIOS_INFO, "ht reset -\n");
 212                 soft_reset();
 213         }
 214
 215         allow_all_aps_stop(bsp_apicid);
 216
 217         //It's the time to set ctrl in sysinfo now;
 218         fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 219         enable_smbus();
 220
 221         //do we need apci timer, tsc...., only debug need it for better output
 222         /* all ap stopped? */
 223         // init_timer(); // Need to use TMICT to synconize FID/VID
 224
 225         sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 226
 227         post_cache_as_ram();
 228 }