2 #include <device/pci_def.h>
4 #include <device/pnp_def.h>
5 #include <arch/romcc_io.h>
6 #include <cpu/x86/lapic.h>
8 #include <console/console.h>
9 #include "lib/ramtest.c"
10 #include "southbridge/intel/i82801ex/i82801ex_early_smbus.c"
11 #include "northbridge/intel/e7520/raminit.h"
12 #include "superio/winbond/w83627hf/w83627hf.h"
13 #include "cpu/x86/lapic/boot_cpu.c"
14 #include "cpu/x86/mtrr/earlymtrr.c"
18 #include "x6dhr2_fixups.c"
19 #include "superio/winbond/w83627hf/w83627hf_early_init.c"
20 #include "northbridge/intel/e7520/memory_initialized.c"
21 #include "cpu/x86/bist.h"
24 #define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
25 #define HIDDEN_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP2)
27 #define DEVPRES_CONFIG ( \
35 #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
37 static inline int spd_read_byte(unsigned device, unsigned address)
39 return smbus_read_byte(device, address);
42 #include "northbridge/intel/e7520/raminit.c"
43 #include "lib/generic_sdram.c"
44 #include "arch/i386/lib/stages.c"
46 static void main(unsigned long bist)
48 static const struct mem_controller mch[] = {
51 .channel0 = {DIMM3, DIMM2, DIMM1, DIMM0, },
52 .channel1 = {DIMM7, DIMM6, DIMM5, DIMM4, },
57 /* Skip this if there was a built in self test failure */
59 if (memory_initialized())
63 /* Setup the console */
66 pnp_write_config(CONSOLE_SERIAL_DEV, 0x24, 0x84 | (1 << 6));
67 w83627hf_enable_dev(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE);
71 /* Halt if there was a built in self test failure */
72 // report_bist_failure(bist);
74 /* MOVE ME TO A BETTER LOCATION !!! */
75 /* config LPC decode for flash memory access */
77 dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0);
78 if (dev == PCI_DEV_INVALID)
80 pci_write_config32(dev, 0xe8, 0x00000000);
81 pci_write_config8(dev, 0xf0, 0x00);
84 display_cpuid_update_microcode();
91 // dump_spd_registers(&cpu[0]);
93 for(i = 0; i < 1; i++)
97 // dump_ipmi_registers();
98 mainboard_set_e7520_leds();
99 sdram_initialize(ARRAY_SIZE(mch), mch);
102 dump_pci_device(PCI_DEV(0, 0x00, 0));
103 dump_bar14(PCI_DEV(0, 0x00, 0));
106 #if 0 // temporarily disabled
107 /* Check the first 1M */
108 // ram_check(0x00000000, 0x000100000);
109 // ram_check(0x00000000, 0x000a0000);
110 // ram_check(0x00100000, 0x01000000);
111 ram_check(0x00100000, 0x00100100);
112 /* check the first 1M in the 3rd Gig */
113 // ram_check(0x30100000, 0x31000000);
116 ram_check(0x00000000, 0x02000000);