src/mainboard/supermicro/x6dhe_g/romstage.c

   1 #include <stdint.h>
   2 #include <device/pci_def.h>
   3 #include <arch/io.h>
   4 #include <device/pnp_def.h>
   5 #include <arch/romcc_io.h>
   6 #include <cpu/x86/lapic.h>
   7 #include <stdlib.h>
   8 #include <console/console.h>
   9 #include "lib/ramtest.c"
  10 #include "pc80/udelay_io.c"
  11 #include "lib/delay.c"
  12 #include "southbridge/intel/esb6300/esb6300_early_smbus.c"
  13 #include "northbridge/intel/e7520/raminit.h"
  14 #include "superio/winbond/w83627hf/w83627hf.h"
  15 #include "cpu/x86/lapic/boot_cpu.c"
  16 #include "cpu/x86/mtrr/earlymtrr.c"
  17 #include "debug.c"
  18 #include "watchdog.c"
  19 #include "reset.c"
  20 #include "x6dhe_g_fixups.c"
  21 #include "superio/winbond/w83627hf/w83627hf_early_init.c"
  22 #include "northbridge/intel/e7520/memory_initialized.c"
  23 #include "cpu/x86/bist.h"
  24 #include <spd.h>
  25
  26 #define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  27 #define HIDDEN_SERIAL_DEV  PNP_DEV(0x2e, W83627HF_SP2)
  28
  29 #define DEVPRES_CONFIG  ( \
  30         DEVPRES_D1F0 | \
  31         DEVPRES_D2F0 | \
  32         DEVPRES_D3F0 | \
  33         DEVPRES_D4F0 | \
  34         DEVPRES_D6F0 | \
  35         0 )
  36 #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
  37
  38 static inline int spd_read_byte(unsigned device, unsigned address)
  39 {
  40         return smbus_read_byte(device, address);
  41 }
  42
  43 #include "northbridge/intel/e7520/raminit.c"
  44 #include "lib/generic_sdram.c"
  45 #include "arch/i386/lib/stages.c"
  46
  47 static void main(unsigned long bist)
  48 {
  49         static const struct mem_controller mch[] = {
  50                 {
  51                         .node_id = 0,
  52                         .channel0 = {DIMM0, DIMM1, DIMM2, DIMM3, },
  53                         .channel1 = {DIMM4, DIMM5, DIMM6, DIMM7, },
  54                 }
  55         };
  56
  57         if (bist == 0) {
  58                 /* Skip this if there was a built in self test failure */
  59                 early_mtrr_init();
  60                 if (memory_initialized())
  61                         skip_romstage();
  62         }
  63
  64         /* Setup the console */
  65         outb(0x87,0x2e);
  66         outb(0x87,0x2e);
  67         pnp_write_config(CONSOLE_SERIAL_DEV, 0x24, 0x84 | (1 << 6));
  68         w83627hf_enable_dev(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE);
  69         uart_init();
  70         console_init();
  71
  72         /* Halt if there was a built in self test failure */
  73 //      report_bist_failure(bist);
  74
  75         /* MOVE ME TO A BETTER LOCATION !!! */
  76         /* config LPC decode for flash memory access */
  77         device_t dev;
  78         dev = pci_locate_device(PCI_ID(0x8086, 0x25a1), 0);
  79         if (dev == PCI_DEV_INVALID)
  80                 die("Missing esb6300?");
  81         pci_write_config32(dev, 0xe8, 0x00000000);
  82         pci_write_config8(dev, 0xf0, 0x00);
  83
  84 #if 0
  85         display_cpuid_update_microcode();
  86         print_pci_devices();
  87 #endif
  88 #if 1
  89         enable_smbus();
  90 #endif
  91 #if 0
  92 //      dump_spd_registers(&cpu[0]);
  93         int i;
  94         for(i = 0; i < 1; i++)
  95                 dump_spd_registers();
  96 #endif
  97         disable_watchdogs();
  98 //      dump_ipmi_registers();
  99 //      mainboard_set_e7520_leds();
 100         sdram_initialize(ARRAY_SIZE(mch), mch);
 101 #if 0
 102         dump_pci_devices();
 103         dump_pci_device(PCI_DEV(0, 0x00, 0));
 104         dump_bar14(PCI_DEV(0, 0x00, 0));
 105 #endif
 106
 107 #if 0 // temporarily disabled
 108         /* Check the first 1M */
 109 //      ram_check(0x00000000, 0x000100000);
 110 //      ram_check(0x00000000, 0x000a0000);
 111         ram_check(0x00100000, 0x01000000);
 112         /* check the first 1M in the 3rd Gig */
 113         ram_check(0x30100000, 0x31000000);
 114 #endif
 115 #if 0
 116         ram_check(0x00000000, 0x02000000);
 117 #endif
 118 }