2 * This file is part of the coreboot project.
4 * Copyright (C) 2006 AMD
5 * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
7 * Copyright (C) 2006 MSI
8 * Written by Bingxun Shi <bingxunshi@gmail.com> for MSI.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
27 #include <device/pci_def.h>
29 #include <device/pnp_def.h>
30 #include <arch/romcc_io.h>
31 #include <cpu/x86/lapic.h>
32 #include <pc80/mc146818rtc.h>
33 #include <console/console.h>
34 #include <cpu/amd/model_fxx_rev.h>
35 #include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
36 #include "northbridge/amd/amdk8/raminit.h"
37 #include "cpu/amd/model_fxx/apic_timer.c"
38 #include "lib/delay.c"
39 #include "cpu/x86/lapic/boot_cpu.c"
40 #include "northbridge/amd/amdk8/reset_test.c"
41 #include "northbridge/amd/amdk8/debug.c"
42 #include "superio/winbond/w83627ehg/w83627ehg_early_serial.c"
43 #include "cpu/x86/mtrr/earlymtrr.c"
44 #include "cpu/x86/bist.h"
46 #include "northbridge/amd/amdk8/setup_resource_map.c"
47 #include <device/pci_ids.h>
48 #include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
50 #define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
52 static void memreset(int controllers, const struct mem_controller *ctrl) { }
54 static inline void activate_spd_rom(const struct mem_controller *ctrl)
56 #define SMBUS_SWITCH1 0x70
57 #define SMBUS_SWITCH2 0x72
58 unsigned device=(ctrl->channel0[0])>>8;
59 smbus_send_byte(SMBUS_SWITCH1, device);
60 smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f);
64 static inline void change_i2c_mux(unsigned device)
66 #define SMBUS_SWITCH1 0x70
67 #define SMBUS_SWITHC2 0x72
68 smbus_send_byte(SMBUS_SWITCH1, device & 0x0f);
69 smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f);
73 static inline int spd_read_byte(unsigned device, unsigned address)
75 return smbus_read_byte(device, address);
78 #include "northbridge/amd/amdk8/amdk8_f.h"
79 #include "northbridge/amd/amdk8/incoherent_ht.c"
80 #include "northbridge/amd/amdk8/coherent_ht.c"
81 #include "northbridge/amd/amdk8/raminit_f.c"
82 #include "lib/generic_sdram.c"
83 #include "resourcemap.c"
84 #include "cpu/amd/dualcore/dualcore.c"
85 #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
87 //set GPIO to input mode
88 #define MCP55_MB_SETUP \
89 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXA_PRSNT2_L*/ \
90 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/ \
91 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/ \
92 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/ \
94 #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
95 #include "cpu/amd/car/post_cache_as_ram.c"
96 #include "cpu/amd/model_fxx/init_cpus.c"
97 // Disabled until it's actually used:
98 // #include "cpu/amd/model_fxx/fidvid.c"
99 #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
100 #include "northbridge/amd/amdk8/early_ht.c"
102 static void sio_setup(void)
107 byte = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b);
109 pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte);
111 dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0);
113 pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
116 //CPU 1 mem is on SMBUS_HUB channel 2, and CPU 2 mem is on channel 1.
120 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
122 static const uint16_t spd_addr[] = {
124 RC0|DIMM0, RC0|DIMM2, RC0|DIMM4, RC0|DIMM6,
125 RC0|DIMM1, RC0|DIMM3, RC0|DIMM5, RC0|DIMM7,
127 RC1|DIMM0, RC1|DIMM2, RC1|DIMM4, RC1|DIMM6,
128 RC1|DIMM1, RC1|DIMM3, RC1|DIMM5, RC1|DIMM7,
131 unsigned bsp_apicid = 0;
133 struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
134 + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
136 if (!cpu_init_detectedx && boot_cpu()) {
137 /* Nothing special needs to be done to find bus 0 */
138 /* Allow the HT devices to be found */
139 enumerate_ht_chain();
145 //init_cpus(cpu_init_detectedx);
146 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
149 w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
153 /* Halt if there was a built in self test failure */
154 report_bist_failure(bist);
156 setup_ms9282_resource_map();
158 setup_coherent_ht_domain();
160 wait_all_core0_started();
162 #if CONFIG_LOGICAL_CPUS==1
163 // It is said that we should start core1 after all core0 launched
165 //wait_all_other_cores_started(bsp_apicid);
167 ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
169 init_timer(); /* Need to use TMICT to synconize FID/VID. */
171 needs_reset = optimize_link_coherent_ht();
172 needs_reset |= optimize_link_incoherent_ht(sysinfo);
173 needs_reset |= mcp55_early_setup_x();
175 print_info("ht reset -\n");
179 //It's the time to set ctrl now;
180 fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
188 dump_smbus_registers();
192 sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);