src/mainboard/dell/s1850/romstage.c

   1 #include <stdint.h>
   2 #include <device/pci_def.h>
   3 #include <arch/io.h>
   4 #include <device/pnp_def.h>
   5 #include <arch/romcc_io.h>
   6 #include <cpu/x86/lapic.h>
   7 #include <stdlib.h>
   8 #include <console/console.h>
   9 #include "lib/ramtest.c"
  10 #include "southbridge/intel/i82801ex/i82801ex_early_smbus.c"
  11 #include "northbridge/intel/e7520/raminit.h"
  12 #include "superio/nsc/pc8374/pc8374_early_init.c"
  13 #include "cpu/x86/lapic/boot_cpu.c"
  14 #include "cpu/x86/mtrr/earlymtrr.c"
  15 #include "debug.c"
  16 #include "watchdog.c"
  17 // Remove comment if resets in this file are actually used.
  18 // #include "reset.c"
  19 #include "s1850_fixups.c"
  20 #include "northbridge/intel/e7520/memory_initialized.c"
  21 #include "cpu/x86/bist.h"
  22 #include <spd.h>
  23
  24 #define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, PC8374_SP1)
  25
  26 #define DEVPRES_CONFIG  ( \
  27         DEVPRES_D0F0 | \
  28         DEVPRES_D1F0 | \
  29         DEVPRES_D2F0 | \
  30         DEVPRES_D3F0 | \
  31         DEVPRES_D4F0 | \
  32         DEVPRES_D6F0 | \
  33         0 )
  34 #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
  35
  36 static inline int spd_read_byte(unsigned device, unsigned address)
  37 {
  38         return smbus_read_byte(device, address);
  39 }
  40
  41 #include "northbridge/intel/e7520/raminit.c"
  42 #include "lib/generic_sdram.c"
  43
  44 /* IPMI garbage. This is all test stuff, if it really works we'll move it somewhere
  45  */
  46
  47 #define nftransport  0xc
  48
  49 #define OBF  0
  50 #define IBF 1
  51
  52 #define ipmidata  0xca0
  53 #define ipmicsr  0xca4
  54
  55 static inline void  ibfzero(void)
  56 {
  57         while(inb(ipmicsr) &  (1<<IBF))
  58                 ;
  59 }
  60 static inline void  clearobf(void)
  61 {
  62         (void) inb(ipmidata);
  63 }
  64
  65 static inline void  waitobf(void)
  66 {
  67         while((inb(ipmicsr) &  (1<<OBF)) == 0)
  68                 ;
  69 }
  70
  71 /* quite possibly the stupidest interface ever designed. */
  72 static inline void  first_cmd_byte(unsigned char byte)
  73 {
  74         ibfzero();
  75         clearobf();
  76         outb(0x61, ipmicsr);
  77         ibfzero();
  78         clearobf();
  79         outb(byte, ipmidata);
  80 }
  81
  82 static inline void  next_cmd_byte(unsigned char byte)
  83 {
  84
  85         ibfzero();
  86         clearobf();
  87         outb(byte, ipmidata);
  88 }
  89
  90 static inline void  last_cmd_byte(unsigned char byte)
  91 {
  92         outb(0x62, ipmicsr);
  93
  94         ibfzero();
  95         clearobf();
  96         outb(byte,  ipmidata);
  97 }
  98
  99 static inline void read_response_byte(void)
 100 {
 101         int val = -1;
 102         if ((inb(ipmicsr)>>6) != 1)
 103                 return;
 104
 105         ibfzero();
 106         waitobf();
 107         val = inb(ipmidata);
 108         outb(0x68, ipmidata);
 109
 110         /* see if it is done */
 111         if ((inb(ipmicsr)>>6) != 1){
 112                 /* wait for the dummy read. Which describes this protocol */
 113                 waitobf();
 114                 (void)inb(ipmidata);
 115         }
 116 }
 117
 118 static inline void ipmidelay(void)
 119 {
 120         int i;
 121         for(i = 0; i < 1000; i++) {
 122                 inb(0x80);
 123         }
 124 }
 125
 126 static inline void bmc_foad(void)
 127 {
 128         unsigned char c;
 129         /* be safe; make sure it is really ready */
 130         while ((inb(ipmicsr)>>6)) {
 131                 outb(0x60, ipmicsr);
 132                 inb(ipmidata);
 133         }
 134         first_cmd_byte(nftransport << 2);
 135         ipmidelay();
 136         next_cmd_byte(0x12);
 137         ipmidelay();
 138         next_cmd_byte(2);
 139         ipmidelay();
 140         last_cmd_byte(3);
 141         ipmidelay();
 142 }
 143
 144 /* end IPMI garbage */
 145
 146 #include "arch/i386/lib/stages.c"
 147
 148 static void main(unsigned long bist)
 149 {
 150         u8 b;
 151         u16 w;
 152         u32 l;
 153         int do_reset;
 154
 155         static const struct mem_controller mch[] = {
 156                 {
 157                         .node_id = 0,
 158                         /* the wiring on this part is really messed up */
 159                         /* this is my best guess so far */
 160                         .channel0 = {DIMM0, DIMM1, DIMM2, DIMM3, },
 161                         .channel1 = {DIMM4, DIMM5, DIMM6, DIMM7, },
 162                 }
 163         };
 164
 165         /* superio setup */
 166         /* observed from serialice */
 167         static const u8 earlyinit[] = {
 168                 0x21, 0x11, 0x11,
 169                 0x22, 1, 1,
 170                 0x23, 05, 05,
 171                 0x24, 0x81, 0x81,
 172                 0x26, 0, 0,
 173                 0,
 174         };
 175
 176         /* using SerialICE, we've seen this basic reset sequence on the dell.
 177          * we don't understand it as it uses undocumented registers, but
 178          * we're going to clone it.
 179          */
 180         /* enable a hidden device. */
 181         b = pci_read_config8(PCI_DEV(0, 0, 0), 0xf4);
 182         b |= 0x8;
 183         pci_write_config8(PCI_DEV(0, 0, 0), 0xf4, b);
 184
 185         /* read-write lock in CMOS on LPC bridge on ICH5 */
 186         pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xd8, 4);
 187
 188         /* operate on undocumented device */
 189         l = pci_read_config32(PCI_DEV(0, 0, 2), 0xa4);
 190         l |= 0x1000;
 191         pci_write_config32(PCI_DEV(0, 0, 2), 0xa4, l);
 192
 193         l = pci_read_config32(PCI_DEV(0, 0, 2), 0x9c);
 194         l |= 0x8000;
 195         pci_write_config32(PCI_DEV(0, 0, 2), 0x9c, l);
 196
 197         /* disable undocumented device */
 198         b = pci_read_config8(PCI_DEV(0, 0, 0), 0xf4);
 199         b &= ~0x8;
 200         pci_write_config8(PCI_DEV(0, 0, 0), 0xf4, b);
 201
 202         /* set up LPC bridge bits, some of which reply on undocumented
 203          * registers
 204          */
 205
 206         b= pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xd8);
 207         b |= 4;
 208         pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xd8, b);
 209
 210         b= pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xd4);
 211         b |= 2;
 212         pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xd4, b);
 213
 214         /* ACPI base address */
 215         pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x40, 0x800);
 216
 217         /* Enable specific ACPI features */
 218         b= pci_read_config8(PCI_DEV(0, 0x1f, 0), 0x44);
 219         b |= 0x10;
 220         pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44, b);
 221
 222         /* ACPI control */
 223         w = inw(0x868);
 224         outw(w|0x800, 0x868);
 225         w = inw(0x866);
 226         outw(w|2, 0x866);
 227
 228 #if 0
 229         /*seriaice shows
 230         dell does this so leave it here so I don't forget
 231          */
 232         /* SMBUS */
 233         pci_write_config16(PCI_DEV(0, 0x1f, 3), 0x20, 0x08c0);
 234
 235         /* unknown */
 236         b = inb(0x8c2);
 237         outb(0xdf, 0x8c2);
 238 #endif
 239
 240         /* another device enable? */
 241         b = pci_read_config8(PCI_DEV(0, 0, 0), 0xf4);
 242         b |= 2;
 243         pci_write_config8(PCI_DEV(0, 0, 0), 0xf4, b);
 244
 245         /* ?? */
 246         l = pci_read_config32(PCI_DEV(0, 8, 0), 0xc0);
 247         do_reset = l & 0x8000000;
 248         l |= 0x8000000;
 249         pci_write_config32(PCI_DEV(0, 8, 0), 0xc0, l);
 250
 251         if (! do_reset) {
 252                 outb(2, 0xcf9);
 253                 outb(6, 0xcf9);
 254         }
 255         if (bist == 0) {
 256                 /* Skip this if there was a built in self test failure */
 257                 early_mtrr_init();
 258                 if (memory_initialized())
 259                         skip_romstage();
 260         }
 261         /* Setup the console */
 262         mainboard_set_ich5();
 263         //bmc_foad();
 264         pc8374_enable_dev(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE);
 265         uart_init();
 266         console_init();
 267
 268         /* stuff we seem to need */
 269         pc8374_enable_dev(PNP_DEV(0x2e, PC8374_KBCK), 0);
 270
 271         /* GPIOs */
 272         pc8374_enable_dev(PNP_DEV(0x2e, PC8374_GPIO), 0xc20);
 273
 274         /* keep this in mind.
 275         SerialICE-hlp: outb 002e <= 23
 276         SerialICE-hlp:  inb 002f => 05
 277         SerialICE-hlp: outb 002f <= 05
 278         SerialICE-hlp: outb 002e <= 24
 279         SerialICE-hlp:  inb 002f => c1
 280         SerialICE-hlp: outb 002f <= c1
 281          */
 282
 283         /* Halt if there was a built in self test failure */
 284 //      report_bist_failure(bist);
 285
 286         /* MOVE ME TO A BETTER LOCATION !!! */
 287         /* config LPC decode for flash memory access */
 288         device_t dev;
 289         dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0);
 290         if (dev == PCI_DEV_INVALID) {
 291                 die("Missing ich5?");
 292         }
 293         pci_write_config32(dev, 0xe8, 0x00000000);
 294         pci_write_config8(dev, 0xf0, 0x00);
 295
 296 #if 0
 297         display_cpuid_update_microcode();
 298 #endif
 299 #if 1
 300         print_pci_devices();
 301 #endif
 302 #if 1
 303         enable_smbus();
 304 #endif
 305 #if 0
 306 //      dump_spd_registers(&cpu[0]);
 307         int i;
 308         for(i = 0; i < 1; i++)
 309                 dump_spd_registers();
 310 #endif
 311 #if 1
 312         show_dram_slots();
 313 #endif
 314         disable_watchdogs();
 315 //      dump_ipmi_registers();
 316         mainboard_set_e7520_leds();
 317
 318         sdram_initialize(ARRAY_SIZE(mch), mch);
 319 #if 0
 320         dump_pci_devices();
 321 #endif
 322 #if 1
 323         dump_pci_device(PCI_DEV(0, 0x00, 0));
 324 //      dump_bar14(PCI_DEV(0, 0x00, 0));
 325 #endif
 326
 327 #if 1 // temporarily disabled
 328         /* Check the first 1M */
 329 //      ram_check(0x00000000, 0x000100000);
 330 //      ram_check(0x00000000, 0x000a0000);
 331 //      ram_check(0x00100000, 0x01000000);
 332         ram_check(0x00100000, 0x00100100);
 333         /* check the first 1M in the 3rd Gig */
 334 //      ram_check(0x30100000, 0x31000000);
 335 #endif
 336 #if 0
 337         ram_check(0x00000000, 0x02000000);
 338 #endif
 339 }