src/mainboard/amd/pistachio/romstage.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2008 Advanced Micro Devices, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18  */
  19
  20 #include <stdint.h>
  21 #include <string.h>
  22 #include <device/pci_def.h>
  23 #include <arch/io.h>
  24 #include <device/pnp_def.h>
  25 #include <arch/romcc_io.h>
  26 #include <cpu/x86/lapic.h>
  27 #include <pc80/mc146818rtc.h>
  28 #include <console/console.h>
  29 #include <cpu/amd/model_fxx_rev.h>
  30 #include "northbridge/amd/amdk8/raminit.h"
  31 #include "cpu/amd/model_fxx/apic_timer.c"
  32 #include "lib/delay.c"
  33 #include "cpu/x86/lapic/boot_cpu.c"
  34 #include "northbridge/amd/amdk8/reset_test.c"
  35 #include "superio/ite/it8712f/it8712f_early_serial.c"
  36 #include <usbdebug.h>
  37 #include <spd.h>
  38 #include "cpu/x86/mtrr/earlymtrr.c"
  39 #include "cpu/x86/bist.h"
  40 #include "northbridge/amd/amdk8/setup_resource_map.c"
  41 #include "southbridge/amd/rs690/rs690_early_setup.c"
  42 #include "southbridge/amd/sb600/sb600_early_setup.c"
  43 #include "northbridge/amd/amdk8/debug.c" /* After sb600_early_setup.c! */
  44
  45 static void memreset(int controllers, const struct mem_controller *ctrl) { }
  46 static void activate_spd_rom(const struct mem_controller *ctrl) { }
  47
  48 static inline int spd_read_byte(u32 device, u32 address)
  49 {
  50         return smbus_read_byte(device, address);
  51 }
  52
  53 #include "northbridge/amd/amdk8/amdk8.h"
  54 #include "northbridge/amd/amdk8/incoherent_ht.c"
  55 #include "northbridge/amd/amdk8/raminit_f.c"
  56 #include "northbridge/amd/amdk8/coherent_ht.c"
  57 #include "lib/generic_sdram.c"
  58 #include "resourcemap.c"
  59 #include "cpu/amd/dualcore/dualcore.c"
  60 #include "cpu/amd/car/post_cache_as_ram.c"
  61 #include "cpu/amd/model_fxx/init_cpus.c"
  62 #include "cpu/amd/model_fxx/fidvid.c"
  63 #include "northbridge/amd/amdk8/early_ht.c"
  64
  65 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
  66 {
  67         static const u16 spd_addr[] = { DIMM0, 0, 0, 0, DIMM1, 0, 0, 0, };
  68         int needs_reset = 0;
  69         u32 bsp_apicid = 0;
  70         msr_t msr;
  71         struct cpuid_result cpuid1;
  72         struct sys_info *sysinfo =
  73             (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE -
  74                                 CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
  75
  76         if (!cpu_init_detectedx && boot_cpu()) {
  77                 /* Nothing special needs to be done to find bus 0 */
  78                 /* Allow the HT devices to be found */
  79                 enumerate_ht_chain();
  80                 sb600_lpc_port80();
  81                 /* sb600_pci_port80(); */
  82         }
  83
  84         if (bist == 0)
  85                 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
  86
  87         enable_rs690_dev8();
  88         sb600_lpc_init();
  89
  90         /* Pistachio used a FPGA to enable serial debug instead of a SIO
  91          * and it doesn't require any special setup. */
  92         uart_init();
  93
  94 #if CONFIG_USBDEBUG
  95         sb600_enable_usbdebug(0);
  96         early_usbdebug_init();
  97 #endif
  98
  99         console_init();
 100
 101         post_code(0x03);
 102
 103         /* Halt if there was a built in self test failure */
 104         report_bist_failure(bist);
 105         printk(BIOS_DEBUG, "bsp_apicid=0x%x\n", bsp_apicid);
 106
 107         setup_pistachio_resource_map();
 108
 109         setup_coherent_ht_domain();
 110
 111 #if CONFIG_LOGICAL_CPUS==1
 112         /* It is said that we should start core1 after all core0 launched */
 113         wait_all_core0_started();
 114         start_other_cores();
 115 #endif
 116         wait_all_aps_started(bsp_apicid);
 117
 118         /* it will set up chains and store link pair for optimization later,
 119          * it will init sblnk and sbbusn, nodes, sbdn */
 120         ht_setup_chains_x(sysinfo);
 121
 122         /* run _early_setup before soft-reset. */
 123         rs690_early_setup();
 124         sb600_early_setup();
 125
 126         post_code(0x04);
 127
 128         /* Check to see if processor is capable of changing FIDVID  */
 129         /* otherwise it will throw a GP# when reading FIDVID_STATUS */
 130         cpuid1 = cpuid(0x80000007);
 131         if ((cpuid1.edx & 0x6) == 0x6) {
 132                 /* Read FIDVID_STATUS */
 133                 msr=rdmsr(0xc0010042);
 134                 printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
 135
 136                 enable_fid_change();
 137                 enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
 138                 init_fidvid_bsp(bsp_apicid);
 139
 140                 /* show final fid and vid */
 141                 msr=rdmsr(0xc0010042);
 142                 printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
 143         } else {
 144                 printk(BIOS_DEBUG, "Changing FIDVID not supported\n");
 145         }
 146
 147         post_code(0x05);
 148
 149         needs_reset = optimize_link_coherent_ht();
 150         needs_reset |= optimize_link_incoherent_ht(sysinfo);
 151         rs690_htinit();
 152         printk(BIOS_DEBUG, "needs_reset=0x%x\n", needs_reset);
 153
 154         post_code(0x06);
 155
 156         if (needs_reset) {
 157                 print_info("ht reset -\n");
 158                 soft_reset();
 159         }
 160
 161         allow_all_aps_stop(bsp_apicid);
 162
 163         /* It's the time to set ctrl now; */
 164         printk(BIOS_DEBUG, "sysinfo->nodes: %2x  sysinfo->ctrl: %p  spd_addr: %p\n",
 165                      sysinfo->nodes, sysinfo->ctrl, spd_addr);
 166         fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 167
 168         post_code(0x07);
 169
 170         sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 171
 172         post_code(0x08);
 173
 174         rs690_before_pci_init();
 175         sb600_before_pci_init();
 176
 177         post_cache_as_ram();
 178 }