src/mainboard/msi/ms7135/romstage.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007 AMD
   5  * (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
   6  * Copyright (C) 2007 Philipp Degler <pdegler@rumms.uni-mannheim.de>
   7  * (Thanks to LSRA University of Mannheim for their support)
   8  * Copyright (C) 2008 Jonathan A. Kollasch <jakllsch@kollasch.net>
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  23  */
  24
  25 #include <stdint.h>
  26 #include <string.h>
  27 #include <device/pci_def.h>
  28 #include <arch/io.h>
  29 #include <device/pnp_def.h>
  30 #include <arch/romcc_io.h>
  31 #include <cpu/x86/lapic.h>
  32 #include <pc80/mc146818rtc.h>
  33 #include "cpu/x86/lapic/boot_cpu.c"
  34 #include "northbridge/amd/amdk8/reset_test.c"
  35 #include "superio/winbond/w83627thg/w83627thg_early_serial.c"
  36 #include <cpu/amd/model_fxx_rev.h>
  37 #include <console/console.h>
  38 #include "northbridge/amd/amdk8/incoherent_ht.c"
  39 #include "southbridge/nvidia/ck804/ck804_early_smbus.h"
  40 #include "northbridge/amd/amdk8/raminit.h"
  41 #include "cpu/amd/model_fxx/apic_timer.c"
  42 #include "lib/delay.c"
  43 #include "northbridge/amd/amdk8/debug.c"
  44 #include "cpu/x86/mtrr/earlymtrr.c"
  45 #include "cpu/x86/bist.h"
  46 #include "northbridge/amd/amdk8/setup_resource_map.c"
  47 #include "northbridge/amd/amdk8/coherent_ht.c"
  48 #include "cpu/amd/dualcore/dualcore.c"
  49 #include <spd.h>
  50
  51 #define SERIAL_DEV PNP_DEV(0x4e, W83627THG_SP1)
  52
  53 static void memreset(int controllers, const struct mem_controller *ctrl) { }
  54 static void activate_spd_rom(const struct mem_controller *ctrl) { }
  55
  56 static inline int spd_read_byte(unsigned device, unsigned address)
  57 {
  58         return smbus_read_byte(device, address);
  59 }
  60
  61 #include "northbridge/amd/amdk8/raminit.c"
  62 #include "lib/generic_sdram.c"
  63 #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
  64 #include "southbridge/nvidia/ck804/ck804_early_setup_car.c"
  65 #include "cpu/amd/car/post_cache_as_ram.c"
  66 #include "cpu/amd/model_fxx/init_cpus.c"
  67 #include "northbridge/amd/amdk8/early_ht.c"
  68
  69 static void sio_setup(void)
  70 {
  71         uint32_t dword;
  72         uint8_t byte;
  73
  74         /* Subject decoding */
  75         byte = pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0x7b);
  76         byte |= 0x20;
  77         pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0x7b, byte);
  78
  79         /* LPC Positive Decode 0 */
  80         dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0xa0);
  81         /* Serial 0, Serial 1 */
  82         dword |= (1 << 0) | (1 << 1);
  83         pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0xa0, dword);
  84 }
  85
  86 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
  87 {
  88         static const uint16_t spd_addr[] = {
  89                 DIMM0, DIMM1, 0, 0,
  90                 0, 0, 0, 0,
  91                 0, 0, 0, 0,
  92                 0, 0, 0, 0,
  93         };
  94
  95         int needs_reset;
  96         unsigned bsp_apicid = 0, nodes;
  97         struct mem_controller ctrl[8];
  98
  99         if (!cpu_init_detectedx && boot_cpu()) {
 100                 /* Nothing special needs to be done to find bus 0 */
 101                 /* Allow the HT devices to be found */
 102                 enumerate_ht_chain();
 103                 sio_setup();
 104         }
 105
 106         if (bist == 0)
 107                 bsp_apicid = init_cpus(cpu_init_detectedx);
 108
 109         w83627thg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 110         uart_init();
 111         console_init();
 112
 113         /* Halt if there was a built in self test failure */
 114         report_bist_failure(bist);
 115
 116 #if 0
 117         dump_pci_device(PCI_DEV(0, 0x18, 0));
 118 #endif
 119
 120         needs_reset = setup_coherent_ht_domain();
 121
 122         wait_all_core0_started();
 123 #if CONFIG_LOGICAL_CPUS==1
 124         // It is said that we should start core1 after all core0 launched
 125         start_other_cores();
 126         wait_all_other_cores_started(bsp_apicid);
 127 #endif
 128
 129         needs_reset |= ht_setup_chains_x();
 130         needs_reset |= ck804_early_setup_x();
 131         if (needs_reset) {
 132                 print_info("ht reset -\n");
 133                 soft_reset();
 134         }
 135
 136         allow_all_aps_stop(bsp_apicid);
 137
 138         nodes = get_nodes();
 139         //It's the time to set ctrl now;
 140         fill_mem_ctrl(nodes, ctrl, spd_addr);
 141
 142         enable_smbus();
 143
 144 #if 0
 145         dump_spd_registers(&ctrl[0]);
 146         dump_smbus_registers();
 147 #endif
 148
 149         sdram_initialize(nodes, ctrl);
 150
 151 #if 0
 152         print_pci_devices();
 153         dump_pci_devices();
 154 #endif
 155
 156         post_cache_as_ram();
 157 }