src/mainboard/asus/a8v-e_deluxe/romstage.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2006 AMD
   5  * (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
   6  * Copyright (C) 2006 MSI
   7  * (Written by Bingxun Shi <bingxunshi@gmail.com> for MSI)
   8  * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  23  */
  24
  25 unsigned int get_sbdn(unsigned bus);
  26
  27 #include <stdint.h>
  28 #include <string.h>
  29 #include <device/pci_def.h>
  30 #include <arch/io.h>
  31 #include <device/pnp_def.h>
  32 #include <arch/romcc_io.h>
  33 #include <cpu/x86/lapic.h>
  34 #include <pc80/mc146818rtc.h>
  35 #include <console/console.h>
  36 #include <cpu/amd/model_fxx_rev.h>
  37 #include "northbridge/amd/amdk8/raminit.h"
  38 #include "cpu/amd/model_fxx/apic_timer.c"
  39 #include "lib/delay.c"
  40 #include "cpu/x86/lapic/boot_cpu.c"
  41 #include "northbridge/amd/amdk8/reset_test.c"
  42 #include "northbridge/amd/amdk8/early_ht.c"
  43 #include "superio/winbond/w83627ehg/w83627ehg_early_serial.c"
  44 #include "southbridge/via/vt8237r/vt8237r_early_smbus.c"
  45 #include "northbridge/amd/amdk8/debug.c" /* After vt8237r_early_smbus.c! */
  46 #include "cpu/x86/mtrr/earlymtrr.c"
  47 #include "cpu/x86/bist.h"
  48 #include "northbridge/amd/amdk8/setup_resource_map.c"
  49 #include <spd.h>
  50
  51 #define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
  52 #define GPIO_DEV PNP_DEV(0x2e, W83627EHG_GPIO_SUSLED)
  53 #define ACPI_DEV PNP_DEV(0x2e, W83627EHG_ACPI)
  54
  55 static void memreset(int controllers, const struct mem_controller *ctrl) { }
  56 static void activate_spd_rom(const struct mem_controller *ctrl) { }
  57
  58 static inline int spd_read_byte(unsigned device, unsigned address)
  59 {
  60         return smbus_read_byte(device, address);
  61 }
  62
  63 #include <reset.h>
  64 void soft_reset(void)
  65 {
  66         uint8_t tmp;
  67
  68         set_bios_reset();
  69         print_debug("soft reset \n");
  70
  71         /* PCI reset */
  72         tmp = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x4f);
  73         tmp |= 0x01;
  74         pci_write_config8(PCI_DEV(0, 0x11, 0), 0x4f, tmp);
  75
  76         while (1) {
  77                 /* daisy daisy ... */
  78                 hlt();
  79         }
  80 }
  81
  82 // defines S3_NVRAM_EARLY:
  83 #include "southbridge/via/k8t890/k8t890_early_car.c"
  84 #include "northbridge/amd/amdk8/amdk8.h"
  85 #include "northbridge/amd/amdk8/incoherent_ht.c"
  86 #include "northbridge/amd/amdk8/coherent_ht.c"
  87 #include "northbridge/amd/amdk8/raminit.c"
  88 #include "lib/generic_sdram.c"
  89 #include "cpu/amd/dualcore/dualcore.c"
  90 #include "cpu/amd/car/post_cache_as_ram.c"
  91 #include "cpu/amd/model_fxx/init_cpus.c"
  92 #include "cpu/amd/model_fxx/fidvid.c"
  93 #include "northbridge/amd/amdk8/resourcemap.c"
  94
  95 unsigned int get_sbdn(unsigned bus)
  96 {
  97         device_t dev;
  98
  99         dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA,
 100                                         PCI_DEVICE_ID_VIA_VT8237R_LPC), bus);
 101         return (dev >> 15) & 0x1f;
 102 }
 103
 104 static void sio_init(void)
 105 {
 106         u8 reg;
 107
 108         pnp_enter_ext_func_mode(SERIAL_DEV);
 109         /* We have 24MHz input. */
 110         reg = pnp_read_config(SERIAL_DEV, 0x24);
 111         pnp_write_config(SERIAL_DEV, 0x24, (reg & ~0x40));
 112         /* We have GPIO for KB/MS pin. */
 113         reg = pnp_read_config(SERIAL_DEV, 0x2a);
 114         pnp_write_config(SERIAL_DEV, 0x2a, (reg | 1));
 115         /* We have all RESTOUT and even some reserved bits, too. */
 116         reg = pnp_read_config(SERIAL_DEV, 0x2c);
 117         pnp_write_config(SERIAL_DEV, 0x2c, (reg | 0xf0));
 118         pnp_exit_ext_func_mode(SERIAL_DEV);
 119
 120         pnp_enter_ext_func_mode(ACPI_DEV);
 121         pnp_set_logical_device(ACPI_DEV);
 122         /*
 123          * Set the delay rising time from PWROK_LP to PWROK_ST to
 124          * 300 - 600ms, and 0 to vice versa.
 125          */
 126         reg = pnp_read_config(ACPI_DEV, 0xe6);
 127         pnp_write_config(ACPI_DEV, 0xe6, (reg & 0xf0));
 128         /* 1 Use external suspend clock source 32.768KHz. Undocumented?? */
 129         reg = pnp_read_config(ACPI_DEV, 0xe4);
 130         pnp_write_config(ACPI_DEV, 0xe4, (reg | 0x10));
 131         pnp_exit_ext_func_mode(ACPI_DEV);
 132
 133         pnp_enter_ext_func_mode(GPIO_DEV);
 134         pnp_set_logical_device(GPIO_DEV);
 135         /* Set memory voltage to 2.75V, vcore offset + 100mV, 1.5V chipset voltage. */
 136         pnp_write_config(GPIO_DEV, 0x30, 0x09); /* Enable GPIO 2 & GPIO 5. */
 137         pnp_write_config(GPIO_DEV, 0xe2, 0x00); /* No inversion */
 138         pnp_write_config(GPIO_DEV, 0xe5, 0x00); /* No inversion */
 139         pnp_write_config(GPIO_DEV, 0xe3, 0x03); /* 0000 0011, 0=output 1=input */
 140         pnp_write_config(GPIO_DEV, 0xe0, 0xde); /* 1101 1110, 0=output 1=input */
 141         pnp_write_config(GPIO_DEV, 0xe1, 0x01); /* Set output val. */
 142         pnp_write_config(GPIO_DEV, 0xe4, 0xb4); /* Set output val (1011 0100). */
 143         pnp_exit_ext_func_mode(GPIO_DEV);
 144 }
 145
 146 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 147 {
 148         static const uint16_t spd_addr[] = {
 149                 // Node 0
 150                 DIMM0, DIMM2, 0, 0,
 151                 DIMM1, DIMM3, 0, 0,
 152                 // Node 1
 153                 DIMM4, DIMM6, 0, 0,
 154                 DIMM5, DIMM7, 0, 0,
 155         };
 156         unsigned bsp_apicid = 0;
 157         int needs_reset = 0;
 158         struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
 159                 + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 160
 161         sio_init();
 162         w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 163         uart_init();
 164         console_init();
 165         enable_rom_decode();
 166
 167         print_info("now booting... fallback\n");
 168
 169         /* Is this a CPU only reset? Or is this a secondary CPU? */
 170         if (!cpu_init_detectedx && boot_cpu()) {
 171                 /* Nothing special needs to be done to find bus 0. */
 172                 /* Allow the HT devices to be found. */
 173                 enumerate_ht_chain();
 174         }
 175
 176         sio_init();
 177         w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 178         uart_init();
 179         console_init();
 180         enable_rom_decode();
 181
 182         print_info("now booting... real_main\n");
 183
 184         if (bist == 0)
 185                 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 186
 187         /* Halt if there was a built in self test failure. */
 188         report_bist_failure(bist);
 189
 190         setup_default_resource_map();
 191         setup_coherent_ht_domain();
 192         wait_all_core0_started();
 193
 194         print_info("now booting... Core0 started\n");
 195
 196 #if CONFIG_LOGICAL_CPUS==1
 197         /* It is said that we should start core1 after all core0 launched. */
 198         start_other_cores();
 199         wait_all_other_cores_started(bsp_apicid);
 200 #endif
 201         init_timer();
 202         ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. */
 203
 204         needs_reset = optimize_link_coherent_ht();
 205         needs_reset |= optimize_link_incoherent_ht(sysinfo);
 206         needs_reset |= k8t890_early_setup_ht();
 207
 208         if (needs_reset) {
 209                 print_debug("ht reset -\n");
 210                 soft_reset();
 211         }
 212
 213         /* the HT settings needs to be OK, because link freq chnage may cause HT disconnect */
 214         enable_fid_change();
 215         init_fidvid_bsp(bsp_apicid);
 216
 217         /* Stop the APs so we can start them later in init. */
 218         allow_all_aps_stop(bsp_apicid);
 219
 220         /* It's the time to set ctrl now. */
 221         fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 222
 223         enable_smbus();
 224         sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 225         post_cache_as_ram();
 226 }