4er slot (3. bsp fertig)
authorBernhard Urban <lewurm@gmx.net>
Thu, 29 Oct 2009 16:40:27 +0000 (17:40 +0100)
committerBernhard Urban <lewurm@gmx.net>
Thu, 29 Oct 2009 16:40:27 +0000 (17:40 +0100)
880 files changed:
bsp3/Designflow/ppr/download/db/vga_pll.(0).cnf.cdb [new file with mode: 0644]
bsp3/Designflow/ppr/download/db/vga_pll.(0).cnf.hdb [new file with mode: 0644]
bsp3/Designflow/ppr/download/db/vga_pll.(1).cnf.cdb [new file with mode: 0644]
bsp3/Designflow/ppr/download/db/vga_pll.(1).cnf.hdb [new file with mode: 0644]
bsp3/Designflow/ppr/download/db/vga_pll.(2).cnf.cdb [new file with mode: 0644]
bsp3/Designflow/ppr/download/db/vga_pll.(2).cnf.hdb [new file with mode: 0644]
bsp3/Designflow/ppr/download/db/vga_pll.(3).cnf.cdb [new file with mode: 0644]
bsp3/Designflow/ppr/download/db/vga_pll.(3).cnf.hdb [new file with mode: 0644]
bsp3/Designflow/ppr/download/db/vga_pll.(4).cnf.cdb [new file with mode: 0644]
bsp3/Designflow/ppr/download/db/vga_pll.(4).cnf.hdb [new file with mode: 0644]
bsp3/Designflow/ppr/download/db/vga_pll.(5).cnf.cdb [new file with mode: 0644]
bsp3/Designflow/ppr/download/db/vga_pll.(5).cnf.hdb [new file with mode: 0644]
bsp3/Designflow/ppr/download/db/vga_pll.asm.qmsg [new file with mode: 0644]
bsp3/Designflow/ppr/download/db/vga_pll.cbx.xml [new file with mode: 0644]
bsp3/Designflow/ppr/download/db/vga_pll.cmp.cdb [new file with mode: 0644]
bsp3/Designflow/ppr/download/db/vga_pll.cmp.hdb [new file with mode: 0644]
bsp3/Designflow/ppr/download/db/vga_pll.cmp.kpt [new file with mode: 0644]
bsp3/Designflow/ppr/download/db/vga_pll.cmp.logdb [new file with mode: 0644]
bsp3/Designflow/ppr/download/db/vga_pll.cmp.rdb [new file with mode: 0644]
bsp3/Designflow/ppr/download/db/vga_pll.cmp.tdb [new file with mode: 0644]
bsp3/Designflow/ppr/download/db/vga_pll.cmp0.ddb [new file with mode: 0644]
bsp3/Designflow/ppr/download/db/vga_pll.db_info [new file with mode: 0644]
bsp3/Designflow/ppr/download/db/vga_pll.eco.cdb [new file with mode: 0644]
bsp3/Designflow/ppr/download/db/vga_pll.eda.qmsg [new file with mode: 0644]
bsp3/Designflow/ppr/download/db/vga_pll.fit.qmsg [new file with mode: 0644]
bsp3/Designflow/ppr/download/db/vga_pll.hier_info [new file with mode: 0644]
bsp3/Designflow/ppr/download/db/vga_pll.hif [new file with mode: 0644]
bsp3/Designflow/ppr/download/db/vga_pll.lpc.html [new file with mode: 0644]
bsp3/Designflow/ppr/download/db/vga_pll.lpc.rdb [new file with mode: 0644]
bsp3/Designflow/ppr/download/db/vga_pll.lpc.txt [new file with mode: 0644]
bsp3/Designflow/ppr/download/db/vga_pll.map.cdb [new file with mode: 0644]
bsp3/Designflow/ppr/download/db/vga_pll.map.hdb [new file with mode: 0644]
bsp3/Designflow/ppr/download/db/vga_pll.map.logdb [new file with mode: 0644]
bsp3/Designflow/ppr/download/db/vga_pll.map.qmsg [new file with mode: 0644]
bsp3/Designflow/ppr/download/db/vga_pll.pre_map.cdb [new file with mode: 0644]
bsp3/Designflow/ppr/download/db/vga_pll.pre_map.hdb [new file with mode: 0644]
bsp3/Designflow/ppr/download/db/vga_pll.rtlv.hdb [new file with mode: 0644]
bsp3/Designflow/ppr/download/db/vga_pll.rtlv_sg.cdb [new file with mode: 0644]
bsp3/Designflow/ppr/download/db/vga_pll.rtlv_sg_swap.cdb [new file with mode: 0644]
bsp3/Designflow/ppr/download/db/vga_pll.sgdiff.cdb [new file with mode: 0644]
bsp3/Designflow/ppr/download/db/vga_pll.sgdiff.hdb [new file with mode: 0644]
bsp3/Designflow/ppr/download/db/vga_pll.sld_design_entry.sci [new file with mode: 0644]
bsp3/Designflow/ppr/download/db/vga_pll.sld_design_entry_dsc.sci [new file with mode: 0644]
bsp3/Designflow/ppr/download/db/vga_pll.syn_hier_info [new file with mode: 0644]
bsp3/Designflow/ppr/download/db/vga_pll.tan.qmsg [new file with mode: 0644]
bsp3/Designflow/ppr/download/db/vga_pll.tis_db_list.ddb [new file with mode: 0644]
bsp3/Designflow/ppr/download/db/vga_pll.tmw_info [new file with mode: 0644]
bsp3/Designflow/ppr/download/db/vga_pll_global_asgn_op.abo [new file with mode: 0644]
bsp3/Designflow/ppr/download/incremental_db/README [new file with mode: 0644]
bsp3/Designflow/ppr/download/incremental_db/compiled_partitions/vga_pll.root_partition.map.kpt [new file with mode: 0644]
bsp3/Designflow/ppr/download/simulation/modelsim/vga_pll.sft [new file with mode: 0644]
bsp3/Designflow/ppr/download/simulation/modelsim/vga_pll.vo [new file with mode: 0644]
bsp3/Designflow/ppr/download/simulation/modelsim/vga_pll_modelsim.xrf [new file with mode: 0644]
bsp3/Designflow/ppr/download/simulation/modelsim/vga_pll_v.sdo [new file with mode: 0644]
bsp3/Designflow/ppr/download/vga_pll.asm.rpt [new file with mode: 0644]
bsp3/Designflow/ppr/download/vga_pll.done [new file with mode: 0644]
bsp3/Designflow/ppr/download/vga_pll.eda.rpt [new file with mode: 0644]
bsp3/Designflow/ppr/download/vga_pll.fit.rpt [new file with mode: 0644]
bsp3/Designflow/ppr/download/vga_pll.fit.smsg [new file with mode: 0644]
bsp3/Designflow/ppr/download/vga_pll.fit.summary [new file with mode: 0644]
bsp3/Designflow/ppr/download/vga_pll.flow.rpt [new file with mode: 0644]
bsp3/Designflow/ppr/download/vga_pll.map.rpt [new file with mode: 0644]
bsp3/Designflow/ppr/download/vga_pll.map.summary [new file with mode: 0644]
bsp3/Designflow/ppr/download/vga_pll.pin [new file with mode: 0644]
bsp3/Designflow/ppr/download/vga_pll.pof [new file with mode: 0644]
bsp3/Designflow/ppr/download/vga_pll.qpf [new file with mode: 0644]
bsp3/Designflow/ppr/download/vga_pll.qsf [new file with mode: 0644]
bsp3/Designflow/ppr/download/vga_pll.qws [new file with mode: 0644]
bsp3/Designflow/ppr/download/vga_pll.sof [new file with mode: 0644]
bsp3/Designflow/ppr/download/vga_pll.tan.rpt [new file with mode: 0644]
bsp3/Designflow/ppr/download/vga_pll.tan.summary [new file with mode: 0644]
bsp3/Designflow/ppr/download/vga_pll.tcl [new file with mode: 0755]
bsp3/Designflow/ppr/download/vga_pll_assignment_defaults.qdf [new file with mode: 0644]
bsp3/Designflow/ppr/sim/db/vga.(0).cnf.cdb [new file with mode: 0644]
bsp3/Designflow/ppr/sim/db/vga.(0).cnf.hdb [new file with mode: 0644]
bsp3/Designflow/ppr/sim/db/vga.(1).cnf.cdb [new file with mode: 0644]
bsp3/Designflow/ppr/sim/db/vga.(1).cnf.hdb [new file with mode: 0644]
bsp3/Designflow/ppr/sim/db/vga.(2).cnf.cdb [new file with mode: 0644]
bsp3/Designflow/ppr/sim/db/vga.(2).cnf.hdb [new file with mode: 0644]
bsp3/Designflow/ppr/sim/db/vga.asm.qmsg [new file with mode: 0644]
bsp3/Designflow/ppr/sim/db/vga.cbx.xml [new file with mode: 0644]
bsp3/Designflow/ppr/sim/db/vga.cmp.bpm [new file with mode: 0644]
bsp3/Designflow/ppr/sim/db/vga.cmp.cdb [new file with mode: 0644]
bsp3/Designflow/ppr/sim/db/vga.cmp.ecobp [new file with mode: 0644]
bsp3/Designflow/ppr/sim/db/vga.cmp.hdb [new file with mode: 0644]
bsp3/Designflow/ppr/sim/db/vga.cmp.kpt [new file with mode: 0644]
bsp3/Designflow/ppr/sim/db/vga.cmp.logdb [new file with mode: 0644]
bsp3/Designflow/ppr/sim/db/vga.cmp.rdb [new file with mode: 0644]
bsp3/Designflow/ppr/sim/db/vga.cmp.tdb [new file with mode: 0644]
bsp3/Designflow/ppr/sim/db/vga.cmp0.ddb [new file with mode: 0644]
bsp3/Designflow/ppr/sim/db/vga.cmp_merge.kpt [new file with mode: 0644]
bsp3/Designflow/ppr/sim/db/vga.db_info [new file with mode: 0644]
bsp3/Designflow/ppr/sim/db/vga.eco.cdb [new file with mode: 0644]
bsp3/Designflow/ppr/sim/db/vga.eda.qmsg [new file with mode: 0644]
bsp3/Designflow/ppr/sim/db/vga.fit.qmsg [new file with mode: 0644]
bsp3/Designflow/ppr/sim/db/vga.hier_info [new file with mode: 0644]
bsp3/Designflow/ppr/sim/db/vga.hif [new file with mode: 0644]
bsp3/Designflow/ppr/sim/db/vga.lpc.html [new file with mode: 0644]
bsp3/Designflow/ppr/sim/db/vga.lpc.rdb [new file with mode: 0644]
bsp3/Designflow/ppr/sim/db/vga.lpc.txt [new file with mode: 0644]
bsp3/Designflow/ppr/sim/db/vga.map.bpm [new file with mode: 0644]
bsp3/Designflow/ppr/sim/db/vga.map.cdb [new file with mode: 0644]
bsp3/Designflow/ppr/sim/db/vga.map.ecobp [new file with mode: 0644]
bsp3/Designflow/ppr/sim/db/vga.map.hdb [new file with mode: 0644]
bsp3/Designflow/ppr/sim/db/vga.map.kpt [new file with mode: 0644]
bsp3/Designflow/ppr/sim/db/vga.map.logdb [new file with mode: 0644]
bsp3/Designflow/ppr/sim/db/vga.map.qmsg [new file with mode: 0644]
bsp3/Designflow/ppr/sim/db/vga.map_bb.cdb [new file with mode: 0644]
bsp3/Designflow/ppr/sim/db/vga.map_bb.hdb [new file with mode: 0644]
bsp3/Designflow/ppr/sim/db/vga.map_bb.logdb [new file with mode: 0644]
bsp3/Designflow/ppr/sim/db/vga.pre_map.cdb [new file with mode: 0644]
bsp3/Designflow/ppr/sim/db/vga.pre_map.hdb [new file with mode: 0644]
bsp3/Designflow/ppr/sim/db/vga.rtlv.hdb [new file with mode: 0644]
bsp3/Designflow/ppr/sim/db/vga.rtlv_sg.cdb [new file with mode: 0644]
bsp3/Designflow/ppr/sim/db/vga.rtlv_sg_swap.cdb [new file with mode: 0644]
bsp3/Designflow/ppr/sim/db/vga.sgdiff.cdb [new file with mode: 0644]
bsp3/Designflow/ppr/sim/db/vga.sgdiff.hdb [new file with mode: 0644]
bsp3/Designflow/ppr/sim/db/vga.sld_design_entry.sci [new file with mode: 0644]
bsp3/Designflow/ppr/sim/db/vga.sld_design_entry_dsc.sci [new file with mode: 0644]
bsp3/Designflow/ppr/sim/db/vga.syn_hier_info [new file with mode: 0644]
bsp3/Designflow/ppr/sim/db/vga.tan.qmsg [new file with mode: 0644]
bsp3/Designflow/ppr/sim/db/vga.tis_db_list.ddb [new file with mode: 0644]
bsp3/Designflow/ppr/sim/db/vga.tmw_info [new file with mode: 0644]
bsp3/Designflow/ppr/sim/db/vga_global_asgn_op.abo [new file with mode: 0644]
bsp3/Designflow/ppr/sim/incremental_db/README [new file with mode: 0644]
bsp3/Designflow/ppr/sim/incremental_db/compiled_partitions/vga.root_partition.cmp.atm [new file with mode: 0644]
bsp3/Designflow/ppr/sim/incremental_db/compiled_partitions/vga.root_partition.cmp.dfp [new file with mode: 0644]
bsp3/Designflow/ppr/sim/incremental_db/compiled_partitions/vga.root_partition.cmp.hdbx [new file with mode: 0644]
bsp3/Designflow/ppr/sim/incremental_db/compiled_partitions/vga.root_partition.cmp.kpt [new file with mode: 0644]
bsp3/Designflow/ppr/sim/incremental_db/compiled_partitions/vga.root_partition.cmp.logdb [new file with mode: 0644]
bsp3/Designflow/ppr/sim/incremental_db/compiled_partitions/vga.root_partition.cmp.rcf [new file with mode: 0644]
bsp3/Designflow/ppr/sim/incremental_db/compiled_partitions/vga.root_partition.map.atm [new file with mode: 0644]
bsp3/Designflow/ppr/sim/incremental_db/compiled_partitions/vga.root_partition.map.dpi [new file with mode: 0644]
bsp3/Designflow/ppr/sim/incremental_db/compiled_partitions/vga.root_partition.map.hdbx [new file with mode: 0644]
bsp3/Designflow/ppr/sim/incremental_db/compiled_partitions/vga.root_partition.map.kpt [new file with mode: 0644]
bsp3/Designflow/ppr/sim/simulation/modelsim/vga.sft [new file with mode: 0644]
bsp3/Designflow/ppr/sim/simulation/modelsim/vga.vho [new file with mode: 0644]
bsp3/Designflow/ppr/sim/simulation/modelsim/vga_modelsim.xrf [new file with mode: 0644]
bsp3/Designflow/ppr/sim/simulation/modelsim/vga_vhd.sdo [new file with mode: 0644]
bsp3/Designflow/ppr/sim/vga.asm.rpt [new file with mode: 0644]
bsp3/Designflow/ppr/sim/vga.done [new file with mode: 0644]
bsp3/Designflow/ppr/sim/vga.eda.rpt [new file with mode: 0644]
bsp3/Designflow/ppr/sim/vga.fit.rpt [new file with mode: 0644]
bsp3/Designflow/ppr/sim/vga.fit.smsg [new file with mode: 0644]
bsp3/Designflow/ppr/sim/vga.fit.summary [new file with mode: 0644]
bsp3/Designflow/ppr/sim/vga.flow.rpt [new file with mode: 0644]
bsp3/Designflow/ppr/sim/vga.map.rpt [new file with mode: 0644]
bsp3/Designflow/ppr/sim/vga.map.summary [new file with mode: 0644]
bsp3/Designflow/ppr/sim/vga.pin [new file with mode: 0644]
bsp3/Designflow/ppr/sim/vga.pof [new file with mode: 0644]
bsp3/Designflow/ppr/sim/vga.qpf [new file with mode: 0644]
bsp3/Designflow/ppr/sim/vga.qsf [new file with mode: 0644]
bsp3/Designflow/ppr/sim/vga.qws [new file with mode: 0644]
bsp3/Designflow/ppr/sim/vga.sof [new file with mode: 0644]
bsp3/Designflow/ppr/sim/vga.tan.rpt [new file with mode: 0644]
bsp3/Designflow/ppr/sim/vga.tan.summary [new file with mode: 0644]
bsp3/Designflow/sim/beh/modelsim.ini [new file with mode: 0644]
bsp3/Designflow/sim/beh/vsim.wlf [new file with mode: 0644]
bsp3/Designflow/sim/beh/work/@_opt/__sdf1 [new file with mode: 0644]
bsp3/Designflow/sim/beh/work/@_opt/_deps [new file with mode: 0644]
bsp3/Designflow/sim/beh/work/@_opt/vopt04053w [new file with mode: 0644]
bsp3/Designflow/sim/beh/work/@_opt/vopt17nitb [new file with mode: 0644]
bsp3/Designflow/sim/beh/work/@_opt/vopt1bwwxj [new file with mode: 0644]
bsp3/Designflow/sim/beh/work/@_opt/vopt20mz8t [new file with mode: 0644]
bsp3/Designflow/sim/beh/work/@_opt/vopt2erw8w [new file with mode: 0644]
bsp3/Designflow/sim/beh/work/@_opt/vopt2xexma [new file with mode: 0644]
bsp3/Designflow/sim/beh/work/@_opt/vopt432j07 [new file with mode: 0644]
bsp3/Designflow/sim/beh/work/@_opt/vopt535hk5 [new file with mode: 0644]
bsp3/Designflow/sim/beh/work/@_opt/vopt59rd1y [new file with mode: 0644]
bsp3/Designflow/sim/beh/work/@_opt/vopt5b6dib [new file with mode: 0644]
bsp3/Designflow/sim/beh/work/@_opt/vopt5xncy6 [new file with mode: 0644]
bsp3/Designflow/sim/beh/work/@_opt/vopt68f5gq [new file with mode: 0644]
bsp3/Designflow/sim/beh/work/@_opt/vopt6fnkx3 [new file with mode: 0644]
bsp3/Designflow/sim/beh/work/@_opt/vopt9146qh [new file with mode: 0644]
bsp3/Designflow/sim/beh/work/@_opt/vopt9ht9r4 [new file with mode: 0644]
bsp3/Designflow/sim/beh/work/@_opt/voptba76z6 [new file with mode: 0644]
bsp3/Designflow/sim/beh/work/@_opt/voptbkfv6z [new file with mode: 0644]
bsp3/Designflow/sim/beh/work/@_opt/voptdgkded [new file with mode: 0644]
bsp3/Designflow/sim/beh/work/@_opt/voptgn7ig7 [new file with mode: 0644]
bsp3/Designflow/sim/beh/work/@_opt/voptgna7ah [new file with mode: 0644]
bsp3/Designflow/sim/beh/work/@_opt/vopth6yhv7 [new file with mode: 0644]
bsp3/Designflow/sim/beh/work/@_opt/voptij3j9b [new file with mode: 0644]
bsp3/Designflow/sim/beh/work/@_opt/voptj3mevt [new file with mode: 0644]
bsp3/Designflow/sim/beh/work/@_opt/voptjd08rj [new file with mode: 0644]
bsp3/Designflow/sim/beh/work/@_opt/voptkhne8r [new file with mode: 0644]
bsp3/Designflow/sim/beh/work/@_opt/voptktyxav [new file with mode: 0644]
bsp3/Designflow/sim/beh/work/@_opt/voptm1etmi [new file with mode: 0644]
bsp3/Designflow/sim/beh/work/@_opt/voptmfhq7j [new file with mode: 0644]
bsp3/Designflow/sim/beh/work/@_opt/voptnjyq35 [new file with mode: 0644]
bsp3/Designflow/sim/beh/work/@_opt/voptq7it8b [new file with mode: 0644]
bsp3/Designflow/sim/beh/work/@_opt/voptqh2tzy [new file with mode: 0644]
bsp3/Designflow/sim/beh/work/@_opt/voptqyad50 [new file with mode: 0644]
bsp3/Designflow/sim/beh/work/@_opt/voptr19fy6 [new file with mode: 0644]
bsp3/Designflow/sim/beh/work/@_opt/voptrzt2e4 [new file with mode: 0644]
bsp3/Designflow/sim/beh/work/@_opt/voptsz3qgs [new file with mode: 0644]
bsp3/Designflow/sim/beh/work/@_opt/voptt3f0sq [new file with mode: 0644]
bsp3/Designflow/sim/beh/work/@_opt/voptt3ndg1 [new file with mode: 0644]
bsp3/Designflow/sim/beh/work/@_opt/voptvav2fq [new file with mode: 0644]
bsp3/Designflow/sim/beh/work/@_opt/voptvk0ts7 [new file with mode: 0644]
bsp3/Designflow/sim/beh/work/@_opt/voptwjx9fs [new file with mode: 0644]
bsp3/Designflow/sim/beh/work/@_opt/voptwqdbn1 [new file with mode: 0644]
bsp3/Designflow/sim/beh/work/@_opt/voptx446k4 [new file with mode: 0644]
bsp3/Designflow/sim/beh/work/@_opt/voptxqjv95 [new file with mode: 0644]
bsp3/Designflow/sim/beh/work/@_opt/vopty6s4jf [new file with mode: 0644]
bsp3/Designflow/sim/beh/work/@_opt/voptzf15h2 [new file with mode: 0644]
bsp3/Designflow/sim/beh/work/@_opt/voptzz0c6r [new file with mode: 0644]
bsp3/Designflow/sim/beh/work/@_opt1/_deps [new file with mode: 0644]
bsp3/Designflow/sim/beh/work/@_opt1/vopt0ksshh [new file with mode: 0644]
bsp3/Designflow/sim/beh/work/@_opt1/vopt1f6diy [new file with mode: 0644]
bsp3/Designflow/sim/beh/work/@_opt1/vopt24wzfi [new file with mode: 0644]
bsp3/Designflow/sim/beh/work/@_opt1/vopt3ctid3 [new file with mode: 0644]
bsp3/Designflow/sim/beh/work/@_opt1/vopt3ytti7 [new file with mode: 0644]
bsp3/Designflow/sim/beh/work/@_opt1/vopt5ckg8j [new file with mode: 0644]
bsp3/Designflow/sim/beh/work/@_opt1/vopt6y3ekx [new file with mode: 0644]
bsp3/Designflow/sim/beh/work/@_opt1/vopt7kcgda [new file with mode: 0644]
bsp3/Designflow/sim/beh/work/@_opt1/vopt8w1aec [new file with mode: 0644]
bsp3/Designflow/sim/beh/work/@_opt1/vopt8xjgmn [new file with mode: 0644]
bsp3/Designflow/sim/beh/work/@_opt1/vopt8zrnmv [new file with mode: 0644]
bsp3/Designflow/sim/beh/work/@_opt1/vopt93gx96 [new file with mode: 0644]
bsp3/Designflow/sim/beh/work/@_opt1/vopt946688 [new file with mode: 0644]
bsp3/Designflow/sim/beh/work/@_opt1/vopta7a1h3 [new file with mode: 0644]
bsp3/Designflow/sim/beh/work/@_opt1/vopta9qw5b [new file with mode: 0644]
bsp3/Designflow/sim/beh/work/@_opt1/voptbnw505 [new file with mode: 0644]
bsp3/Designflow/sim/beh/work/@_opt1/voptchqnhv [new file with mode: 0644]
bsp3/Designflow/sim/beh/work/@_opt1/voptf7nhqi [new file with mode: 0644]
bsp3/Designflow/sim/beh/work/@_opt1/vopthd5xvd [new file with mode: 0644]
bsp3/Designflow/sim/beh/work/@_opt1/vopti8zmmt [new file with mode: 0644]
bsp3/Designflow/sim/beh/work/@_opt1/voptiaxeg9 [new file with mode: 0644]
bsp3/Designflow/sim/beh/work/@_opt1/voptj4v2zc [new file with mode: 0644]
bsp3/Designflow/sim/beh/work/@_opt1/voptjm4x1t [new file with mode: 0644]
bsp3/Designflow/sim/beh/work/@_opt1/voptkihv0f [new file with mode: 0644]
bsp3/Designflow/sim/beh/work/@_opt1/voptkm1v6j [new file with mode: 0644]
bsp3/Designflow/sim/beh/work/@_opt1/voptkmiaa7 [new file with mode: 0644]
bsp3/Designflow/sim/beh/work/@_opt1/voptmrzat9 [new file with mode: 0644]
bsp3/Designflow/sim/beh/work/@_opt1/voptmxz0ht [new file with mode: 0644]
bsp3/Designflow/sim/beh/work/@_opt1/voptnm1zts [new file with mode: 0644]
bsp3/Designflow/sim/beh/work/@_opt1/voptnndw8s [new file with mode: 0644]
bsp3/Designflow/sim/beh/work/@_opt1/voptqi9gfb [new file with mode: 0644]
bsp3/Designflow/sim/beh/work/@_opt1/voptr3m01f [new file with mode: 0644]
bsp3/Designflow/sim/beh/work/@_opt1/voptsh2kbc [new file with mode: 0644]
bsp3/Designflow/sim/beh/work/@_opt1/voptwki2a0 [new file with mode: 0644]
bsp3/Designflow/sim/beh/work/@_opt1/voptwkkqyn [new file with mode: 0644]
bsp3/Designflow/sim/beh/work/@_opt1/voptwnvnyc [new file with mode: 0644]
bsp3/Designflow/sim/beh/work/@_opt1/voptx2ga7e [new file with mode: 0644]
bsp3/Designflow/sim/beh/work/@_opt1/voptx9sws4 [new file with mode: 0644]
bsp3/Designflow/sim/beh/work/@_opt1/voptynr0w7 [new file with mode: 0644]
bsp3/Designflow/sim/beh/work/@_opt1/voptz2bt1c [new file with mode: 0644]
bsp3/Designflow/sim/beh/work/@_opt1/voptz5k8xq [new file with mode: 0644]
bsp3/Designflow/sim/beh/work/@_opt1/voptzz5eq3 [new file with mode: 0644]
bsp3/Designflow/sim/beh/work/_info [new file with mode: 0644]
bsp3/Designflow/sim/beh/work/_vmake [new file with mode: 0644]
bsp3/Designflow/sim/beh/work/board_driver/_primary.dat [new file with mode: 0644]
bsp3/Designflow/sim/beh/work/board_driver/_primary.dbs [new file with mode: 0644]
bsp3/Designflow/sim/beh/work/board_driver/behav.dat [new file with mode: 0644]
bsp3/Designflow/sim/beh/work/board_driver/behav.dbs [new file with mode: 0644]
bsp3/Designflow/sim/beh/work/vga/_primary.dat [new file with mode: 0644]
bsp3/Designflow/sim/beh/work/vga/_primary.dbs [new file with mode: 0644]
bsp3/Designflow/sim/beh/work/vga/behav.dat [new file with mode: 0644]
bsp3/Designflow/sim/beh/work/vga/behav.dbs [new file with mode: 0644]
bsp3/Designflow/sim/beh/work/vga_conf_beh/_primary.dat [new file with mode: 0644]
bsp3/Designflow/sim/beh/work/vga_conf_beh/_primary.dbs [new file with mode: 0644]
bsp3/Designflow/sim/beh/work/vga_control/_primary.dat [new file with mode: 0644]
bsp3/Designflow/sim/beh/work/vga_control/_primary.dbs [new file with mode: 0644]
bsp3/Designflow/sim/beh/work/vga_control/behav.dat [new file with mode: 0644]
bsp3/Designflow/sim/beh/work/vga_control/behav.dbs [new file with mode: 0644]
bsp3/Designflow/sim/beh/work/vga_driver/_primary.dat [new file with mode: 0644]
bsp3/Designflow/sim/beh/work/vga_driver/_primary.dbs [new file with mode: 0644]
bsp3/Designflow/sim/beh/work/vga_driver/behav.dat [new file with mode: 0644]
bsp3/Designflow/sim/beh/work/vga_driver/behav.dbs [new file with mode: 0644]
bsp3/Designflow/sim/beh/work/vga_pak/_primary.dat [new file with mode: 0644]
bsp3/Designflow/sim/beh/work/vga_pak/_primary.dbs [new file with mode: 0644]
bsp3/Designflow/sim/beh/work/vga_tb/_primary.dat [new file with mode: 0644]
bsp3/Designflow/sim/beh/work/vga_tb/_primary.dbs [new file with mode: 0644]
bsp3/Designflow/sim/beh/work/vga_tb/behaviour.dat [new file with mode: 0644]
bsp3/Designflow/sim/beh/work/vga_tb/behaviour.dbs [new file with mode: 0644]
bsp3/Designflow/sim/post/modelsim.ini [new file with mode: 0644]
bsp3/Designflow/sim/post/vsim.wlf [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/__sdf1 [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/_deps [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopt04g9zr [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopt0775gz [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopt0ecc2w [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopt0ihnm0 [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopt0mft48 [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopt0mksmh [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopt0rc3m1 [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopt0t26b3 [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopt0t7tzn [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopt110x3c [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopt13n14v [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopt18d7i9 [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopt18vb0r [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopt1a6tfd [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopt1agceg [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopt1f9yqb [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopt1he2aw [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopt1q9yzv [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopt1rxnye [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopt1y85nx [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopt1zs9t3 [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopt206keg [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopt20bi9h [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopt21agm6 [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopt25ed5c [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopt274nvn [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopt27sqdt [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopt2dc332 [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopt2e8c94 [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopt2f3a0x [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopt2j5bkg [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopt2mhxts [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopt2n4d8r [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopt2ydh57 [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopt2zz0w8 [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopt32qnct [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopt35k5wn [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopt3cfxrm [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopt3kd3wc [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopt3n9xvk [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopt3s62qk [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopt3v2cwx [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopt40shqr [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopt466cvr [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopt478w7a [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopt4b2e0j [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopt4h7x0t [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopt4qq65j [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopt4rb1ts [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopt4tekwx [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopt4ttffc [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopt4zyxm4 [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopt5287sw [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopt52eq6n [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopt55g40n [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopt5gtiwz [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopt5k57cn [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopt5si1tq [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopt68a3cn [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopt6as2k8 [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopt6i91n9 [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopt6iehg9 [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopt6nbb7g [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopt6nhxfn [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopt6rhy0e [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopt6w3eqg [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopt6wr2ez [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopt70fsca [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopt716s76 [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopt71gszc [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopt785ncr [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopt7dmrts [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopt7dw2jd [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopt7hs9d2 [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopt7ndivd [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopt7y2es7 [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopt7y4h7c [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopt7y5y26 [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopt80kb6s [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopt85cx2g [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopt8bvh4c [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopt8e77ct [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopt8ij05x [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopt8j0mtg [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopt8k66qj [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopt8m56re [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopt8ng6xh [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopt8njaqt [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopt8yhe3w [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopt8ziwrw [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopt95ij4a [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopt9a1jxm [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopt9d1qrj [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopt9h8r68 [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopt9knfnt [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopt9ks3v6 [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopt9kvygh [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopt9rw4ta [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopt9vfz01 [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopt9xxyy1 [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopta3vqte [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopta6gskx [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptajhv81 [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptasd3s8 [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptb1fbks [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptbbfkjn [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptbe3c1g [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptbehey2 [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptbeq6gd [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptbr95i6 [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptbrg3gz [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptbsx1xs [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptbtfiwb [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptbycmqt [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptbzgbat [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptc2vmiz [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptc5c5bq [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptc745ki [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptccnfkd [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptcmsfjz [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptcq3297 [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptczegea [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptd0tja7 [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptd2nx7v [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptda9n7k [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptde43s5 [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptdgzq4m [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptdt1kqd [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopte38ew9 [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopte3c0b8 [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopte6bm43 [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopte6tw9f [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopte6vewz [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopte7cdjw [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptec5k4k [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopted2bjz [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptee9zbv [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptehc8qt [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptemmexf [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptenvrm7 [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopteq3s6b [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptervh7c [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptexb4sn [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptf3xim8 [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptfbjxgg [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptfd96yv [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptfg8mkb [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptfgziqm [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptfjdkq2 [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptfnzcsx [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptfqwwnk [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptfwwe01 [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptg33dir [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptg4a5e2 [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptg5gxf2 [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptg98wsq [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptg9hyxh [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptgehny4 [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptgf4fb8 [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptgfmnqn [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptggzebt [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptgq2ee5 [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptgrj5dx [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptgt7ck1 [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptgv1vae [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptgw96k6 [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptgx98fc [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopth0r1q1 [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopthf9fm2 [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopthh22i5 [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopthi1hkx [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopthi41g1 [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopthqq36t [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopthsj9c1 [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopti1hrgb [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopti30km4 [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopti7sxxb [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopti7trii [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptidh34d [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptizkix2 [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptj02i77 [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptj2vmsh [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptj4ige9 [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptj6g9r7 [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptj8iea1 [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptjc0ms0 [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptjf2mg0 [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptjh5m3n [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptjhbvq1 [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptjmz2fq [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptjrba9g [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptk299q0 [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptk3m8eg [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptk71at1 [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptka4h5r [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptkfq0ks [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptkik6hi [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptkjcf41 [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptkk7zn7 [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptknakms [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptkwfg7b [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptm289ge [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptm2tjnz [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptm5rsfd [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptm788y2 [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptmas2y3 [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptmbqb5s [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptmc2amk [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptmenshy [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptmfsea8 [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptmhrw9j [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptn99e2j [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptngrjm4 [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptnsszm7 [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptq0ijic [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptq3cbn0 [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptq6jizj [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptq758xd [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptq8x19g [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptq9jyiy [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptqbtaqb [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptqe37id [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptqizctz [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptqra3gr [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptqzq8en [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptr0v6kq [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptr6403x [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptrcqggt [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptrehctx [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptrgin7n [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptrh7jg3 [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptrkqkb6 [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptrqqi3r [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptrqy1ym [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptrtgskv [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptrtj0ec [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopts7vksi [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptsj7ma9 [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptsmgy31 [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptsmwm69 [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptt00gdd [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptt3acvn [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptt5ebyt [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptt8w0rj [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopttdxxj4 [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopttehte1 [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopttf098e [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopttjxskh [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptts38h1 [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopttwr2kt [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopttx2t7a [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopttyy3mx [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopttzmffh [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptv0zb1d [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptv63t1g [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptv9yyfx [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptvbs1k9 [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptvee1bs [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptvgh3x6 [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptvhifra [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptvi2hi3 [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptvjvbjr [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptvkq1q6 [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptvn0yh7 [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptvr74r3 [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptvstekn [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptvxwhvk [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptw0q5q4 [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptw3zvzg [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptwcraje [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptwdeqf8 [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptwj1h56 [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptwn8bd8 [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptx1a26g [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptxcxqtx [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptxdahza [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptxj446w [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptxy0mgt [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopty4nqz9 [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/vopty9tfij [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptyhmtbi [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptyhngfr [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptykrs0a [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptymsefg [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptyn1f5j [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptyqya85 [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptyrwyt3 [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptyskb8t [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptz3jt2s [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptza8gh6 [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptzcy49x [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptzgnc75 [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptznc0g5 [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptzww4tv [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptzwzy11 [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptzy6fxn [new file with mode: 0644]
bsp3/Designflow/sim/post/work/@_opt/voptzztzz4 [new file with mode: 0644]
bsp3/Designflow/sim/post/work/_info [new file with mode: 0644]
bsp3/Designflow/sim/post/work/_vmake [new file with mode: 0644]
bsp3/Designflow/sim/post/work/vga/_primary.dat [new file with mode: 0644]
bsp3/Designflow/sim/post/work/vga/_primary.dbs [new file with mode: 0644]
bsp3/Designflow/sim/post/work/vga/structure.dat [new file with mode: 0644]
bsp3/Designflow/sim/post/work/vga/structure.dbs [new file with mode: 0644]
bsp3/Designflow/sim/post/work/vga_conf_pos/_primary.dat [new file with mode: 0644]
bsp3/Designflow/sim/post/work/vga_conf_pos/_primary.dbs [new file with mode: 0644]
bsp3/Designflow/sim/post/work/vga_pak/_primary.dat [new file with mode: 0644]
bsp3/Designflow/sim/post/work/vga_pak/_primary.dbs [new file with mode: 0644]
bsp3/Designflow/sim/post/work/vga_pos_tb/_primary.dat [new file with mode: 0644]
bsp3/Designflow/sim/post/work/vga_pos_tb/_primary.dbs [new file with mode: 0644]
bsp3/Designflow/sim/post/work/vga_pos_tb/structure.dat [new file with mode: 0644]
bsp3/Designflow/sim/post/work/vga_pos_tb/structure.dbs [new file with mode: 0644]
bsp3/Designflow/sim/pre/modelsim.ini [new file with mode: 0644]
bsp3/Designflow/sim/pre/vsim.wlf [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/_deps [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/vopt0am9rm [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/vopt0i6c4w [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/vopt0k8345 [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/vopt0x4vyk [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/vopt0y2684 [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/vopt10awzd [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/vopt122z3y [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/vopt12wqt0 [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/vopt13sgc7 [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/vopt1aknqe [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/vopt1bf2vs [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/vopt1vm71y [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/vopt1vx7wc [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/vopt1wgqi9 [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/vopt20fb7q [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/vopt2ba2c6 [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/vopt2dqh6v [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/vopt2zz7n9 [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/vopt304sfh [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/vopt3adrmf [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/vopt3e4dc2 [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/vopt3h1taq [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/vopt3vm89b [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/vopt3vnm8t [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/vopt3vvqwi [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/vopt42chjt [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/vopt42jzcw [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/vopt46cyae [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/vopt48vm08 [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/vopt48wi2g [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/vopt4bmgcy [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/vopt4c55m9 [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/vopt4e60zb [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/vopt4gr2v9 [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/vopt4mzriq [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/vopt4q83sz [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/vopt4xtadv [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/vopt4yx10q [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/vopt4zc1kg [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/vopt51t5y6 [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/vopt55sjrn [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/vopt5n887w [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/vopt5qd302 [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/vopt5twm9e [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/vopt65v1sn [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/vopt6c7vre [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/vopt6dq9se [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/vopt6g26rn [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/vopt6gi0b5 [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/vopt6kfx6i [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/vopt6tze3s [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/vopt73vatx [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/vopt7fs99w [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/vopt7ja1s8 [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/vopt7njjhw [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/vopt7s1sw6 [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/vopt7xgg6h [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/vopt7ykvec [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/vopt8fgnja [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/vopt8hk0km [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/vopt8kw9m0 [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/vopt8ngb3w [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/vopt8q3htk [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/vopt8q7wss [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/vopt8qmdq9 [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/vopt8s49cb [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/vopt8zw982 [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/vopt903g6g [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/vopt9mdbfh [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/vopt9tii6m [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/vopt9xs68h [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/vopta3ata3 [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/vopta5hbfq [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/voptaabh4z [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/voptae9fw2 [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/voptaek2j6 [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/voptahtanj [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/voptajrs74 [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/voptak99fc [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/voptaxk6y6 [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/voptb84s9f [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/voptbc3ayg [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/voptbhb8ir [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/voptbin7c8 [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/voptbj57q5 [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/voptbt7y2r [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/voptbw5av9 [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/voptc2ewey [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/voptcatdcf [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/voptceddes [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/voptcr2z7y [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/voptcw5jcx [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/voptd42wzn [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/voptd73ncv [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/voptd8q1ti [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/voptd9eszt [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/voptdwtd08 [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/vopte3by5t [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/vopterjbne [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/voptewzwms [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/voptey6j55 [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/voptfzexn2 [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/voptg3itef [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/voptgfc83c [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/voptgh694y [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/voptgj09sr [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/voptgjk5ib [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/voptgkfeyz [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/voptgkx96a [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/voptgneik3 [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/voptgwdknb [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/vopth0mvka [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/vopth1bexi [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/vopth31iw4 [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/vopth7wx3g [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/vopthbfncq [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/vopthd5jm4 [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/vopthecd8z [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/vopthizaii [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/vopthsw3di [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/vopti8yvt9 [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/voptie06aa [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/voptimd8rb [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/voptinhwyy [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/voptirch1m [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/voptiyswhn [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/voptj3k9ec [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/voptj5ya8z [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/voptj942ct [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/voptjf2x9t [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/voptjm2qv3 [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/voptjq05ys [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/voptk8baxb [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/voptkcdgj2 [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/voptke28ta [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/voptke9xx5 [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/voptkfv4jx [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/voptksgd04 [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/voptkt39i1 [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/voptkw9jq2 [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/voptkyb7ay [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/voptmczyb8 [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/voptmehdfj [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/voptmf1ksc [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/voptmfqanq [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/voptmr3by9 [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/voptms89dz [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/voptmt092v [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/voptmty6w0 [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/voptn4tie8 [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/voptn6hhj8 [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/voptncvj5h [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/voptnfbheh [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/voptni0j2s [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/voptnt9fe1 [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/voptnvr0kz [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/voptnx8gdn [new file with mode: 0644]
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bsp3/Designflow/sim/pre/work/@_opt/voptq0rt1m [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/voptq5yz3e [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/voptqaa3k2 [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/voptqax3fm [new file with mode: 0644]
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bsp3/Designflow/sim/pre/work/@_opt/voptqj2cd6 [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/voptqr9n0q [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/voptrwv5rc [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/voptrzm7y3 [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/vopts7w6rz [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/vopts7yrmd [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/voptsbtefi [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/voptsby5g2 [new file with mode: 0644]
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bsp3/Designflow/sim/pre/work/@_opt/vopttjnesc [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/vopttt6738 [new file with mode: 0644]
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bsp3/Designflow/sim/pre/work/@_opt/voptv6wd4a [new file with mode: 0644]
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bsp3/Designflow/sim/pre/work/@_opt/voptzfr2yb [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/@_opt/voptzv8bv1 [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/_info [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/_vmake [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/vga/_primary.dat [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/vga/_primary.dbs [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/vga/beh.dat [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/vga/beh.dbs [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/vga_conf_pre/_primary.dat [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/vga_conf_pre/_primary.dbs [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/vga_control/_primary.dat [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/vga_control/_primary.dbs [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/vga_control/beh.dat [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/vga_control/beh.dbs [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/vga_driver/_primary.dat [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/vga_driver/_primary.dbs [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/vga_driver/beh.dat [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/vga_driver/beh.dbs [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/vga_pak/_primary.dat [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/vga_pak/_primary.dbs [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/vga_pre_tb/_primary.dat [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/vga_pre_tb/_primary.dbs [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/vga_pre_tb/structure.dat [new file with mode: 0644]
bsp3/Designflow/sim/pre/work/vga_pre_tb/structure.dbs [new file with mode: 0644]
bsp3/Designflow/src/board_driver_arc.vhd [new file with mode: 0644]
bsp3/Designflow/src/board_driver_ent.vhd [new file with mode: 0644]
bsp3/Designflow/src/dide_16_3.txt [new file with mode: 0644]
bsp3/Designflow/src/vga_arc.vhd [new file with mode: 0755]
bsp3/Designflow/src/vga_beh_tb.vhd [new file with mode: 0644]
bsp3/Designflow/src/vga_control_arc.vhd [new file with mode: 0644]
bsp3/Designflow/src/vga_control_ent.vhd [new file with mode: 0644]
bsp3/Designflow/src/vga_driver_arc.vhd [new file with mode: 0644]
bsp3/Designflow/src/vga_driver_ent.vhd [new file with mode: 0644]
bsp3/Designflow/src/vga_ent.vhd [new file with mode: 0644]
bsp3/Designflow/src/vga_pak.vhd [new file with mode: 0644]
bsp3/Designflow/src/vga_pll.bdf [new file with mode: 0755]
bsp3/Designflow/src/vga_pll.tcl [new file with mode: 0755]
bsp3/Designflow/src/vga_pos_tb.vhd [new file with mode: 0644]
bsp3/Designflow/src/vga_pre_tb.vhd [new file with mode: 0644]
bsp3/Designflow/src/vpll.bsf [new file with mode: 0644]
bsp3/Designflow/src/vpll.vhd [new file with mode: 0644]
bsp3/Designflow/syn/rev_1/.recordref [new file with mode: 0644]
bsp3/Designflow/syn/rev_1/backup/vga.srr [new file with mode: 0644]
bsp3/Designflow/syn/rev_1/rpt_vga.areasrr [new file with mode: 0644]
bsp3/Designflow/syn/rev_1/rpt_vga_areasrr.htm [new file with mode: 0644]
bsp3/Designflow/syn/rev_1/run_options.txt [new file with mode: 0644]
bsp3/Designflow/syn/rev_1/scratchproject.prs [new file with mode: 0644]
bsp3/Designflow/syn/rev_1/syntmp/sap_log_flink.htm [new file with mode: 0644]
bsp3/Designflow/syn/rev_1/syntmp/sap_log_srr.htm [new file with mode: 0644]
bsp3/Designflow/syn/rev_1/syntmp/vga.msg [new file with mode: 0644]
bsp3/Designflow/syn/rev_1/syntmp/vga.plg [new file with mode: 0644]
bsp3/Designflow/syn/rev_1/syntmp/vga_cons_ui.tcl [new file with mode: 0644]
bsp3/Designflow/syn/rev_1/syntmp/vga_driver_arc_flink.htm [new file with mode: 0644]
bsp3/Designflow/syn/rev_1/syntmp/vga_flink.htm [new file with mode: 0644]
bsp3/Designflow/syn/rev_1/syntmp/vga_srr.htm [new file with mode: 0644]
bsp3/Designflow/syn/rev_1/syntmp/vga_toc.htm [new file with mode: 0644]
bsp3/Designflow/syn/rev_1/verif/vga.vif [new file with mode: 0644]
bsp3/Designflow/syn/rev_1/vga.fse [new file with mode: 0644]
bsp3/Designflow/syn/rev_1/vga.htm [new file with mode: 0644]
bsp3/Designflow/syn/rev_1/vga.map [new file with mode: 0644]
bsp3/Designflow/syn/rev_1/vga.sap [new file with mode: 0644]
bsp3/Designflow/syn/rev_1/vga.srd [new file with mode: 0644]
bsp3/Designflow/syn/rev_1/vga.srm [new file with mode: 0644]
bsp3/Designflow/syn/rev_1/vga.srr [new file with mode: 0644]
bsp3/Designflow/syn/rev_1/vga.srs [new file with mode: 0644]
bsp3/Designflow/syn/rev_1/vga.sxr [new file with mode: 0644]
bsp3/Designflow/syn/rev_1/vga.szr [new file with mode: 0644]
bsp3/Designflow/syn/rev_1/vga.tcl [new file with mode: 0644]
bsp3/Designflow/syn/rev_1/vga.tlg [new file with mode: 0644]
bsp3/Designflow/syn/rev_1/vga.vhm [new file with mode: 0644]
bsp3/Designflow/syn/rev_1/vga.vqm [new file with mode: 0644]
bsp3/Designflow/syn/rev_1/vga.xrf [new file with mode: 0644]
bsp3/Designflow/syn/rev_1/vga_cons.tcl [new file with mode: 0644]
bsp3/Designflow/syn/rev_1/vga_rm.tcl [new file with mode: 0644]
bsp3/Designflow/syn/vga.prd [new file with mode: 0644]
bsp3/Designflow/syn/vga.prj [new file with mode: 0644]
bsp3/Protokolle/pics/1behsim.png [new file with mode: 0644]
bsp3/Protokolle/pics/3pre-sim.png [new file with mode: 0644]
bsp3/Protokolle/pics/3pre-sim_2.png [new file with mode: 0644]
bsp3/Protokolle/pics/5postlayout1.png [new file with mode: 0644]
bsp3/Protokolle/pics/5postlayout2.png [new file with mode: 0644]
bsp3/Protokolle/pics/7auslastung.png [new file with mode: 0644]
bsp3/Protokolle/pics/logik.JPG [new file with mode: 0644]

diff --git a/bsp3/Designflow/ppr/download/db/vga_pll.(0).cnf.cdb b/bsp3/Designflow/ppr/download/db/vga_pll.(0).cnf.cdb
new file mode 100644 (file)
index 0000000..8f16c2e
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diff --git a/bsp3/Designflow/ppr/download/db/vga_pll.(0).cnf.hdb b/bsp3/Designflow/ppr/download/db/vga_pll.(0).cnf.hdb
new file mode 100644 (file)
index 0000000..ccea43a
Binary files /dev/null and b/bsp3/Designflow/ppr/download/db/vga_pll.(0).cnf.hdb differ
diff --git a/bsp3/Designflow/ppr/download/db/vga_pll.(1).cnf.cdb b/bsp3/Designflow/ppr/download/db/vga_pll.(1).cnf.cdb
new file mode 100644 (file)
index 0000000..0b51743
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diff --git a/bsp3/Designflow/ppr/download/db/vga_pll.(1).cnf.hdb b/bsp3/Designflow/ppr/download/db/vga_pll.(1).cnf.hdb
new file mode 100644 (file)
index 0000000..abf453a
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diff --git a/bsp3/Designflow/ppr/download/db/vga_pll.(2).cnf.cdb b/bsp3/Designflow/ppr/download/db/vga_pll.(2).cnf.cdb
new file mode 100644 (file)
index 0000000..cbb77cc
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diff --git a/bsp3/Designflow/ppr/download/db/vga_pll.(2).cnf.hdb b/bsp3/Designflow/ppr/download/db/vga_pll.(2).cnf.hdb
new file mode 100644 (file)
index 0000000..ae66b06
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diff --git a/bsp3/Designflow/ppr/download/db/vga_pll.(3).cnf.cdb b/bsp3/Designflow/ppr/download/db/vga_pll.(3).cnf.cdb
new file mode 100644 (file)
index 0000000..d134112
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diff --git a/bsp3/Designflow/ppr/download/db/vga_pll.(3).cnf.hdb b/bsp3/Designflow/ppr/download/db/vga_pll.(3).cnf.hdb
new file mode 100644 (file)
index 0000000..ad58a28
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diff --git a/bsp3/Designflow/ppr/download/db/vga_pll.(4).cnf.cdb b/bsp3/Designflow/ppr/download/db/vga_pll.(4).cnf.cdb
new file mode 100644 (file)
index 0000000..e7e2dc1
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diff --git a/bsp3/Designflow/ppr/download/db/vga_pll.(4).cnf.hdb b/bsp3/Designflow/ppr/download/db/vga_pll.(4).cnf.hdb
new file mode 100644 (file)
index 0000000..fe00fe9
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diff --git a/bsp3/Designflow/ppr/download/db/vga_pll.(5).cnf.cdb b/bsp3/Designflow/ppr/download/db/vga_pll.(5).cnf.cdb
new file mode 100644 (file)
index 0000000..4b16a59
Binary files /dev/null and b/bsp3/Designflow/ppr/download/db/vga_pll.(5).cnf.cdb differ
diff --git a/bsp3/Designflow/ppr/download/db/vga_pll.(5).cnf.hdb b/bsp3/Designflow/ppr/download/db/vga_pll.(5).cnf.hdb
new file mode 100644 (file)
index 0000000..1e9ea30
Binary files /dev/null and b/bsp3/Designflow/ppr/download/db/vga_pll.(5).cnf.hdb differ
diff --git a/bsp3/Designflow/ppr/download/db/vga_pll.asm.qmsg b/bsp3/Designflow/ppr/download/db/vga_pll.asm.qmsg
new file mode 100644 (file)
index 0000000..50bf0cb
--- /dev/null
@@ -0,0 +1,5 @@
+{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 132 02/25/2009 SJ Full Version " "Info: Version 9.0 Build 132 02/25/2009 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Thu Oct 29 17:13:07 2009 " "Info: Processing started: Thu Oct 29 17:13:07 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off vga_pll -c vga_pll " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off vga_pll -c vga_pll" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" {  } {  } 0 0 "Assembler is generating device programming files" 0 0 "" 0 -1}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "269 " "Info: Peak virtual memory: 269 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Thu Oct 29 17:13:25 2009 " "Info: Processing ended: Thu Oct 29 17:13:25 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:18 " "Info: Elapsed time: 00:00:18" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:18 " "Info: Total CPU time (on all processors): 00:00:18" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
diff --git a/bsp3/Designflow/ppr/download/db/vga_pll.cbx.xml b/bsp3/Designflow/ppr/download/db/vga_pll.cbx.xml
new file mode 100644 (file)
index 0000000..0c82b90
--- /dev/null
@@ -0,0 +1,5 @@
+<?xml version="1.0" ?>
+<LOG_ROOT>
+       <PROJECT NAME="vga_pll">
+       </PROJECT>
+</LOG_ROOT>
diff --git a/bsp3/Designflow/ppr/download/db/vga_pll.cmp.cdb b/bsp3/Designflow/ppr/download/db/vga_pll.cmp.cdb
new file mode 100644 (file)
index 0000000..e3d063a
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diff --git a/bsp3/Designflow/ppr/download/db/vga_pll.cmp.hdb b/bsp3/Designflow/ppr/download/db/vga_pll.cmp.hdb
new file mode 100644 (file)
index 0000000..ffd3645
Binary files /dev/null and b/bsp3/Designflow/ppr/download/db/vga_pll.cmp.hdb differ
diff --git a/bsp3/Designflow/ppr/download/db/vga_pll.cmp.kpt b/bsp3/Designflow/ppr/download/db/vga_pll.cmp.kpt
new file mode 100644 (file)
index 0000000..77fe779
--- /dev/null
@@ -0,0 +1,10 @@
+<kpt_db name="vga_pll.cmp" kpt_version="1.1">
+  <key_points_set type="reference" hier_sep="|">
+  </key_points_set>
+  <key_points_set type="transition" hier_sep="|">
+  </key_points_set>
+  <key_points_set type="transformed" hier_sep="|">
+  </key_points_set>
+  <transformations_set hier_sep="|">
+  </transformations_set>
+</kpt_db>
diff --git a/bsp3/Designflow/ppr/download/db/vga_pll.cmp.logdb b/bsp3/Designflow/ppr/download/db/vga_pll.cmp.logdb
new file mode 100644 (file)
index 0000000..626799f
--- /dev/null
@@ -0,0 +1 @@
+v1
diff --git a/bsp3/Designflow/ppr/download/db/vga_pll.cmp.rdb b/bsp3/Designflow/ppr/download/db/vga_pll.cmp.rdb
new file mode 100644 (file)
index 0000000..9f8caac
Binary files /dev/null and b/bsp3/Designflow/ppr/download/db/vga_pll.cmp.rdb differ
diff --git a/bsp3/Designflow/ppr/download/db/vga_pll.cmp.tdb b/bsp3/Designflow/ppr/download/db/vga_pll.cmp.tdb
new file mode 100644 (file)
index 0000000..e244402
Binary files /dev/null and b/bsp3/Designflow/ppr/download/db/vga_pll.cmp.tdb differ
diff --git a/bsp3/Designflow/ppr/download/db/vga_pll.cmp0.ddb b/bsp3/Designflow/ppr/download/db/vga_pll.cmp0.ddb
new file mode 100644 (file)
index 0000000..4237f13
Binary files /dev/null and b/bsp3/Designflow/ppr/download/db/vga_pll.cmp0.ddb differ
diff --git a/bsp3/Designflow/ppr/download/db/vga_pll.db_info b/bsp3/Designflow/ppr/download/db/vga_pll.db_info
new file mode 100644 (file)
index 0000000..d0b3ea7
--- /dev/null
@@ -0,0 +1,3 @@
+Quartus_Version = Version 9.0 Build 132 02/25/2009 SJ Full Version
+Version_Index = 167805952
+Creation_Time = Thu Oct 29 17:11:00 2009
diff --git a/bsp3/Designflow/ppr/download/db/vga_pll.eco.cdb b/bsp3/Designflow/ppr/download/db/vga_pll.eco.cdb
new file mode 100644 (file)
index 0000000..a488d53
Binary files /dev/null and b/bsp3/Designflow/ppr/download/db/vga_pll.eco.cdb differ
diff --git a/bsp3/Designflow/ppr/download/db/vga_pll.eda.qmsg b/bsp3/Designflow/ppr/download/db/vga_pll.eda.qmsg
new file mode 100644 (file)
index 0000000..3d743ec
--- /dev/null
@@ -0,0 +1,5 @@
+{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II " "Info: Running Quartus II EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 132 02/25/2009 SJ Full Version " "Info: Version 9.0 Build 132 02/25/2009 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Thu Oct 29 17:13:31 2009 " "Info: Processing started: Thu Oct 29 17:13:31 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off vga_pll -c vga_pll " "Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off vga_pll -c vga_pll" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
+{ "Info" "IWSC_DONE_HDL_SDO_GENERATION" "vga_pll.vo vga_pll_v.sdo /homes/burban/didelu/dide_16/bsp3/Designflow/ppr/download/simulation/modelsim/ simulation " "Info: Generated files \"vga_pll.vo\" and \"vga_pll_v.sdo\" in directory \"/homes/burban/didelu/dide_16/bsp3/Designflow/ppr/download/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 0 "Generated files \"%1!s!\" and \"%2!s!\" in directory \"%3!s!\" for EDA %4!s! tool" 0 0 "" 0 -1}
+{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 0 s Quartus II " "Info: Quartus II EDA Netlist Writer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "162 " "Info: Peak virtual memory: 162 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Thu Oct 29 17:13:32 2009 " "Info: Processing ended: Thu Oct 29 17:13:32 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
diff --git a/bsp3/Designflow/ppr/download/db/vga_pll.fit.qmsg b/bsp3/Designflow/ppr/download/db/vga_pll.fit.qmsg
new file mode 100644 (file)
index 0000000..dd256f3
--- /dev/null
@@ -0,0 +1,51 @@
+{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 132 02/25/2009 SJ Full Version " "Info: Version 9.0 Build 132 02/25/2009 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Thu Oct 29 17:12:35 2009 " "Info: Processing started: Thu Oct 29 17:12:35 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off vga_pll -c vga_pll " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off vga_pll -c vga_pll" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Info: Parallel compilation is enabled and will use 2 of the 2 processors detected" {  } {  } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1}
+{ "Info" "IMPP_MPP_USER_DEVICE" "vga_pll EP1S25F672C6 " "Info: Selected device EP1S25F672C6 for design \"vga_pll\"" {  } {  } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0 "" 0 -1}
+{ "Warning" "WCUT_CUT_YGR_PLL_BAD_FANOUT_CLK3" "clk0 vpll:inst1\|altpll:altpll_component\|pll " "Warning: Output port clk0 of PLL \"vpll:inst1\|altpll:altpll_component\|pll\" feeds an output pin via global clocks -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance" {  } { { "altpll.tdf" "" { Text "/opt/quartus/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } } { "../../src/vpll.vhd" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/src/vpll.vhd" 121 0 0 } } { "../../src/vga_pll.bdf" "" { Schematic "/homes/burban/didelu/dide_16/bsp3/Designflow/src/vga_pll.bdf" { { 56 408 504 152 "inst1" "" } } } }  } 0 0 "Output port %1!s! of PLL \"%2!s!\" feeds an output pin via global clocks -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance" 0 0 "" 0 -1}
+{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "" 0 -1}
+{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1S10F672C6 " "Info: Device EP1S10F672C6 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1S20F672C6 " "Info: Device EP1S20F672C6 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1S25F672C6_HARDCOPY_FPGA_PROTOTYPE " "Info: Device EP1S25F672C6_HARDCOPY_FPGA_PROTOTYPE is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1}  } {  } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "" 0 -1}
+{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "1 " "Info: Fitter converted 1 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~DATA0~ F16 " "Info: Pin ~DATA0~ is reserved at location F16" {  } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { ~DATA0~ } } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~DATA0~ } "NODE_NAME" } }  } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "" 0 -1}
+{ "Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "12 91 " "Warning: No exact pin location assignment(s) for 12 pins of 91 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_hsync_counter\[6\] " "Info: Pin d_hsync_counter\[6\] not assigned to an exact location on the device" {  } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_hsync_counter[6] } } } { "/opt/quartus/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/quartus/quartus/linux/Assignment Editor.qase" 1 { { 0 "d_hsync_counter\[6\]" } } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 4076 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_hsync_counter[6] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_hsync_counter\[5\] " "Info: Pin d_hsync_counter\[5\] not assigned to an exact location on the device" {  } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_hsync_counter[5] } } } { "/opt/quartus/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/quartus/quartus/linux/Assignment Editor.qase" 1 { { 0 "d_hsync_counter\[5\]" } } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 4089 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_hsync_counter[5] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_hsync_counter\[4\] " "Info: Pin d_hsync_counter\[4\] not assigned to an exact location on the device" {  } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_hsync_counter[4] } } } { "/opt/quartus/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/quartus/quartus/linux/Assignment Editor.qase" 1 { { 0 "d_hsync_counter\[4\]" } } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 4102 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_hsync_counter[4] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_hsync_counter\[3\] " "Info: Pin d_hsync_counter\[3\] not assigned to an exact location on the device" {  } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_hsync_counter[3] } } } { "/opt/quartus/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/quartus/quartus/linux/Assignment Editor.qase" 1 { { 0 "d_hsync_counter\[3\]" } } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 4115 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_hsync_counter[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_hsync_counter\[2\] " "Info: Pin d_hsync_counter\[2\] not assigned to an exact location on the device" {  } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_hsync_counter[2] } } } { "/opt/quartus/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/quartus/quartus/linux/Assignment Editor.qase" 1 { { 0 "d_hsync_counter\[2\]" } } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 4128 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_hsync_counter[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_hsync_counter\[1\] " "Info: Pin d_hsync_counter\[1\] not assigned to an exact location on the device" {  } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_hsync_counter[1] } } } { "/opt/quartus/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/quartus/quartus/linux/Assignment Editor.qase" 1 { { 0 "d_hsync_counter\[1\]" } } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 4141 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_hsync_counter[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_vsync_counter\[6\] " "Info: Pin d_vsync_counter\[6\] not assigned to an exact location on the device" {  } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_vsync_counter[6] } } } { "/opt/quartus/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/quartus/quartus/linux/Assignment Editor.qase" 1 { { 0 "d_vsync_counter\[6\]" } } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 3946 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_vsync_counter[6] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_vsync_counter\[5\] " "Info: Pin d_vsync_counter\[5\] not assigned to an exact location on the device" {  } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_vsync_counter[5] } } } { "/opt/quartus/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/quartus/quartus/linux/Assignment Editor.qase" 1 { { 0 "d_vsync_counter\[5\]" } } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 3959 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_vsync_counter[5] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_vsync_counter\[4\] " "Info: Pin d_vsync_counter\[4\] not assigned to an exact location on the device" {  } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_vsync_counter[4] } } } { "/opt/quartus/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/quartus/quartus/linux/Assignment Editor.qase" 1 { { 0 "d_vsync_counter\[4\]" } } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 3972 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_vsync_counter[4] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_vsync_counter\[3\] " "Info: Pin d_vsync_counter\[3\] not assigned to an exact location on the device" {  } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_vsync_counter[3] } } } { "/opt/quartus/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/quartus/quartus/linux/Assignment Editor.qase" 1 { { 0 "d_vsync_counter\[3\]" } } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 3985 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_vsync_counter[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_vsync_counter\[2\] " "Info: Pin d_vsync_counter\[2\] not assigned to an exact location on the device" {  } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_vsync_counter[2] } } } { "/opt/quartus/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/quartus/quartus/linux/Assignment Editor.qase" 1 { { 0 "d_vsync_counter\[2\]" } } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 3998 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_vsync_counter[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_vsync_counter\[1\] " "Info: Pin d_vsync_counter\[1\] not assigned to an exact location on the device" {  } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_vsync_counter[1] } } } { "/opt/quartus/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/quartus/quartus/linux/Assignment Editor.qase" 1 { { 0 "d_vsync_counter\[1\]" } } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 4011 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_vsync_counter[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1}  } {  } 0 0 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "" 0 -1}
+{ "Info" "ITDC_FITTER_TIMING_ENGINE" "Classic " "Info: Fitter is using the Classic Timing Analyzer" {  } {  } 0 0 "Fitter is using the %1!s! Timing Analyzer" 0 0 "" 0 -1}
+{ "Info" "ITAN_TDC_USER_OPTIMIZATION_GOALS" "" "Info: Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements" {  } {  } 0 0 "Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1}
+{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0 "" 0 -1}
+{ "Info" "ICUT_CUT_YGR_PLL_CAN_ACHIEVE_RATIO_AND_PHASE_SHIFT" "vpll:inst1\|altpll:altpll_component\|pll " "Info: Implementing parameter values for PLL \"vpll:inst1\|altpll:altpll_component\|pll\"" { { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "vpll:inst1\|altpll:altpll_component\|_clk0 31 38 0 -18 " "Info: Implementing clock multiplication of 31, clock division of 38, and phase shift of 0 degrees (-18 ps) for vpll:inst1\|altpll:altpll_component\|_clk0 port" {  } {  } 0 0 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "" 0 -1}  } { { "altpll.tdf" "" { Text "/opt/quartus/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } } { "../../src/vpll.vhd" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/src/vpll.vhd" 121 0 0 } } { "../../src/vga_pll.bdf" "" { Schematic "/homes/burban/didelu/dide_16/bsp3/Designflow/src/vga_pll.bdf" { { 56 408 504 152 "inst1" "" } } } }  } 0 0 "Implementing parameter values for PLL \"%1!s!\"" 0 0 "" 0 -1}
+{ "Info" "IFYGR_FYGR_PLL_CLK_PROMOTION" "" "Info: Promoted PLL clock signals" { { "Info" "IFYGR_FYGR_PLL_PROMOTE_GCLK" "vpll:inst1\|altpll:altpll_component\|_clk0 " "Info: Promoted signal \"vpll:inst1\|altpll:altpll_component\|_clk0\" to use global clock" {  } { { "/opt/quartus/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/quartus/quartus/linux/Assignment Editor.qase" 1 { { 0 "vpll:inst1\|altpll:altpll_component\|_clk0" } } } } { "../../src/vga_pll.bdf" "" { Schematic "/homes/burban/didelu/dide_16/bsp3/Designflow/src/vga_pll.bdf" { { 56 408 504 152 "inst1" "" } } } } { "altpll.tdf" "" { Text "/opt/quartus/quartus/libraries/megafunctions/altpll.tdf" 592 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { vpll:inst1|altpll:altpll_component|_clk0 } "NODE_NAME" } }  } 0 0 "Promoted signal \"%1!s!\" to use global clock" 0 0 "" 0 -1}  } {  } 0 0 "Promoted PLL clock signals" 0 0 "" 0 -1}
+{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "PLL Placement Operation " "Info: Completed PLL Placement Operation" {  } {  } 0 0 "Completed %1!s!" 0 0 "" 0 -1}
+{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "vga:inst\|vga_driver:vga_driver_unit\|un6_dly_counter_0_x Global clock " "Info: Automatically promoted some destinations of signal \"vga:inst\|vga_driver:vga_driver_unit\|un6_dly_counter_0_x\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "vga:inst\|vga_driver:vga_driver_unit\|hsync_state_6_ " "Info: Destination \"vga:inst\|vga_driver:vga_driver_unit\|hsync_state_6_\" may be non-global or may not use global clock" {  } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 118 23 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0 -1} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "vga:inst\|vga_driver:vga_driver_unit\|vsync_state_0_ " "Info: Destination \"vga:inst\|vga_driver:vga_driver_unit\|vsync_state_0_\" may be non-global or may not use global clock" {  } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 111 23 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0 -1} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "vga:inst\|vga_driver:vga_driver_unit\|vsync_state_1_ " "Info: Destination \"vga:inst\|vga_driver:vga_driver_unit\|vsync_state_1_\" may be non-global or may not use global clock" {  } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 110 23 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0 -1} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "vga:inst\|vga_driver:vga_driver_unit\|v_enable_sig_Z " "Info: Destination \"vga:inst\|vga_driver:vga_driver_unit\|v_enable_sig_Z\" may be non-global or may not use global clock" {  } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 155 22 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0 -1} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "vga:inst\|vga_driver:vga_driver_unit\|h_enable_sig_Z " "Info: Destination \"vga:inst\|vga_driver:vga_driver_unit\|h_enable_sig_Z\" may be non-global or may not use global clock" {  } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 154 22 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0 -1} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "vga:inst\|vga_driver:vga_driver_unit\|vsync_state_5_ " "Info: Destination \"vga:inst\|vga_driver:vga_driver_unit\|vsync_state_5_\" may be non-global or may not use global clock" {  } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 106 23 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0 -1} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "vga:inst\|vga_driver:vga_driver_unit\|vsync_state_4_ " "Info: Destination \"vga:inst\|vga_driver:vga_driver_unit\|vsync_state_4_\" may be non-global or may not use global clock" {  } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 109 23 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0 -1} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "vga:inst\|vga_driver:vga_driver_unit\|vsync_state_3_ " "Info: Destination \"vga:inst\|vga_driver:vga_driver_unit\|vsync_state_3_\" may be non-global or may not use global clock" {  } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 107 23 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0 -1} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "vga:inst\|vga_driver:vga_driver_unit\|vsync_state_2_ " "Info: Destination \"vga:inst\|vga_driver:vga_driver_unit\|vsync_state_2_\" may be non-global or may not use global clock" {  } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 105 23 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0 -1} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "vga:inst\|vga_driver:vga_driver_unit\|hsync_state_5_ " "Info: Destination \"vga:inst\|vga_driver:vga_driver_unit\|hsync_state_5_\" may be non-global or may not use global clock" {  } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 115 23 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0 -1} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_LIMITED_TO_SUB" "10 " "Info: Limited to 10 non-global destinations" {  } {  } 0 0 "Limited to %1!d! non-global destinations" 0 0 "" 0 -1}  } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 157 29 0 } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "" 0 -1}
+{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0 "" 0 -1}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0 0 "Starting register packing" 0 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" {  } {  } 1 0 "Started Fast Input/Output/OE register processing" 1 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" {  } {  } 1 0 "Finished Fast Input/Output/OE register processing" 1 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Extra Info: Start inferring scan chains for DSP blocks" {  } {  } 1 0 "Start inferring scan chains for DSP blocks" 1 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Extra Info: Inferring scan chains for DSP blocks is complete" {  } {  } 1 0 "Inferring scan chains for DSP blocks is complete" 1 0 "" 0 -1}
+{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0 0 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_START_LUT_IO_MAC_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, LUTs, RAM blocks, and DSP blocks to improve timing and density" {  } {  } 1 0 "Moving registers into I/O cells, LUTs, RAM blocks, and DSP blocks to improve timing and density" 1 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_IO_MAC_RAM_PACKING" "" "Extra Info: Finished moving registers into LUTs, I/O cells, DSP blocks, and RAM blocks" {  } {  } 1 0 "Finished moving registers into LUTs, I/O cells, DSP blocks, and RAM blocks" 1 0 "" 0 -1}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0 0 "Finished register packing" 0 0 "" 0 -1}
+{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "12 unused 3.3V 0 12 0 " "Info: Number of I/O pins in group: 12 (unused VREF, 3.3V VCCIO, 0 input, 12 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "3.3-V LVTTL. " "Info: I/O standards used: 3.3-V LVTTL." {  } {  } 0 0 "I/O standards used: %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "" 0 -1}  } {  } 0 0 "Statistics of %1!s!" 0 0 "" 0 -1}
+{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use 3.3V 11 50 " "Info: I/O bank number 1 does not use VREF pins and has 3.3V VCCIO pins. 11 total pin(s) used --  50 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use 3.3V 27 32 " "Info: I/O bank number 2 does not use VREF pins and has 3.3V VCCIO pins. 27 total pin(s) used --  32 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use 3.3V 6 48 " "Info: I/O bank number 3 does not use VREF pins and has 3.3V VCCIO pins. 6 total pin(s) used --  48 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use 3.3V 7 49 " "Info: I/O bank number 4 does not use VREF pins and has 3.3V VCCIO pins. 7 total pin(s) used --  49 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use 3.3V 20 39 " "Info: I/O bank number 5 does not use VREF pins and has 3.3V VCCIO pins. 20 total pin(s) used --  39 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use 3.3V 7 54 " "Info: I/O bank number 6 does not use VREF pins and has 3.3V VCCIO pins. 7 total pin(s) used --  54 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use undetermined 0 57 " "Info: I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  57 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use 3.3V 2 52 " "Info: I/O bank number 8 does not use VREF pins and has 3.3V VCCIO pins. 2 total pin(s) used --  52 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "9 does not use undetermined 0 6 " "Info: I/O bank number 9 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  6 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "11 does not use undetermined 0 6 " "Info: I/O bank number 11 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  6 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0 -1}  } {  } 0 0 "Statistics of %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "I/O bank details %1!s! I/O pin placement" 0 0 "" 0 -1}
+{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:03 " "Info: Fitter preparation operations ending: elapsed time is 00:00:03" {  } {  } 0 0 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:03 " "Info: Fitter placement operations ending: elapsed time is 00:00:03" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
+{ "Info" "ITDB_FULL_SLACK_TPD_RESULT" "register vga:inst\|vga_driver:vga_driver_unit\|column_counter_sig_9 register vga:inst\|vga_control:vga_control_unit\|b 29.931 ns " "Info: Slack time is 29.931 ns between source register \"vga:inst\|vga_driver:vga_driver_unit\|column_counter_sig_9\" and destination register \"vga:inst\|vga_control:vga_control_unit\|b\"" { { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "36.591 ns + Largest register register " "Info: + Largest register to register requirement is 36.591 ns" {  } {  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "vpll:inst1\|altpll:altpll_component\|_clk0 destination 2.138 ns   Shortest register " "Info:   Shortest clock path from clock \"vpll:inst1\|altpll:altpll_component\|_clk0\" to destination register is 2.138 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns vpll:inst1\|altpll:altpll_component\|_clk0 1 CLK PLL_1 63 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 63; CLK Node = 'vpll:inst1\|altpll:altpll_component\|_clk0'" {  } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { vpll:inst1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "/opt/quartus/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.578 ns) + CELL(0.560 ns) 2.138 ns vga:inst\|vga_control:vga_control_unit\|b 2 REG Unassigned 3 " "Info: 2: + IC(1.578 ns) + CELL(0.560 ns) = 2.138 ns; Loc. = Unassigned; Fanout = 3; REG Node = 'vga:inst\|vga_control:vga_control_unit\|b'" {  } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.138 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_control:vga_control_unit|b } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 3185 11 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.560 ns ( 26.19 % ) " "Info: Total cell delay = 0.560 ns ( 26.19 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.578 ns ( 73.81 % ) " "Info: Total interconnect delay = 1.578 ns ( 73.81 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "altpll.tdf" "" { Text "/opt/quartus/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "vpll:inst1\|altpll:altpll_component\|_clk0 destination 2.138 ns   Longest register " "Info:   Longest clock path from clock \"vpll:inst1\|altpll:altpll_component\|_clk0\" to destination register is 2.138 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns vpll:inst1\|altpll:altpll_component\|_clk0 1 CLK PLL_1 63 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 63; CLK Node = 'vpll:inst1\|altpll:altpll_component\|_clk0'" {  } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { vpll:inst1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "/opt/quartus/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.578 ns) + CELL(0.560 ns) 2.138 ns vga:inst\|vga_control:vga_control_unit\|b 2 REG Unassigned 3 " "Info: 2: + IC(1.578 ns) + CELL(0.560 ns) = 2.138 ns; Loc. = Unassigned; Fanout = 3; REG Node = 'vga:inst\|vga_control:vga_control_unit\|b'" {  } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.138 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_control:vga_control_unit|b } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 3185 11 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.560 ns ( 26.19 % ) " "Info: Total cell delay = 0.560 ns ( 26.19 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.578 ns ( 73.81 % ) " "Info: Total interconnect delay = 1.578 ns ( 73.81 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "altpll.tdf" "" { Text "/opt/quartus/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "vpll:inst1\|altpll:altpll_component\|_clk0 source 2.138 ns   Shortest register " "Info:   Shortest clock path from clock \"vpll:inst1\|altpll:altpll_component\|_clk0\" to source register is 2.138 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns vpll:inst1\|altpll:altpll_component\|_clk0 1 CLK PLL_1 63 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 63; CLK Node = 'vpll:inst1\|altpll:altpll_component\|_clk0'" {  } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { vpll:inst1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "/opt/quartus/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.578 ns) + CELL(0.560 ns) 2.138 ns vga:inst\|vga_driver:vga_driver_unit\|column_counter_sig_9 2 REG Unassigned 4 " "Info: 2: + IC(1.578 ns) + CELL(0.560 ns) = 2.138 ns; Loc. = Unassigned; Fanout = 4; REG Node = 'vga:inst\|vga_driver:vga_driver_unit\|column_counter_sig_9'" {  } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.138 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_driver:vga_driver_unit|column_counter_sig_9 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 128 30 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.560 ns ( 26.19 % ) " "Info: Total cell delay = 0.560 ns ( 26.19 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.578 ns ( 73.81 % ) " "Info: Total interconnect delay = 1.578 ns ( 73.81 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "altpll.tdf" "" { Text "/opt/quartus/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "vpll:inst1\|altpll:altpll_component\|_clk0 source 2.138 ns   Longest register " "Info:   Longest clock path from clock \"vpll:inst1\|altpll:altpll_component\|_clk0\" to source register is 2.138 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns vpll:inst1\|altpll:altpll_component\|_clk0 1 CLK PLL_1 63 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 63; CLK Node = 'vpll:inst1\|altpll:altpll_component\|_clk0'" {  } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { vpll:inst1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "/opt/quartus/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.578 ns) + CELL(0.560 ns) 2.138 ns vga:inst\|vga_driver:vga_driver_unit\|column_counter_sig_9 2 REG Unassigned 4 " "Info: 2: + IC(1.578 ns) + CELL(0.560 ns) = 2.138 ns; Loc. = Unassigned; Fanout = 4; REG Node = 'vga:inst\|vga_driver:vga_driver_unit\|column_counter_sig_9'" {  } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.138 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_driver:vga_driver_unit|column_counter_sig_9 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 128 30 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.560 ns ( 26.19 % ) " "Info: Total cell delay = 0.560 ns ( 26.19 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.578 ns ( 73.81 % ) " "Info: Total interconnect delay = 1.578 ns ( 73.81 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "altpll.tdf" "" { Text "/opt/quartus/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.176 ns   " "Info:   Micro clock to output delay of source is 0.176 ns" {  } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 128 30 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns   " "Info:   Micro setup delay of destination is 0.010 ns" {  } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 3185 11 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.660 ns - Longest register register " "Info: - Longest register to register delay is 6.660 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns vga:inst\|vga_driver:vga_driver_unit\|column_counter_sig_9 1 REG Unassigned 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = Unassigned; Fanout = 4; REG Node = 'vga:inst\|vga_driver:vga_driver_unit\|column_counter_sig_9'" {  } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { vga:inst|vga_driver:vga_driver_unit|column_counter_sig_9 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 128 30 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.108 ns) + CELL(0.459 ns) 2.567 ns vga:inst\|vga_control:vga_control_unit\|r_next_i_o7 2 COMB Unassigned 3 " "Info: 2: + IC(2.108 ns) + CELL(0.459 ns) = 2.567 ns; Loc. = Unassigned; Fanout = 3; COMB Node = 'vga:inst\|vga_control:vga_control_unit\|r_next_i_o7'" {  } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.567 ns" { vga:inst|vga_driver:vga_driver_unit|column_counter_sig_9 vga:inst|vga_control:vga_control_unit|r_next_i_o7 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 3207 19 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.405 ns) + CELL(0.087 ns) 5.059 ns vga:inst\|vga_control:vga_control_unit\|N_6_i_0_g0_0 3 COMB Unassigned 1 " "Info: 3: + IC(2.405 ns) + CELL(0.087 ns) = 5.059 ns; Loc. = Unassigned; Fanout = 1; COMB Node = 'vga:inst\|vga_control:vga_control_unit\|N_6_i_0_g0_0'" {  } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.492 ns" { vga:inst|vga_control:vga_control_unit|r_next_i_o7 vga:inst|vga_control:vga_control_unit|N_6_i_0_g0_0 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 3205 20 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.366 ns) + CELL(0.235 ns) 6.660 ns vga:inst\|vga_control:vga_control_unit\|b 4 REG Unassigned 3 " "Info: 4: + IC(1.366 ns) + CELL(0.235 ns) = 6.660 ns; Loc. = Unassigned; Fanout = 3; REG Node = 'vga:inst\|vga_control:vga_control_unit\|b'" {  } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "1.601 ns" { vga:inst|vga_control:vga_control_unit|N_6_i_0_g0_0 vga:inst|vga_control:vga_control_unit|b } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 3185 11 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.781 ns ( 11.73 % ) " "Info: Total cell delay = 0.781 ns ( 11.73 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "5.879 ns ( 88.27 % ) " "Info: Total interconnect delay = 5.879 ns ( 88.27 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "6.660 ns" { vga:inst|vga_driver:vga_driver_unit|column_counter_sig_9 vga:inst|vga_control:vga_control_unit|r_next_i_o7 vga:inst|vga_control:vga_control_unit|N_6_i_0_g0_0 vga:inst|vga_control:vga_control_unit|b } "NODE_NAME" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1}  } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "6.660 ns" { vga:inst|vga_driver:vga_driver_unit|column_counter_sig_9 vga:inst|vga_control:vga_control_unit|r_next_i_o7 vga:inst|vga_control:vga_control_unit|N_6_i_0_g0_0 vga:inst|vga_control:vga_control_unit|b } "NODE_NAME" } }  } 0 0 "Slack time is %5!s! between source %1!s! \"%2!s!\" and destination %3!s! \"%4!s!\"" 0 0 "" 0 -1}
+{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "6.660 ns register register " "Info: Estimated most critical path is register to register delay of 6.660 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns vga:inst\|vga_driver:vga_driver_unit\|column_counter_sig_9 1 REG LAB_X78_Y33 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X78_Y33; Fanout = 4; REG Node = 'vga:inst\|vga_driver:vga_driver_unit\|column_counter_sig_9'" {  } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { vga:inst|vga_driver:vga_driver_unit|column_counter_sig_9 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 128 30 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.108 ns) + CELL(0.459 ns) 2.567 ns vga:inst\|vga_control:vga_control_unit\|r_next_i_o7 2 COMB LAB_X56_Y45 3 " "Info: 2: + IC(2.108 ns) + CELL(0.459 ns) = 2.567 ns; Loc. = LAB_X56_Y45; Fanout = 3; COMB Node = 'vga:inst\|vga_control:vga_control_unit\|r_next_i_o7'" {  } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.567 ns" { vga:inst|vga_driver:vga_driver_unit|column_counter_sig_9 vga:inst|vga_control:vga_control_unit|r_next_i_o7 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 3207 19 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.405 ns) + CELL(0.087 ns) 5.059 ns vga:inst\|vga_control:vga_control_unit\|N_6_i_0_g0_0 3 COMB LAB_X76_Y33 1 " "Info: 3: + IC(2.405 ns) + CELL(0.087 ns) = 5.059 ns; Loc. = LAB_X76_Y33; Fanout = 1; COMB Node = 'vga:inst\|vga_control:vga_control_unit\|N_6_i_0_g0_0'" {  } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.492 ns" { vga:inst|vga_control:vga_control_unit|r_next_i_o7 vga:inst|vga_control:vga_control_unit|N_6_i_0_g0_0 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 3205 20 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.366 ns) + CELL(0.235 ns) 6.660 ns vga:inst\|vga_control:vga_control_unit\|b 4 REG LAB_X78_Y32 3 " "Info: 4: + IC(1.366 ns) + CELL(0.235 ns) = 6.660 ns; Loc. = LAB_X78_Y32; Fanout = 3; REG Node = 'vga:inst\|vga_control:vga_control_unit\|b'" {  } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "1.601 ns" { vga:inst|vga_control:vga_control_unit|N_6_i_0_g0_0 vga:inst|vga_control:vga_control_unit|b } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 3185 11 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.781 ns ( 11.73 % ) " "Info: Total cell delay = 0.781 ns ( 11.73 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "5.879 ns ( 88.27 % ) " "Info: Total interconnect delay = 5.879 ns ( 88.27 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "6.660 ns" { vga:inst|vga_driver:vga_driver_unit|column_counter_sig_9 vga:inst|vga_control:vga_control_unit|r_next_i_o7 vga:inst|vga_control:vga_control_unit|N_6_i_0_g0_0 vga:inst|vga_control:vga_control_unit|b } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Info: Average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "1 X34_Y24 X44_Y35 " "Info: Peak interconnect usage is 1% of the available device resources in the region that extends from location X34_Y24 to location X44_Y35" {  } {  } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0 -1}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Info: Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0 -1} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0 -1}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "" 0 -1}
+{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0 "" 0 -1}
+{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 -1}
+{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0 -1}
+{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0 "" 0 -1}
+{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "6 " "Warning: Following 6 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "seven_seg_pin\[13\] GND " "Info: Pin seven_seg_pin\[13\] has GND driving its datain port" {  } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { seven_seg_pin[13] } } } { "/opt/quartus/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/quartus/quartus/linux/Assignment Editor.qase" 1 { { 0 "seven_seg_pin\[13\]" } } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 4466 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { seven_seg_pin[13] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "seven_seg_pin\[6\] GND " "Info: Pin seven_seg_pin\[6\] has GND driving its datain port" {  } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { seven_seg_pin[6] } } } { "/opt/quartus/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/quartus/quartus/linux/Assignment Editor.qase" 1 { { 0 "seven_seg_pin\[6\]" } } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 4557 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { seven_seg_pin[6] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "seven_seg_pin\[5\] GND " "Info: Pin seven_seg_pin\[5\] has GND driving its datain port" {  } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { seven_seg_pin[5] } } } { "/opt/quartus/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/quartus/quartus/linux/Assignment Editor.qase" 1 { { 0 "seven_seg_pin\[5\]" } } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 4570 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { seven_seg_pin[5] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "seven_seg_pin\[4\] GND " "Info: Pin seven_seg_pin\[4\] has GND driving its datain port" {  } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { seven_seg_pin[4] } } } { "/opt/quartus/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/quartus/quartus/linux/Assignment Editor.qase" 1 { { 0 "seven_seg_pin\[4\]" } } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 4583 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { seven_seg_pin[4] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "seven_seg_pin\[3\] GND " "Info: Pin seven_seg_pin\[3\] has GND driving its datain port" {  } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { seven_seg_pin[3] } } } { "/opt/quartus/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/quartus/quartus/linux/Assignment Editor.qase" 1 { { 0 "seven_seg_pin\[3\]" } } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 4596 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { seven_seg_pin[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "seven_seg_pin\[0\] GND " "Info: Pin seven_seg_pin\[0\] has GND driving its datain port" {  } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { seven_seg_pin[0] } } } { "/opt/quartus/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/quartus/quartus/linux/Assignment Editor.qase" 1 { { 0 "seven_seg_pin\[0\]" } } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 4635 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { seven_seg_pin[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1}  } {  } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" 0 0 "" 0 -1}
+{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." {  } {  } 0 0 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "" 0 -1}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/homes/burban/didelu/dide_16/bsp3/Designflow/ppr/download/vga_pll.fit.smsg " "Info: Generated suppressed messages file /homes/burban/didelu/dide_16/bsp3/Designflow/ppr/download/vga_pll.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 4 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "320 " "Info: Peak virtual memory: 320 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Thu Oct 29 17:13:03 2009 " "Info: Processing ended: Thu Oct 29 17:13:03 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:28 " "Info: Elapsed time: 00:00:28" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:28 " "Info: Total CPU time (on all processors): 00:00:28" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
diff --git a/bsp3/Designflow/ppr/download/db/vga_pll.hier_info b/bsp3/Designflow/ppr/download/db/vga_pll.hier_info
new file mode 100644 (file)
index 0000000..71b8994
--- /dev/null
@@ -0,0 +1,432 @@
+|vga_pll
+d_hsync <= vga:inst.d_hsync
+board_clk => vpll:inst1.inclk0
+reset => vga:inst.reset_pin
+d_vsync <= vga:inst.d_vsync
+d_set_column_counter <= vga:inst.d_set_column_counter
+d_set_line_counter <= vga:inst.d_set_line_counter
+d_set_hsync_counter <= vga:inst.d_set_hsync_counter
+d_set_vsync_counter <= vga:inst.d_set_vsync_counter
+d_r <= vga:inst.d_r
+d_g <= vga:inst.d_g
+d_b <= vga:inst.d_b
+d_h_enable <= vga:inst.d_h_enable
+d_v_enable <= vga:inst.d_v_enable
+d_state_clk <= vga:inst.d_state_clk
+r0_pin <= vga:inst.r0_pin
+r1_pin <= vga:inst.r1_pin
+r2_pin <= vga:inst.r2_pin
+g0_pin <= vga:inst.g0_pin
+g1_pin <= vga:inst.g1_pin
+g2_pin <= vga:inst.g2_pin
+b0_pin <= vga:inst.b0_pin
+b1_pin <= vga:inst.b1_pin
+hsync_pin <= vga:inst.hsync_pin
+vsync_pin <= vga:inst.vsync_pin
+d_column_counter[0] <= vga:inst.d_column_counter[0]
+d_column_counter[1] <= vga:inst.d_column_counter[1]
+d_column_counter[2] <= vga:inst.d_column_counter[2]
+d_column_counter[3] <= vga:inst.d_column_counter[3]
+d_column_counter[4] <= vga:inst.d_column_counter[4]
+d_column_counter[5] <= vga:inst.d_column_counter[5]
+d_column_counter[6] <= vga:inst.d_column_counter[6]
+d_column_counter[7] <= vga:inst.d_column_counter[7]
+d_column_counter[8] <= vga:inst.d_column_counter[8]
+d_column_counter[9] <= vga:inst.d_column_counter[9]
+d_hsync_counter[0] <= vga:inst.d_hsync_counter[0]
+d_hsync_counter[1] <= vga:inst.d_hsync_counter[1]
+d_hsync_counter[2] <= vga:inst.d_hsync_counter[2]
+d_hsync_counter[3] <= vga:inst.d_hsync_counter[3]
+d_hsync_counter[4] <= vga:inst.d_hsync_counter[4]
+d_hsync_counter[5] <= vga:inst.d_hsync_counter[5]
+d_hsync_counter[6] <= vga:inst.d_hsync_counter[6]
+d_hsync_counter[7] <= vga:inst.d_hsync_counter[7]
+d_hsync_counter[8] <= vga:inst.d_hsync_counter[8]
+d_hsync_counter[9] <= vga:inst.d_hsync_counter[9]
+d_hsync_state[6] <= vga:inst.d_hsync_state[6]
+d_hsync_state[5] <= vga:inst.d_hsync_state[5]
+d_hsync_state[4] <= vga:inst.d_hsync_state[4]
+d_hsync_state[3] <= vga:inst.d_hsync_state[3]
+d_hsync_state[2] <= vga:inst.d_hsync_state[2]
+d_hsync_state[1] <= vga:inst.d_hsync_state[1]
+d_hsync_state[0] <= vga:inst.d_hsync_state[0]
+d_line_counter[0] <= vga:inst.d_line_counter[0]
+d_line_counter[1] <= vga:inst.d_line_counter[1]
+d_line_counter[2] <= vga:inst.d_line_counter[2]
+d_line_counter[3] <= vga:inst.d_line_counter[3]
+d_line_counter[4] <= vga:inst.d_line_counter[4]
+d_line_counter[5] <= vga:inst.d_line_counter[5]
+d_line_counter[6] <= vga:inst.d_line_counter[6]
+d_line_counter[7] <= vga:inst.d_line_counter[7]
+d_line_counter[8] <= vga:inst.d_line_counter[8]
+d_vsync_counter[0] <= vga:inst.d_vsync_counter[0]
+d_vsync_counter[1] <= vga:inst.d_vsync_counter[1]
+d_vsync_counter[2] <= vga:inst.d_vsync_counter[2]
+d_vsync_counter[3] <= vga:inst.d_vsync_counter[3]
+d_vsync_counter[4] <= vga:inst.d_vsync_counter[4]
+d_vsync_counter[5] <= vga:inst.d_vsync_counter[5]
+d_vsync_counter[6] <= vga:inst.d_vsync_counter[6]
+d_vsync_counter[7] <= vga:inst.d_vsync_counter[7]
+d_vsync_counter[8] <= vga:inst.d_vsync_counter[8]
+d_vsync_counter[9] <= vga:inst.d_vsync_counter[9]
+d_vsync_state[6] <= vga:inst.d_vsync_state[6]
+d_vsync_state[5] <= vga:inst.d_vsync_state[5]
+d_vsync_state[4] <= vga:inst.d_vsync_state[4]
+d_vsync_state[3] <= vga:inst.d_vsync_state[3]
+d_vsync_state[2] <= vga:inst.d_vsync_state[2]
+d_vsync_state[1] <= vga:inst.d_vsync_state[1]
+d_vsync_state[0] <= vga:inst.d_vsync_state[0]
+seven_seg_pin[0] <= vga:inst.seven_seg_pin[0]
+seven_seg_pin[1] <= vga:inst.seven_seg_pin[1]
+seven_seg_pin[2] <= vga:inst.seven_seg_pin[2]
+seven_seg_pin[3] <= vga:inst.seven_seg_pin[3]
+seven_seg_pin[4] <= vga:inst.seven_seg_pin[4]
+seven_seg_pin[5] <= vga:inst.seven_seg_pin[5]
+seven_seg_pin[6] <= vga:inst.seven_seg_pin[6]
+seven_seg_pin[7] <= vga:inst.seven_seg_pin[7]
+seven_seg_pin[8] <= vga:inst.seven_seg_pin[8]
+seven_seg_pin[9] <= vga:inst.seven_seg_pin[9]
+seven_seg_pin[10] <= vga:inst.seven_seg_pin[10]
+seven_seg_pin[11] <= vga:inst.seven_seg_pin[11]
+seven_seg_pin[12] <= vga:inst.seven_seg_pin[12]
+seven_seg_pin[13] <= vga:inst.seven_seg_pin[13]
+
+
+|vga_pll|vga:inst
+clk_pin => clk_pin_in.PADIO
+reset_pin => reset_pin_in.PADIO
+r0_pin <= r0_pin_out.PADIO
+r1_pin <= r1_pin_out.PADIO
+r2_pin <= r2_pin_out.PADIO
+g0_pin <= g0_pin_out.PADIO
+g1_pin <= g1_pin_out.PADIO
+g2_pin <= g2_pin_out.PADIO
+b0_pin <= b0_pin_out.PADIO
+b1_pin <= b1_pin_out.PADIO
+hsync_pin <= hsync_pin_out.PADIO
+vsync_pin <= vsync_pin_out.PADIO
+seven_seg_pin[0] <= seven_seg_pin_tri_0_.PADIO
+seven_seg_pin[1] <= seven_seg_pin_out_1_.PADIO
+seven_seg_pin[2] <= seven_seg_pin_out_2_.PADIO
+seven_seg_pin[3] <= seven_seg_pin_tri_3_.PADIO
+seven_seg_pin[4] <= seven_seg_pin_tri_4_.PADIO
+seven_seg_pin[5] <= seven_seg_pin_tri_5_.PADIO
+seven_seg_pin[6] <= seven_seg_pin_tri_6_.PADIO
+seven_seg_pin[7] <= seven_seg_pin_out_7_.PADIO
+seven_seg_pin[8] <= seven_seg_pin_out_8_.PADIO
+seven_seg_pin[9] <= seven_seg_pin_out_9_.PADIO
+seven_seg_pin[10] <= seven_seg_pin_out_10_.PADIO
+seven_seg_pin[11] <= seven_seg_pin_out_11_.PADIO
+seven_seg_pin[12] <= seven_seg_pin_out_12_.PADIO
+seven_seg_pin[13] <= seven_seg_pin_tri_13_.PADIO
+d_hsync <= d_hsync_out.PADIO
+d_vsync <= d_vsync_out.PADIO
+d_column_counter[0] <= d_column_counter_out_0_.PADIO
+d_column_counter[1] <= d_column_counter_out_1_.PADIO
+d_column_counter[2] <= d_column_counter_out_2_.PADIO
+d_column_counter[3] <= d_column_counter_out_3_.PADIO
+d_column_counter[4] <= d_column_counter_out_4_.PADIO
+d_column_counter[5] <= d_column_counter_out_5_.PADIO
+d_column_counter[6] <= d_column_counter_out_6_.PADIO
+d_column_counter[7] <= d_column_counter_out_7_.PADIO
+d_column_counter[8] <= d_column_counter_out_8_.PADIO
+d_column_counter[9] <= d_column_counter_out_9_.PADIO
+d_line_counter[0] <= d_line_counter_out_0_.PADIO
+d_line_counter[1] <= d_line_counter_out_1_.PADIO
+d_line_counter[2] <= d_line_counter_out_2_.PADIO
+d_line_counter[3] <= d_line_counter_out_3_.PADIO
+d_line_counter[4] <= d_line_counter_out_4_.PADIO
+d_line_counter[5] <= d_line_counter_out_5_.PADIO
+d_line_counter[6] <= d_line_counter_out_6_.PADIO
+d_line_counter[7] <= d_line_counter_out_7_.PADIO
+d_line_counter[8] <= d_line_counter_out_8_.PADIO
+d_set_column_counter <= d_set_column_counter_out.PADIO
+d_set_line_counter <= d_set_line_counter_out.PADIO
+d_hsync_counter[0] <= d_hsync_counter_out_0_.PADIO
+d_hsync_counter[1] <= d_hsync_counter_out_1_.PADIO
+d_hsync_counter[2] <= d_hsync_counter_out_2_.PADIO
+d_hsync_counter[3] <= d_hsync_counter_out_3_.PADIO
+d_hsync_counter[4] <= d_hsync_counter_out_4_.PADIO
+d_hsync_counter[5] <= d_hsync_counter_out_5_.PADIO
+d_hsync_counter[6] <= d_hsync_counter_out_6_.PADIO
+d_hsync_counter[7] <= d_hsync_counter_out_7_.PADIO
+d_hsync_counter[8] <= d_hsync_counter_out_8_.PADIO
+d_hsync_counter[9] <= d_hsync_counter_out_9_.PADIO
+d_vsync_counter[0] <= d_vsync_counter_out_0_.PADIO
+d_vsync_counter[1] <= d_vsync_counter_out_1_.PADIO
+d_vsync_counter[2] <= d_vsync_counter_out_2_.PADIO
+d_vsync_counter[3] <= d_vsync_counter_out_3_.PADIO
+d_vsync_counter[4] <= d_vsync_counter_out_4_.PADIO
+d_vsync_counter[5] <= d_vsync_counter_out_5_.PADIO
+d_vsync_counter[6] <= d_vsync_counter_out_6_.PADIO
+d_vsync_counter[7] <= d_vsync_counter_out_7_.PADIO
+d_vsync_counter[8] <= d_vsync_counter_out_8_.PADIO
+d_vsync_counter[9] <= d_vsync_counter_out_9_.PADIO
+d_set_hsync_counter <= d_set_hsync_counter_out.PADIO
+d_set_vsync_counter <= d_set_vsync_counter_out.PADIO
+d_h_enable <= d_h_enable_out.PADIO
+d_v_enable <= d_v_enable_out.PADIO
+d_r <= d_r_out.PADIO
+d_g <= d_g_out.PADIO
+d_b <= d_b_out.PADIO
+d_hsync_state[6] <= d_hsync_state_out_6_.PADIO
+d_hsync_state[5] <= d_hsync_state_out_5_.PADIO
+d_hsync_state[4] <= d_hsync_state_out_4_.PADIO
+d_hsync_state[3] <= d_hsync_state_out_3_.PADIO
+d_hsync_state[2] <= d_hsync_state_out_2_.PADIO
+d_hsync_state[1] <= d_hsync_state_out_1_.PADIO
+d_hsync_state[0] <= d_hsync_state_out_0_.PADIO
+d_vsync_state[6] <= d_vsync_state_out_6_.PADIO
+d_vsync_state[5] <= d_vsync_state_out_5_.PADIO
+d_vsync_state[4] <= d_vsync_state_out_4_.PADIO
+d_vsync_state[3] <= d_vsync_state_out_3_.PADIO
+d_vsync_state[2] <= d_vsync_state_out_2_.PADIO
+d_vsync_state[1] <= d_vsync_state_out_1_.PADIO
+d_vsync_state[0] <= d_vsync_state_out_0_.PADIO
+d_state_clk <= d_state_clk_out.PADIO
+
+
+|vga_pll|vga:inst|vga_driver:vga_driver_unit
+line_counter_sig_0 <= line_counter_sig_0_.REGOUT
+line_counter_sig_1 <= line_counter_sig_1_.REGOUT
+line_counter_sig_2 <= line_counter_sig_2_.REGOUT
+line_counter_sig_3 <= line_counter_sig_3_.REGOUT
+line_counter_sig_4 <= line_counter_sig_4_.REGOUT
+line_counter_sig_5 <= line_counter_sig_5_.REGOUT
+line_counter_sig_6 <= line_counter_sig_6_.REGOUT
+line_counter_sig_7 <= line_counter_sig_7_.REGOUT
+line_counter_sig_8 <= line_counter_sig_8_.REGOUT
+dly_counter_1 => vsync_state_6_.DATAC
+dly_counter_1 => h_sync_Z.DATAC
+dly_counter_1 => v_sync_Z.DATAC
+dly_counter_1 => line_counter_next_0_sqmuxa_1_1_cZ.DATAC
+dly_counter_1 => vsync_counter_next_1_sqmuxa_cZ.DATAC
+dly_counter_1 => hsync_counter_next_1_sqmuxa_cZ.DATAC
+dly_counter_1 => column_counter_next_0_sqmuxa_1_1_cZ.DATAC
+dly_counter_0 => vsync_state_6_.DATAB
+dly_counter_0 => h_sync_Z.DATAB
+dly_counter_0 => v_sync_Z.DATAB
+dly_counter_0 => line_counter_next_0_sqmuxa_1_1_cZ.DATAB
+dly_counter_0 => vsync_counter_next_1_sqmuxa_cZ.DATAB
+dly_counter_0 => hsync_counter_next_1_sqmuxa_cZ.DATAB
+dly_counter_0 => column_counter_next_0_sqmuxa_1_1_cZ.DATAB
+vsync_state_2 <= vsync_state_2_.REGOUT
+vsync_state_5 <= vsync_state_5_.REGOUT
+vsync_state_3 <= vsync_state_3_.REGOUT
+vsync_state_6 <= vsync_state_6_.REGOUT
+vsync_state_4 <= vsync_state_4_.REGOUT
+vsync_state_1 <= vsync_state_1_.REGOUT
+vsync_state_0 <= vsync_state_0_.REGOUT
+hsync_state_2 <= hsync_state_2_.REGOUT
+hsync_state_4 <= hsync_state_4_.REGOUT
+hsync_state_0 <= hsync_state_0_.REGOUT
+hsync_state_5 <= hsync_state_5_.REGOUT
+hsync_state_1 <= hsync_state_1_.REGOUT
+hsync_state_3 <= hsync_state_3_.REGOUT
+hsync_state_6 <= hsync_state_6_.REGOUT
+column_counter_sig_0 <= column_counter_sig_0_.REGOUT
+column_counter_sig_1 <= column_counter_sig_1_.REGOUT
+column_counter_sig_2 <= column_counter_sig_2_.REGOUT
+column_counter_sig_3 <= column_counter_sig_3_.REGOUT
+column_counter_sig_4 <= column_counter_sig_4_.REGOUT
+column_counter_sig_5 <= column_counter_sig_5_.REGOUT
+column_counter_sig_6 <= column_counter_sig_6_.REGOUT
+column_counter_sig_7 <= column_counter_sig_7_.REGOUT
+column_counter_sig_8 <= column_counter_sig_8_.REGOUT
+column_counter_sig_9 <= column_counter_sig_9_.REGOUT
+vsync_counter_9 <= vsync_counter_9_.REGOUT
+vsync_counter_8 <= vsync_counter_8_.REGOUT
+vsync_counter_7 <= vsync_counter_7_.REGOUT
+vsync_counter_6 <= vsync_counter_6_.REGOUT
+vsync_counter_5 <= vsync_counter_5_.REGOUT
+vsync_counter_4 <= vsync_counter_4_.REGOUT
+vsync_counter_3 <= vsync_counter_3_.REGOUT
+vsync_counter_2 <= vsync_counter_2_.REGOUT
+vsync_counter_1 <= vsync_counter_1_.REGOUT
+vsync_counter_0 <= vsync_counter_0_.REGOUT
+hsync_counter_9 <= hsync_counter_9_.REGOUT
+hsync_counter_8 <= hsync_counter_8_.REGOUT
+hsync_counter_7 <= hsync_counter_7_.REGOUT
+hsync_counter_6 <= hsync_counter_6_.REGOUT
+hsync_counter_5 <= hsync_counter_5_.REGOUT
+hsync_counter_4 <= hsync_counter_4_.REGOUT
+hsync_counter_3 <= hsync_counter_3_.REGOUT
+hsync_counter_2 <= hsync_counter_2_.REGOUT
+hsync_counter_1 <= hsync_counter_1_.REGOUT
+hsync_counter_0 <= hsync_counter_0_.REGOUT
+d_set_vsync_counter <= d_set_vsync_counter_cZ.COMBOUT
+un10_column_counter_siglt6_1 <= COLUMN_COUNT_next_un10_column_counter_siglt6_1.COMBOUT
+un10_column_counter_siglt6_3 <= COLUMN_COUNT_next_un10_column_counter_siglt6_3.COMBOUT
+v_sync <= v_sync_Z.REGOUT
+h_sync <= h_sync_Z.REGOUT
+h_enable_sig <= h_enable_sig_Z.REGOUT
+v_enable_sig <= v_enable_sig_Z.REGOUT
+reset_pin_c => vsync_state_6_.DATAA
+reset_pin_c => h_sync_Z.DATAA
+reset_pin_c => v_sync_Z.DATAA
+reset_pin_c => line_counter_next_0_sqmuxa_1_1_cZ.DATAA
+reset_pin_c => vsync_counter_next_1_sqmuxa_cZ.DATAA
+reset_pin_c => hsync_counter_next_1_sqmuxa_cZ.DATAA
+reset_pin_c => column_counter_next_0_sqmuxa_1_1_cZ.DATAA
+un6_dly_counter_0_x <= vsync_state_6_.COMBOUT
+d_set_hsync_counter <= d_set_hsync_counter_cZ.COMBOUT
+clk_pin_c => hsync_counter_0_.CLK
+clk_pin_c => hsync_counter_1_.CLK
+clk_pin_c => hsync_counter_2_.CLK
+clk_pin_c => hsync_counter_3_.CLK
+clk_pin_c => hsync_counter_4_.CLK
+clk_pin_c => hsync_counter_5_.CLK
+clk_pin_c => hsync_counter_6_.CLK
+clk_pin_c => hsync_counter_7_.CLK
+clk_pin_c => hsync_counter_8_.CLK
+clk_pin_c => hsync_counter_9_.CLK
+clk_pin_c => vsync_counter_0_.CLK
+clk_pin_c => vsync_counter_1_.CLK
+clk_pin_c => vsync_counter_2_.CLK
+clk_pin_c => vsync_counter_3_.CLK
+clk_pin_c => vsync_counter_4_.CLK
+clk_pin_c => vsync_counter_5_.CLK
+clk_pin_c => vsync_counter_6_.CLK
+clk_pin_c => vsync_counter_7_.CLK
+clk_pin_c => vsync_counter_8_.CLK
+clk_pin_c => vsync_counter_9_.CLK
+clk_pin_c => column_counter_sig_9_.CLK
+clk_pin_c => column_counter_sig_8_.CLK
+clk_pin_c => column_counter_sig_7_.CLK
+clk_pin_c => column_counter_sig_6_.CLK
+clk_pin_c => column_counter_sig_5_.CLK
+clk_pin_c => column_counter_sig_4_.CLK
+clk_pin_c => column_counter_sig_3_.CLK
+clk_pin_c => column_counter_sig_2_.CLK
+clk_pin_c => column_counter_sig_1_.CLK
+clk_pin_c => column_counter_sig_0_.CLK
+clk_pin_c => hsync_state_6_.CLK
+clk_pin_c => vsync_state_0_.CLK
+clk_pin_c => vsync_state_1_.CLK
+clk_pin_c => vsync_state_6_.CLK
+clk_pin_c => line_counter_sig_8_.CLK
+clk_pin_c => line_counter_sig_7_.CLK
+clk_pin_c => line_counter_sig_6_.CLK
+clk_pin_c => line_counter_sig_5_.CLK
+clk_pin_c => line_counter_sig_4_.CLK
+clk_pin_c => line_counter_sig_3_.CLK
+clk_pin_c => line_counter_sig_2_.CLK
+clk_pin_c => line_counter_sig_1_.CLK
+clk_pin_c => line_counter_sig_0_.CLK
+clk_pin_c => v_enable_sig_Z.CLK
+clk_pin_c => h_enable_sig_Z.CLK
+clk_pin_c => h_sync_Z.CLK
+clk_pin_c => v_sync_Z.CLK
+clk_pin_c => vsync_state_5_.CLK
+clk_pin_c => vsync_state_4_.CLK
+clk_pin_c => vsync_state_3_.CLK
+clk_pin_c => vsync_state_2_.CLK
+clk_pin_c => hsync_state_5_.CLK
+clk_pin_c => hsync_state_4_.CLK
+clk_pin_c => hsync_state_3_.CLK
+clk_pin_c => hsync_state_2_.CLK
+clk_pin_c => hsync_state_1_.CLK
+clk_pin_c => hsync_state_0_.CLK
+
+
+|vga_pll|vga:inst|vga_control:vga_control_unit
+column_counter_sig_1 => g_next_i_o3_cZ.DATAB
+column_counter_sig_7 => r_next_i_o7_cZ.DATAA
+column_counter_sig_2 => b_next_i_o3_0_cZ.DATAC
+column_counter_sig_2 => g_next_i_o3_cZ.DATAA
+column_counter_sig_0 => b_next_i_a7_1_cZ.DATAC
+column_counter_sig_4 => N_23_i_0_g0_a_cZ.DATAB
+column_counter_sig_4 => b_next_i_o3_0_cZ.DATAB
+column_counter_sig_3 => N_23_i_0_g0_a_cZ.DATAA
+column_counter_sig_3 => b_next_i_o3_0_cZ.DATAA
+column_counter_sig_5 => g_Z.DATAB
+column_counter_sig_5 => N_4_i_0_g0_1_cZ.DATAA
+column_counter_sig_5 => N_6_i_0_g0_0_cZ.DATAA
+column_counter_sig_5 => b_next_i_a7_1_cZ.DATAA
+column_counter_sig_5 => b_next_i_o3_0_cZ.DATAD
+column_counter_sig_6 => b_Z.DATAA
+column_counter_sig_6 => r_Z.DATAA
+column_counter_sig_6 => g_Z.DATAA
+column_counter_sig_6 => N_4_i_0_g0_1_cZ.DATAB
+column_counter_sig_6 => N_6_i_0_g0_0_cZ.DATAB
+column_counter_sig_6 => b_next_i_a7_1_cZ.DATAB
+h_enable_sig => r_next_i_o7_cZ.DATAC
+v_enable_sig => r_next_i_o7_cZ.DATAB
+un10_column_counter_siglt6_1 => N_23_i_0_g0_a_cZ.DATAD
+g <= g_Z.REGOUT
+un10_column_counter_siglt6_3 => r_Z.DATAB
+un10_column_counter_siglt6_3 => N_6_i_0_g0_0_cZ.DATAC
+r <= r_Z.REGOUT
+un6_dly_counter_0_x => b_Z.ACLR
+un6_dly_counter_0_x => r_Z.ACLR
+un6_dly_counter_0_x => g_Z.ACLR
+clk_pin_c => b_Z.CLK
+clk_pin_c => r_Z.CLK
+clk_pin_c => g_Z.CLK
+b <= b_Z.REGOUT
+
+
+|vga_pll|vpll:inst1
+inclk0 => altpll:altpll_component.inclk[0]
+c0 <= altpll:altpll_component.clk[0]
+
+
+|vga_pll|vpll:inst1|altpll:altpll_component
+inclk[0] => pll.CLK
+inclk[1] => ~NO_FANOUT~
+fbin => ~NO_FANOUT~
+pllena => ~NO_FANOUT~
+clkswitch => ~NO_FANOUT~
+areset => ~NO_FANOUT~
+pfdena => ~NO_FANOUT~
+clkena[0] => ~NO_FANOUT~
+clkena[1] => pll.ENA1
+clkena[2] => pll.ENA2
+clkena[3] => pll.ENA3
+clkena[4] => pll.ENA4
+clkena[5] => pll.ENA5
+extclkena[0] => pll.EXTCLKENA
+extclkena[1] => pll.EXTCLKENA1
+extclkena[2] => pll.EXTCLKENA2
+extclkena[3] => pll.EXTCLKENA3
+scanclk => ~NO_FANOUT~
+scanclkena => ~NO_FANOUT~
+scanaclr => ~NO_FANOUT~
+scanread => ~NO_FANOUT~
+scanwrite => ~NO_FANOUT~
+scandata => ~NO_FANOUT~
+phasecounterselect[0] => ~NO_FANOUT~
+phasecounterselect[1] => ~NO_FANOUT~
+phasecounterselect[2] => ~NO_FANOUT~
+phasecounterselect[3] => ~NO_FANOUT~
+phaseupdown => ~NO_FANOUT~
+phasestep => ~NO_FANOUT~
+configupdate => ~NO_FANOUT~
+fbmimicbidir <= <GND>
+clk[0] <= clk[0]~0.DB_MAX_OUTPUT_PORT_TYPE
+clk[1] <= <GND>
+clk[2] <= <GND>
+clk[3] <= <GND>
+clk[4] <= <GND>
+clk[5] <= <GND>
+extclk[0] <= <GND>
+extclk[1] <= <GND>
+extclk[2] <= <GND>
+extclk[3] <= <GND>
+clkbad[0] <= <GND>
+clkbad[1] <= <GND>
+enable1 <= <GND>
+enable0 <= <GND>
+activeclock <= <GND>
+clkloss <= <GND>
+locked <= <GND>
+scandataout <= <GND>
+scandone <= <GND>
+sclkout0 <= <GND>
+sclkout1 <= sclkout1~0.DB_MAX_OUTPUT_PORT_TYPE
+phasedone <= <GND>
+vcooverrange <= <GND>
+vcounderrange <= <GND>
+fbout <= <GND>
+
+
diff --git a/bsp3/Designflow/ppr/download/db/vga_pll.hif b/bsp3/Designflow/ppr/download/db/vga_pll.hif
new file mode 100644 (file)
index 0000000..5409a6a
--- /dev/null
@@ -0,0 +1,1669 @@
+Version 9.0 Build 132 02/25/2009 SJ Full Version
+45
+3235
+OFF
+OFF
+OFF
+ON
+ON
+OFF
+FV_OFF
+Level2
+0
+0
+VRSM_ON
+VHSM_ON
+synplcty.lmf
+-- Start Library Paths --
+-- End Library Paths --
+-- Start VHDL Libraries --
+-- End VHDL Libraries --
+# entity
+vga_pll
+# storage
+db|vga_pll.(0).cnf
+db|vga_pll.(0).cnf
+# case_insensitive
+# source_file
+..|..|src|vga_pll.bdf
+d3e7ceaac9b26558f3ae0434c87e1
+26
+# internal_option {
+BLOCK_DESIGN_NAMING
+AUTO
+}
+# hierarchies {
+|
+}
+# lmf
+|opt|quartus|quartus|lmf|synplcty.lmf
+3057712873b497a38b70a3917f30cc38
+# macro_sequence
+
+# end
+# entity
+vga
+# storage
+db|vga_pll.(1).cnf
+db|vga_pll.(1).cnf
+# case_sensitive
+# source_file
+..|..|syn|rev_1|vga.vqm
+75b23e99ee7fd7794044e77b9ba64bf9
+28
+# hierarchies {
+vga:inst
+}
+# lmf
+|opt|quartus|quartus|lmf|synplcty.lmf
+3057712873b497a38b70a3917f30cc38
+# macro_sequence
+
+# end
+# entity
+vga_driver
+# storage
+db|vga_pll.(2).cnf
+db|vga_pll.(2).cnf
+# case_sensitive
+# source_file
+..|..|syn|rev_1|vga.vqm
+75b23e99ee7fd7794044e77b9ba64bf9
+28
+# hierarchies {
+vga:inst|vga_driver:vga_driver_unit
+}
+# lmf
+|opt|quartus|quartus|lmf|synplcty.lmf
+3057712873b497a38b70a3917f30cc38
+# macro_sequence
+
+# end
+# entity
+vga_control
+# storage
+db|vga_pll.(3).cnf
+db|vga_pll.(3).cnf
+# case_sensitive
+# source_file
+..|..|syn|rev_1|vga.vqm
+75b23e99ee7fd7794044e77b9ba64bf9
+28
+# hierarchies {
+vga:inst|vga_control:vga_control_unit
+}
+# lmf
+|opt|quartus|quartus|lmf|synplcty.lmf
+3057712873b497a38b70a3917f30cc38
+# macro_sequence
+
+# end
+# entity
+vpll
+# storage
+db|vga_pll.(4).cnf
+db|vga_pll.(4).cnf
+# logic_option {
+AUTO_RAM_RECOGNITION
+ON
+}
+# case_insensitive
+# source_file
+..|..|src|vpll.vhd
+ccc2bcb05887d5721243fd22481948be
+5
+# internal_option {
+HDL_INITIAL_FANOUT_LIMIT
+OFF
+AUTO_RESOURCE_SHARING
+OFF
+AUTO_RAM_RECOGNITION
+ON
+AUTO_ROM_RECOGNITION
+ON
+}
+# hierarchies {
+vpll:inst1
+}
+# lmf
+|opt|quartus|quartus|lmf|maxplus2.lmf
+9a59d39b0706640b4b2718e8a1ff1f
+# macro_sequence
+
+# end
+# entity
+altpll
+# storage
+db|vga_pll.(5).cnf
+db|vga_pll.(5).cnf
+# case_insensitive
+# source_file
+|opt|quartus|quartus|libraries|megafunctions|altpll.tdf
+d980162588d7aa8b78874932c782e18
+7
+# user_parameter {
+OPERATION_MODE
+NORMAL
+PARAMETER_UNKNOWN
+USR
+PLL_TYPE
+AUTO
+PARAMETER_UNKNOWN
+USR
+QUALIFY_CONF_DONE
+OFF
+PARAMETER_UNKNOWN
+DEF
+COMPENSATE_CLOCK
+CLK0
+PARAMETER_UNKNOWN
+USR
+SCAN_CHAIN
+LONG
+PARAMETER_UNKNOWN
+DEF
+PRIMARY_CLOCK
+INCLK0
+PARAMETER_UNKNOWN
+DEF
+INCLK0_INPUT_FREQUENCY
+30003
+PARAMETER_SIGNED_DEC
+USR
+INCLK1_INPUT_FREQUENCY
+0
+PARAMETER_UNKNOWN
+DEF
+GATE_LOCK_SIGNAL
+NO
+PARAMETER_UNKNOWN
+USR
+GATE_LOCK_COUNTER
+0
+PARAMETER_UNKNOWN
+DEF
+LOCK_HIGH
+1
+PARAMETER_UNKNOWN
+DEF
+LOCK_LOW
+1
+PARAMETER_UNKNOWN
+DEF
+VALID_LOCK_MULTIPLIER
+1
+PARAMETER_SIGNED_DEC
+USR
+INVALID_LOCK_MULTIPLIER
+5
+PARAMETER_SIGNED_DEC
+USR
+SWITCH_OVER_ON_LOSSCLK
+OFF
+PARAMETER_UNKNOWN
+DEF
+SWITCH_OVER_ON_GATED_LOCK
+OFF
+PARAMETER_UNKNOWN
+DEF
+ENABLE_SWITCH_OVER_COUNTER
+OFF
+PARAMETER_UNKNOWN
+DEF
+SKIP_VCO
+OFF
+PARAMETER_UNKNOWN
+DEF
+SWITCH_OVER_COUNTER
+0
+PARAMETER_UNKNOWN
+DEF
+SWITCH_OVER_TYPE
+AUTO
+PARAMETER_UNKNOWN
+DEF
+FEEDBACK_SOURCE
+EXTCLK0
+PARAMETER_UNKNOWN
+DEF
+BANDWIDTH
+0
+PARAMETER_UNKNOWN
+DEF
+BANDWIDTH_TYPE
+AUTO
+PARAMETER_UNKNOWN
+USR
+SPREAD_FREQUENCY
+0
+PARAMETER_SIGNED_DEC
+USR
+DOWN_SPREAD
+0
+PARAMETER_UNKNOWN
+DEF
+SELF_RESET_ON_GATED_LOSS_LOCK
+OFF
+PARAMETER_UNKNOWN
+DEF
+SELF_RESET_ON_LOSS_LOCK
+OFF
+PARAMETER_UNKNOWN
+DEF
+CLK9_MULTIPLY_BY
+0
+PARAMETER_UNKNOWN
+DEF
+CLK8_MULTIPLY_BY
+0
+PARAMETER_UNKNOWN
+DEF
+CLK7_MULTIPLY_BY
+0
+PARAMETER_UNKNOWN
+DEF
+CLK6_MULTIPLY_BY
+0
+PARAMETER_UNKNOWN
+DEF
+CLK5_MULTIPLY_BY
+1
+PARAMETER_UNKNOWN
+DEF
+CLK4_MULTIPLY_BY
+1
+PARAMETER_UNKNOWN
+DEF
+CLK3_MULTIPLY_BY
+1
+PARAMETER_UNKNOWN
+DEF
+CLK2_MULTIPLY_BY
+1
+PARAMETER_UNKNOWN
+DEF
+CLK1_MULTIPLY_BY
+1
+PARAMETER_UNKNOWN
+DEF
+CLK0_MULTIPLY_BY
+5435
+PARAMETER_SIGNED_DEC
+USR
+CLK9_DIVIDE_BY
+0
+PARAMETER_UNKNOWN
+DEF
+CLK8_DIVIDE_BY
+0
+PARAMETER_UNKNOWN
+DEF
+CLK7_DIVIDE_BY
+0
+PARAMETER_UNKNOWN
+DEF
+CLK6_DIVIDE_BY
+0
+PARAMETER_UNKNOWN
+DEF
+CLK5_DIVIDE_BY
+1
+PARAMETER_UNKNOWN
+DEF
+CLK4_DIVIDE_BY
+1
+PARAMETER_UNKNOWN
+DEF
+CLK3_DIVIDE_BY
+1
+PARAMETER_UNKNOWN
+DEF
+CLK2_DIVIDE_BY
+1
+PARAMETER_UNKNOWN
+DEF
+CLK1_DIVIDE_BY
+1
+PARAMETER_UNKNOWN
+DEF
+CLK0_DIVIDE_BY
+6666
+PARAMETER_SIGNED_DEC
+USR
+CLK9_PHASE_SHIFT
+0
+PARAMETER_UNKNOWN
+DEF
+CLK8_PHASE_SHIFT
+0
+PARAMETER_UNKNOWN
+DEF
+CLK7_PHASE_SHIFT
+0
+PARAMETER_UNKNOWN
+DEF
+CLK6_PHASE_SHIFT
+0
+PARAMETER_UNKNOWN
+DEF
+CLK5_PHASE_SHIFT
+0
+PARAMETER_UNKNOWN
+DEF
+CLK4_PHASE_SHIFT
+0
+PARAMETER_UNKNOWN
+DEF
+CLK3_PHASE_SHIFT
+0
+PARAMETER_UNKNOWN
+DEF
+CLK2_PHASE_SHIFT
+0
+PARAMETER_UNKNOWN
+DEF
+CLK1_PHASE_SHIFT
+0
+PARAMETER_UNKNOWN
+DEF
+CLK0_PHASE_SHIFT
+0
+PARAMETER_UNKNOWN
+USR
+CLK5_TIME_DELAY
+0
+PARAMETER_UNKNOWN
+DEF
+CLK4_TIME_DELAY
+0
+PARAMETER_UNKNOWN
+DEF
+CLK3_TIME_DELAY
+0
+PARAMETER_UNKNOWN
+DEF
+CLK2_TIME_DELAY
+0
+PARAMETER_UNKNOWN
+DEF
+CLK1_TIME_DELAY
+0
+PARAMETER_UNKNOWN
+DEF
+CLK0_TIME_DELAY
+0
+PARAMETER_UNKNOWN
+USR
+CLK9_DUTY_CYCLE
+50
+PARAMETER_UNKNOWN
+DEF
+CLK8_DUTY_CYCLE
+50
+PARAMETER_UNKNOWN
+DEF
+CLK7_DUTY_CYCLE
+50
+PARAMETER_UNKNOWN
+DEF
+CLK6_DUTY_CYCLE
+50
+PARAMETER_UNKNOWN
+DEF
+CLK5_DUTY_CYCLE
+50
+PARAMETER_UNKNOWN
+DEF
+CLK4_DUTY_CYCLE
+50
+PARAMETER_UNKNOWN
+DEF
+CLK3_DUTY_CYCLE
+50
+PARAMETER_UNKNOWN
+DEF
+CLK2_DUTY_CYCLE
+50
+PARAMETER_UNKNOWN
+DEF
+CLK1_DUTY_CYCLE
+50
+PARAMETER_UNKNOWN
+DEF
+CLK0_DUTY_CYCLE
+50
+PARAMETER_SIGNED_DEC
+USR
+CLK9_USE_EVEN_COUNTER_MODE
+OFF
+PARAMETER_UNKNOWN
+DEF
+CLK8_USE_EVEN_COUNTER_MODE
+OFF
+PARAMETER_UNKNOWN
+DEF
+CLK7_USE_EVEN_COUNTER_MODE
+OFF
+PARAMETER_UNKNOWN
+DEF
+CLK6_USE_EVEN_COUNTER_MODE
+OFF
+PARAMETER_UNKNOWN
+DEF
+CLK5_USE_EVEN_COUNTER_MODE
+OFF
+PARAMETER_UNKNOWN
+DEF
+CLK4_USE_EVEN_COUNTER_MODE
+OFF
+PARAMETER_UNKNOWN
+DEF
+CLK3_USE_EVEN_COUNTER_MODE
+OFF
+PARAMETER_UNKNOWN
+DEF
+CLK2_USE_EVEN_COUNTER_MODE
+OFF
+PARAMETER_UNKNOWN
+DEF
+CLK1_USE_EVEN_COUNTER_MODE
+OFF
+PARAMETER_UNKNOWN
+DEF
+CLK0_USE_EVEN_COUNTER_MODE
+OFF
+PARAMETER_UNKNOWN
+DEF
+CLK9_USE_EVEN_COUNTER_VALUE
+OFF
+PARAMETER_UNKNOWN
+DEF
+CLK8_USE_EVEN_COUNTER_VALUE
+OFF
+PARAMETER_UNKNOWN
+DEF
+CLK7_USE_EVEN_COUNTER_VALUE
+OFF
+PARAMETER_UNKNOWN
+DEF
+CLK6_USE_EVEN_COUNTER_VALUE
+OFF
+PARAMETER_UNKNOWN
+DEF
+CLK5_USE_EVEN_COUNTER_VALUE
+OFF
+PARAMETER_UNKNOWN
+DEF
+CLK4_USE_EVEN_COUNTER_VALUE
+OFF
+PARAMETER_UNKNOWN
+DEF
+CLK3_USE_EVEN_COUNTER_VALUE
+OFF
+PARAMETER_UNKNOWN
+DEF
+CLK2_USE_EVEN_COUNTER_VALUE
+OFF
+PARAMETER_UNKNOWN
+DEF
+CLK1_USE_EVEN_COUNTER_VALUE
+OFF
+PARAMETER_UNKNOWN
+DEF
+CLK0_USE_EVEN_COUNTER_VALUE
+OFF
+PARAMETER_UNKNOWN
+DEF
+LOCK_WINDOW_UI
+ 0.05
+PARAMETER_UNKNOWN
+DEF
+LOCK_WINDOW_UI_BITS
+UNUSED
+PARAMETER_UNKNOWN
+DEF
+VCO_RANGE_DETECTOR_LOW_BITS
+UNUSED
+PARAMETER_UNKNOWN
+DEF
+VCO_RANGE_DETECTOR_HIGH_BITS
+UNUSED
+PARAMETER_UNKNOWN
+DEF
+DPA_MULTIPLY_BY
+0
+PARAMETER_UNKNOWN
+DEF
+DPA_DIVIDE_BY
+1
+PARAMETER_UNKNOWN
+DEF
+DPA_DIVIDER
+0
+PARAMETER_UNKNOWN
+DEF
+EXTCLK3_MULTIPLY_BY
+1
+PARAMETER_UNKNOWN
+DEF
+EXTCLK2_MULTIPLY_BY
+1
+PARAMETER_UNKNOWN
+DEF
+EXTCLK1_MULTIPLY_BY
+1
+PARAMETER_UNKNOWN
+DEF
+EXTCLK0_MULTIPLY_BY
+1
+PARAMETER_UNKNOWN
+DEF
+EXTCLK3_DIVIDE_BY
+1
+PARAMETER_UNKNOWN
+DEF
+EXTCLK2_DIVIDE_BY
+1
+PARAMETER_UNKNOWN
+DEF
+EXTCLK1_DIVIDE_BY
+1
+PARAMETER_UNKNOWN
+DEF
+EXTCLK0_DIVIDE_BY
+1
+PARAMETER_UNKNOWN
+DEF
+EXTCLK3_PHASE_SHIFT
+0
+PARAMETER_UNKNOWN
+DEF
+EXTCLK2_PHASE_SHIFT
+0
+PARAMETER_UNKNOWN
+DEF
+EXTCLK1_PHASE_SHIFT
+0
+PARAMETER_UNKNOWN
+DEF
+EXTCLK0_PHASE_SHIFT
+0
+PARAMETER_UNKNOWN
+DEF
+EXTCLK3_TIME_DELAY
+0
+PARAMETER_UNKNOWN
+DEF
+EXTCLK2_TIME_DELAY
+0
+PARAMETER_UNKNOWN
+DEF
+EXTCLK1_TIME_DELAY
+0
+PARAMETER_UNKNOWN
+DEF
+EXTCLK0_TIME_DELAY
+0
+PARAMETER_UNKNOWN
+DEF
+EXTCLK3_DUTY_CYCLE
+50
+PARAMETER_UNKNOWN
+DEF
+EXTCLK2_DUTY_CYCLE
+50
+PARAMETER_UNKNOWN
+DEF
+EXTCLK1_DUTY_CYCLE
+50
+PARAMETER_UNKNOWN
+DEF
+EXTCLK0_DUTY_CYCLE
+50
+PARAMETER_UNKNOWN
+DEF
+VCO_MULTIPLY_BY
+0
+PARAMETER_UNKNOWN
+DEF
+VCO_DIVIDE_BY
+0
+PARAMETER_UNKNOWN
+DEF
+SCLKOUT0_PHASE_SHIFT
+0
+PARAMETER_UNKNOWN
+DEF
+SCLKOUT1_PHASE_SHIFT
+0
+PARAMETER_UNKNOWN
+DEF
+VCO_MIN
+0
+PARAMETER_UNKNOWN
+DEF
+VCO_MAX
+0
+PARAMETER_UNKNOWN
+DEF
+VCO_CENTER
+0
+PARAMETER_UNKNOWN
+DEF
+PFD_MIN
+0
+PARAMETER_UNKNOWN
+DEF
+PFD_MAX
+0
+PARAMETER_UNKNOWN
+DEF
+M_INITIAL
+0
+PARAMETER_UNKNOWN
+DEF
+M
+0
+PARAMETER_UNKNOWN
+DEF
+N
+1
+PARAMETER_UNKNOWN
+DEF
+M2
+1
+PARAMETER_UNKNOWN
+DEF
+N2
+1
+PARAMETER_UNKNOWN
+DEF
+SS
+1
+PARAMETER_UNKNOWN
+DEF
+C0_HIGH
+0
+PARAMETER_UNKNOWN
+DEF
+C1_HIGH
+0
+PARAMETER_UNKNOWN
+DEF
+C2_HIGH
+0
+PARAMETER_UNKNOWN
+DEF
+C3_HIGH
+0
+PARAMETER_UNKNOWN
+DEF
+C4_HIGH
+0
+PARAMETER_UNKNOWN
+DEF
+C5_HIGH
+0
+PARAMETER_UNKNOWN
+DEF
+C6_HIGH
+0
+PARAMETER_UNKNOWN
+DEF
+C7_HIGH
+0
+PARAMETER_UNKNOWN
+DEF
+C8_HIGH
+0
+PARAMETER_UNKNOWN
+DEF
+C9_HIGH
+0
+PARAMETER_UNKNOWN
+DEF
+C0_LOW
+0
+PARAMETER_UNKNOWN
+DEF
+C1_LOW
+0
+PARAMETER_UNKNOWN
+DEF
+C2_LOW
+0
+PARAMETER_UNKNOWN
+DEF
+C3_LOW
+0
+PARAMETER_UNKNOWN
+DEF
+C4_LOW
+0
+PARAMETER_UNKNOWN
+DEF
+C5_LOW
+0
+PARAMETER_UNKNOWN
+DEF
+C6_LOW
+0
+PARAMETER_UNKNOWN
+DEF
+C7_LOW
+0
+PARAMETER_UNKNOWN
+DEF
+C8_LOW
+0
+PARAMETER_UNKNOWN
+DEF
+C9_LOW
+0
+PARAMETER_UNKNOWN
+DEF
+C0_INITIAL
+0
+PARAMETER_UNKNOWN
+DEF
+C1_INITIAL
+0
+PARAMETER_UNKNOWN
+DEF
+C2_INITIAL
+0
+PARAMETER_UNKNOWN
+DEF
+C3_INITIAL
+0
+PARAMETER_UNKNOWN
+DEF
+C4_INITIAL
+0
+PARAMETER_UNKNOWN
+DEF
+C5_INITIAL
+0
+PARAMETER_UNKNOWN
+DEF
+C6_INITIAL
+0
+PARAMETER_UNKNOWN
+DEF
+C7_INITIAL
+0
+PARAMETER_UNKNOWN
+DEF
+C8_INITIAL
+0
+PARAMETER_UNKNOWN
+DEF
+C9_INITIAL
+0
+PARAMETER_UNKNOWN
+DEF
+C0_MODE
+BYPASS
+PARAMETER_UNKNOWN
+DEF
+C1_MODE
+BYPASS
+PARAMETER_UNKNOWN
+DEF
+C2_MODE
+BYPASS
+PARAMETER_UNKNOWN
+DEF
+C3_MODE
+BYPASS
+PARAMETER_UNKNOWN
+DEF
+C4_MODE
+BYPASS
+PARAMETER_UNKNOWN
+DEF
+C5_MODE
+BYPASS
+PARAMETER_UNKNOWN
+DEF
+C6_MODE
+BYPASS
+PARAMETER_UNKNOWN
+DEF
+C7_MODE
+BYPASS
+PARAMETER_UNKNOWN
+DEF
+C8_MODE
+BYPASS
+PARAMETER_UNKNOWN
+DEF
+C9_MODE
+BYPASS
+PARAMETER_UNKNOWN
+DEF
+C0_PH
+0
+PARAMETER_UNKNOWN
+DEF
+C1_PH
+0
+PARAMETER_UNKNOWN
+DEF
+C2_PH
+0
+PARAMETER_UNKNOWN
+DEF
+C3_PH
+0
+PARAMETER_UNKNOWN
+DEF
+C4_PH
+0
+PARAMETER_UNKNOWN
+DEF
+C5_PH
+0
+PARAMETER_UNKNOWN
+DEF
+C6_PH
+0
+PARAMETER_UNKNOWN
+DEF
+C7_PH
+0
+PARAMETER_UNKNOWN
+DEF
+C8_PH
+0
+PARAMETER_UNKNOWN
+DEF
+C9_PH
+0
+PARAMETER_UNKNOWN
+DEF
+L0_HIGH
+1
+PARAMETER_UNKNOWN
+DEF
+L1_HIGH
+1
+PARAMETER_UNKNOWN
+DEF
+G0_HIGH
+1
+PARAMETER_UNKNOWN
+DEF
+G1_HIGH
+1
+PARAMETER_UNKNOWN
+DEF
+G2_HIGH
+1
+PARAMETER_UNKNOWN
+DEF
+G3_HIGH
+1
+PARAMETER_UNKNOWN
+DEF
+E0_HIGH
+1
+PARAMETER_UNKNOWN
+DEF
+E1_HIGH
+1
+PARAMETER_UNKNOWN
+DEF
+E2_HIGH
+1
+PARAMETER_UNKNOWN
+DEF
+E3_HIGH
+1
+PARAMETER_UNKNOWN
+DEF
+L0_LOW
+1
+PARAMETER_UNKNOWN
+DEF
+L1_LOW
+1
+PARAMETER_UNKNOWN
+DEF
+G0_LOW
+1
+PARAMETER_UNKNOWN
+DEF
+G1_LOW
+1
+PARAMETER_UNKNOWN
+DEF
+G2_LOW
+1
+PARAMETER_UNKNOWN
+DEF
+G3_LOW
+1
+PARAMETER_UNKNOWN
+DEF
+E0_LOW
+1
+PARAMETER_UNKNOWN
+DEF
+E1_LOW
+1
+PARAMETER_UNKNOWN
+DEF
+E2_LOW
+1
+PARAMETER_UNKNOWN
+DEF
+E3_LOW
+1
+PARAMETER_UNKNOWN
+DEF
+L0_INITIAL
+1
+PARAMETER_UNKNOWN
+DEF
+L1_INITIAL
+1
+PARAMETER_UNKNOWN
+DEF
+G0_INITIAL
+1
+PARAMETER_UNKNOWN
+DEF
+G1_INITIAL
+1
+PARAMETER_UNKNOWN
+DEF
+G2_INITIAL
+1
+PARAMETER_UNKNOWN
+DEF
+G3_INITIAL
+1
+PARAMETER_UNKNOWN
+DEF
+E0_INITIAL
+1
+PARAMETER_UNKNOWN
+DEF
+E1_INITIAL
+1
+PARAMETER_UNKNOWN
+DEF
+E2_INITIAL
+1
+PARAMETER_UNKNOWN
+DEF
+E3_INITIAL
+1
+PARAMETER_UNKNOWN
+DEF
+L0_MODE
+BYPASS
+PARAMETER_UNKNOWN
+DEF
+L1_MODE
+BYPASS
+PARAMETER_UNKNOWN
+DEF
+G0_MODE
+BYPASS
+PARAMETER_UNKNOWN
+DEF
+G1_MODE
+BYPASS
+PARAMETER_UNKNOWN
+DEF
+G2_MODE
+BYPASS
+PARAMETER_UNKNOWN
+DEF
+G3_MODE
+BYPASS
+PARAMETER_UNKNOWN
+DEF
+E0_MODE
+BYPASS
+PARAMETER_UNKNOWN
+DEF
+E1_MODE
+BYPASS
+PARAMETER_UNKNOWN
+DEF
+E2_MODE
+BYPASS
+PARAMETER_UNKNOWN
+DEF
+E3_MODE
+BYPASS
+PARAMETER_UNKNOWN
+DEF
+L0_PH
+0
+PARAMETER_UNKNOWN
+DEF
+L1_PH
+0
+PARAMETER_UNKNOWN
+DEF
+G0_PH
+0
+PARAMETER_UNKNOWN
+DEF
+G1_PH
+0
+PARAMETER_UNKNOWN
+DEF
+G2_PH
+0
+PARAMETER_UNKNOWN
+DEF
+G3_PH
+0
+PARAMETER_UNKNOWN
+DEF
+E0_PH
+0
+PARAMETER_UNKNOWN
+DEF
+E1_PH
+0
+PARAMETER_UNKNOWN
+DEF
+E2_PH
+0
+PARAMETER_UNKNOWN
+DEF
+E3_PH
+0
+PARAMETER_UNKNOWN
+DEF
+M_PH
+0
+PARAMETER_UNKNOWN
+DEF
+C1_USE_CASC_IN
+OFF
+PARAMETER_UNKNOWN
+DEF
+C2_USE_CASC_IN
+OFF
+PARAMETER_UNKNOWN
+DEF
+C3_USE_CASC_IN
+OFF
+PARAMETER_UNKNOWN
+DEF
+C4_USE_CASC_IN
+OFF
+PARAMETER_UNKNOWN
+DEF
+C5_USE_CASC_IN
+OFF
+PARAMETER_UNKNOWN
+DEF
+C6_USE_CASC_IN
+OFF
+PARAMETER_UNKNOWN
+DEF
+C7_USE_CASC_IN
+OFF
+PARAMETER_UNKNOWN
+DEF
+C8_USE_CASC_IN
+OFF
+PARAMETER_UNKNOWN
+DEF
+C9_USE_CASC_IN
+OFF
+PARAMETER_UNKNOWN
+DEF
+CLK0_COUNTER
+G0
+PARAMETER_UNKNOWN
+DEF
+CLK1_COUNTER
+G0
+PARAMETER_UNKNOWN
+DEF
+CLK2_COUNTER
+G0
+PARAMETER_UNKNOWN
+DEF
+CLK3_COUNTER
+G0
+PARAMETER_UNKNOWN
+DEF
+CLK4_COUNTER
+G0
+PARAMETER_UNKNOWN
+DEF
+CLK5_COUNTER
+G0
+PARAMETER_UNKNOWN
+DEF
+CLK6_COUNTER
+E0
+PARAMETER_UNKNOWN
+DEF
+CLK7_COUNTER
+E1
+PARAMETER_UNKNOWN
+DEF
+CLK8_COUNTER
+E2
+PARAMETER_UNKNOWN
+DEF
+CLK9_COUNTER
+E3
+PARAMETER_UNKNOWN
+DEF
+L0_TIME_DELAY
+0
+PARAMETER_UNKNOWN
+DEF
+L1_TIME_DELAY
+0
+PARAMETER_UNKNOWN
+DEF
+G0_TIME_DELAY
+0
+PARAMETER_UNKNOWN
+DEF
+G1_TIME_DELAY
+0
+PARAMETER_UNKNOWN
+DEF
+G2_TIME_DELAY
+0
+PARAMETER_UNKNOWN
+DEF
+G3_TIME_DELAY
+0
+PARAMETER_UNKNOWN
+DEF
+E0_TIME_DELAY
+0
+PARAMETER_UNKNOWN
+DEF
+E1_TIME_DELAY
+0
+PARAMETER_UNKNOWN
+DEF
+E2_TIME_DELAY
+0
+PARAMETER_UNKNOWN
+DEF
+E3_TIME_DELAY
+0
+PARAMETER_UNKNOWN
+DEF
+M_TIME_DELAY
+0
+PARAMETER_UNKNOWN
+DEF
+N_TIME_DELAY
+0
+PARAMETER_UNKNOWN
+DEF
+EXTCLK3_COUNTER
+E3
+PARAMETER_UNKNOWN
+DEF
+EXTCLK2_COUNTER
+E2
+PARAMETER_UNKNOWN
+DEF
+EXTCLK1_COUNTER
+E1
+PARAMETER_UNKNOWN
+DEF
+EXTCLK0_COUNTER
+E0
+PARAMETER_UNKNOWN
+DEF
+ENABLE0_COUNTER
+L0
+PARAMETER_UNKNOWN
+DEF
+ENABLE1_COUNTER
+L0
+PARAMETER_UNKNOWN
+DEF
+CHARGE_PUMP_CURRENT
+2
+PARAMETER_UNKNOWN
+DEF
+LOOP_FILTER_R
+ 1.000000
+PARAMETER_UNKNOWN
+DEF
+LOOP_FILTER_C
+5
+PARAMETER_UNKNOWN
+DEF
+CHARGE_PUMP_CURRENT_BITS
+9999
+PARAMETER_UNKNOWN
+DEF
+LOOP_FILTER_R_BITS
+9999
+PARAMETER_UNKNOWN
+DEF
+LOOP_FILTER_C_BITS
+9999
+PARAMETER_UNKNOWN
+DEF
+VCO_POST_SCALE
+0
+PARAMETER_UNKNOWN
+DEF
+CLK2_OUTPUT_FREQUENCY
+0
+PARAMETER_UNKNOWN
+DEF
+CLK1_OUTPUT_FREQUENCY
+0
+PARAMETER_UNKNOWN
+DEF
+CLK0_OUTPUT_FREQUENCY
+0
+PARAMETER_UNKNOWN
+DEF
+INTENDED_DEVICE_FAMILY
+Stratix
+PARAMETER_UNKNOWN
+USR
+PORT_CLKENA0
+PORT_CONNECTIVITY
+PARAMETER_UNKNOWN
+DEF
+PORT_CLKENA1
+PORT_CONNECTIVITY
+PARAMETER_UNKNOWN
+DEF
+PORT_CLKENA2
+PORT_CONNECTIVITY
+PARAMETER_UNKNOWN
+DEF
+PORT_CLKENA3
+PORT_CONNECTIVITY
+PARAMETER_UNKNOWN
+DEF
+PORT_CLKENA4
+PORT_CONNECTIVITY
+PARAMETER_UNKNOWN
+DEF
+PORT_CLKENA5
+PORT_CONNECTIVITY
+PARAMETER_UNKNOWN
+DEF
+PORT_EXTCLKENA0
+PORT_CONNECTIVITY
+PARAMETER_UNKNOWN
+DEF
+PORT_EXTCLKENA1
+PORT_CONNECTIVITY
+PARAMETER_UNKNOWN
+DEF
+PORT_EXTCLKENA2
+PORT_CONNECTIVITY
+PARAMETER_UNKNOWN
+DEF
+PORT_EXTCLKENA3
+PORT_CONNECTIVITY
+PARAMETER_UNKNOWN
+DEF
+PORT_EXTCLK0
+PORT_CONNECTIVITY
+PARAMETER_UNKNOWN
+DEF
+PORT_EXTCLK1
+PORT_CONNECTIVITY
+PARAMETER_UNKNOWN
+DEF
+PORT_EXTCLK2
+PORT_CONNECTIVITY
+PARAMETER_UNKNOWN
+DEF
+PORT_EXTCLK3
+PORT_CONNECTIVITY
+PARAMETER_UNKNOWN
+DEF
+PORT_CLKBAD0
+PORT_CONNECTIVITY
+PARAMETER_UNKNOWN
+DEF
+PORT_CLKBAD1
+PORT_CONNECTIVITY
+PARAMETER_UNKNOWN
+DEF
+PORT_CLK0
+PORT_CONNECTIVITY
+PARAMETER_UNKNOWN
+DEF
+PORT_CLK1
+PORT_CONNECTIVITY
+PARAMETER_UNKNOWN
+DEF
+PORT_CLK2
+PORT_CONNECTIVITY
+PARAMETER_UNKNOWN
+DEF
+PORT_CLK3
+PORT_CONNECTIVITY
+PARAMETER_UNKNOWN
+DEF
+PORT_CLK4
+PORT_CONNECTIVITY
+PARAMETER_UNKNOWN
+DEF
+PORT_CLK5
+PORT_CONNECTIVITY
+PARAMETER_UNKNOWN
+DEF
+PORT_CLK6
+PORT_UNUSED
+PARAMETER_UNKNOWN
+DEF
+PORT_CLK7
+PORT_UNUSED
+PARAMETER_UNKNOWN
+DEF
+PORT_CLK8
+PORT_UNUSED
+PARAMETER_UNKNOWN
+DEF
+PORT_CLK9
+PORT_UNUSED
+PARAMETER_UNKNOWN
+DEF
+PORT_SCANDATA
+PORT_CONNECTIVITY
+PARAMETER_UNKNOWN
+DEF
+PORT_SCANDATAOUT
+PORT_CONNECTIVITY
+PARAMETER_UNKNOWN
+DEF
+PORT_SCANDONE
+PORT_CONNECTIVITY
+PARAMETER_UNKNOWN
+DEF
+PORT_SCLKOUT1
+PORT_CONNECTIVITY
+PARAMETER_UNKNOWN
+DEF
+PORT_SCLKOUT0
+PORT_CONNECTIVITY
+PARAMETER_UNKNOWN
+DEF
+PORT_ACTIVECLOCK
+PORT_CONNECTIVITY
+PARAMETER_UNKNOWN
+DEF
+PORT_CLKLOSS
+PORT_CONNECTIVITY
+PARAMETER_UNKNOWN
+DEF
+PORT_INCLK1
+PORT_CONNECTIVITY
+PARAMETER_UNKNOWN
+DEF
+PORT_INCLK0
+PORT_CONNECTIVITY
+PARAMETER_UNKNOWN
+DEF
+PORT_FBIN
+PORT_CONNECTIVITY
+PARAMETER_UNKNOWN
+DEF
+PORT_PLLENA
+PORT_CONNECTIVITY
+PARAMETER_UNKNOWN
+DEF
+PORT_CLKSWITCH
+PORT_CONNECTIVITY
+PARAMETER_UNKNOWN
+DEF
+PORT_ARESET
+PORT_CONNECTIVITY
+PARAMETER_UNKNOWN
+DEF
+PORT_PFDENA
+PORT_CONNECTIVITY
+PARAMETER_UNKNOWN
+DEF
+PORT_SCANCLK
+PORT_CONNECTIVITY
+PARAMETER_UNKNOWN
+DEF
+PORT_SCANACLR
+PORT_CONNECTIVITY
+PARAMETER_UNKNOWN
+DEF
+PORT_SCANREAD
+PORT_CONNECTIVITY
+PARAMETER_UNKNOWN
+DEF
+PORT_SCANWRITE
+PORT_CONNECTIVITY
+PARAMETER_UNKNOWN
+DEF
+PORT_ENABLE0
+PORT_CONNECTIVITY
+PARAMETER_UNKNOWN
+DEF
+PORT_ENABLE1
+PORT_CONNECTIVITY
+PARAMETER_UNKNOWN
+DEF
+PORT_LOCKED
+PORT_CONNECTIVITY
+PARAMETER_UNKNOWN
+DEF
+PORT_CONFIGUPDATE
+PORT_CONNECTIVITY
+PARAMETER_UNKNOWN
+DEF
+PORT_FBOUT
+PORT_CONNECTIVITY
+PARAMETER_UNKNOWN
+DEF
+PORT_PHASEDONE
+PORT_CONNECTIVITY
+PARAMETER_UNKNOWN
+DEF
+PORT_PHASESTEP
+PORT_CONNECTIVITY
+PARAMETER_UNKNOWN
+DEF
+PORT_PHASEUPDOWN
+PORT_CONNECTIVITY
+PARAMETER_UNKNOWN
+DEF
+PORT_SCANCLKENA
+PORT_CONNECTIVITY
+PARAMETER_UNKNOWN
+DEF
+PORT_PHASECOUNTERSELECT
+PORT_CONNECTIVITY
+PARAMETER_UNKNOWN
+DEF
+PORT_VCOOVERRANGE
+PORT_CONNECTIVITY
+PARAMETER_UNKNOWN
+DEF
+PORT_VCOUNDERRANGE
+PORT_CONNECTIVITY
+PARAMETER_UNKNOWN
+DEF
+M_TEST_SOURCE
+5
+PARAMETER_UNKNOWN
+DEF
+C0_TEST_SOURCE
+5
+PARAMETER_UNKNOWN
+DEF
+C1_TEST_SOURCE
+5
+PARAMETER_UNKNOWN
+DEF
+C2_TEST_SOURCE
+5
+PARAMETER_UNKNOWN
+DEF
+C3_TEST_SOURCE
+5
+PARAMETER_UNKNOWN
+DEF
+C4_TEST_SOURCE
+5
+PARAMETER_UNKNOWN
+DEF
+C5_TEST_SOURCE
+5
+PARAMETER_UNKNOWN
+DEF
+C6_TEST_SOURCE
+5
+PARAMETER_UNKNOWN
+DEF
+C7_TEST_SOURCE
+5
+PARAMETER_UNKNOWN
+DEF
+C8_TEST_SOURCE
+5
+PARAMETER_UNKNOWN
+DEF
+C9_TEST_SOURCE
+5
+PARAMETER_UNKNOWN
+DEF
+CBXI_PARAMETER
+NOTHING
+PARAMETER_UNKNOWN
+DEF
+VCO_FREQUENCY_CONTROL
+AUTO
+PARAMETER_UNKNOWN
+DEF
+VCO_PHASE_SHIFT_STEP
+0
+PARAMETER_UNKNOWN
+DEF
+WIDTH_CLOCK
+6
+PARAMETER_UNKNOWN
+DEF
+WIDTH_PHASECOUNTERSELECT
+4
+PARAMETER_UNKNOWN
+DEF
+USING_FBMIMICBIDIR_PORT
+OFF
+PARAMETER_UNKNOWN
+DEF
+DEVICE_FAMILY
+Stratix
+PARAMETER_UNKNOWN
+USR
+SCAN_CHAIN_MIF_FILE
+UNUSED
+PARAMETER_UNKNOWN
+DEF
+SIM_GATE_LOCK_DEVICE_BEHAVIOR
+OFF
+PARAMETER_UNKNOWN
+DEF
+AUTO_CARRY_CHAINS
+ON
+AUTO_CARRY
+USR
+IGNORE_CARRY_BUFFERS
+OFF
+IGNORE_CARRY
+USR
+AUTO_CASCADE_CHAINS
+ON
+AUTO_CASCADE
+USR
+IGNORE_CASCADE_BUFFERS
+OFF
+IGNORE_CASCADE
+USR
+}
+# used_port {
+inclk0
+-1
+3
+clk0
+-1
+3
+inclk1
+-1
+1
+extclkena3
+-1
+1
+extclkena2
+-1
+1
+extclkena1
+-1
+1
+extclkena0
+-1
+1
+clkena5
+-1
+1
+clkena4
+-1
+1
+clkena3
+-1
+1
+clkena2
+-1
+1
+clkena1
+-1
+1
+areset
+-1
+1
+pllena
+-1
+2
+clkena0
+-1
+2
+}
+# include_file {
+|opt|quartus|quartus|libraries|megafunctions|aglobal90.inc
+99832fdf63412df51d7531202d74e75
+|opt|quartus|quartus|libraries|megafunctions|stratixii_pll.inc
+6d1985e16ab5f59a1fd6b0ae20978a4e
+|opt|quartus|quartus|libraries|megafunctions|cycloneii_pll.inc
+39a0d9d1237d1db39c848c3f9faffc
+|opt|quartus|quartus|libraries|megafunctions|stratix_pll.inc
+5f8211898149ceae8264a0ea5036254f
+}
+# hierarchies {
+vpll:inst1|altpll:altpll_component
+}
+# lmf
+|opt|quartus|quartus|lmf|synplcty.lmf
+3057712873b497a38b70a3917f30cc38
+# macro_sequence
+
+# end
+# complete
+\r
\ No newline at end of file
diff --git a/bsp3/Designflow/ppr/download/db/vga_pll.lpc.html b/bsp3/Designflow/ppr/download/db/vga_pll.lpc.html
new file mode 100644 (file)
index 0000000..ebfddf5
--- /dev/null
@@ -0,0 +1,82 @@
+<TABLE BORDER="1" cellspacing="1" cellpadding="2">
+<TR valign="middle" bgcolor="#C0C0C0">
+<TH>Hierarchy</TH>
+<TH>Input</TH>
+<TH>Constant Input</TH>
+<TH>Unused Input</TH>
+<TH>Floating Input</TH>
+<TH>Output</TH>
+<TH>Constant Output</TH>
+<TH>Unused Output</TH>
+<TH>Floating Output</TH>
+<TH>Bidir</TH>
+<TH>Constant Bidir</TH>
+<TH>Unused Bidir</TH>
+<TH>Input only Bidir</TH>
+<TH>Output only Bidir</TH>
+</TR>
+<TR valign="middle">
+<TD ALIGN="LEFT">inst1</TD>
+<TD ALIGN="LEFT">1</TD>
+<TD ALIGN="LEFT">0</TD>
+<TD ALIGN="LEFT">0</TD>
+<TD ALIGN="LEFT">0</TD>
+<TD ALIGN="LEFT">1</TD>
+<TD ALIGN="LEFT">0</TD>
+<TD ALIGN="LEFT">0</TD>
+<TD ALIGN="LEFT">0</TD>
+<TD ALIGN="LEFT">0</TD>
+<TD ALIGN="LEFT">0</TD>
+<TD ALIGN="LEFT">0</TD>
+<TD ALIGN="LEFT">0</TD>
+<TD ALIGN="LEFT">0</TD>
+</TR>
+<TR valign="middle">
+<TD ALIGN="LEFT">inst|vga_control_unit</TD>
+<TD ALIGN="LEFT">14</TD>
+<TD ALIGN="LEFT">0</TD>
+<TD ALIGN="LEFT">0</TD>
+<TD ALIGN="LEFT">0</TD>
+<TD ALIGN="LEFT">3</TD>
+<TD ALIGN="LEFT">0</TD>
+<TD ALIGN="LEFT">0</TD>
+<TD ALIGN="LEFT">0</TD>
+<TD ALIGN="LEFT">0</TD>
+<TD ALIGN="LEFT">0</TD>
+<TD ALIGN="LEFT">0</TD>
+<TD ALIGN="LEFT">0</TD>
+<TD ALIGN="LEFT">0</TD>
+</TR>
+<TR valign="middle">
+<TD ALIGN="LEFT">inst|vga_driver_unit</TD>
+<TD ALIGN="LEFT">4</TD>
+<TD ALIGN="LEFT">0</TD>
+<TD ALIGN="LEFT">0</TD>
+<TD ALIGN="LEFT">0</TD>
+<TD ALIGN="LEFT">62</TD>
+<TD ALIGN="LEFT">0</TD>
+<TD ALIGN="LEFT">0</TD>
+<TD ALIGN="LEFT">0</TD>
+<TD ALIGN="LEFT">0</TD>
+<TD ALIGN="LEFT">0</TD>
+<TD ALIGN="LEFT">0</TD>
+<TD ALIGN="LEFT">0</TD>
+<TD ALIGN="LEFT">0</TD>
+</TR>
+<TR valign="middle">
+<TD ALIGN="LEFT">inst</TD>
+<TD ALIGN="LEFT">2</TD>
+<TD ALIGN="LEFT">0</TD>
+<TD ALIGN="LEFT">0</TD>
+<TD ALIGN="LEFT">0</TD>
+<TD ALIGN="LEFT">89</TD>
+<TD ALIGN="LEFT">0</TD>
+<TD ALIGN="LEFT">0</TD>
+<TD ALIGN="LEFT">0</TD>
+<TD ALIGN="LEFT">0</TD>
+<TD ALIGN="LEFT">0</TD>
+<TD ALIGN="LEFT">0</TD>
+<TD ALIGN="LEFT">0</TD>
+<TD ALIGN="LEFT">0</TD>
+</TR>
+</TABLE>
diff --git a/bsp3/Designflow/ppr/download/db/vga_pll.lpc.rdb b/bsp3/Designflow/ppr/download/db/vga_pll.lpc.rdb
new file mode 100644 (file)
index 0000000..19666b5
Binary files /dev/null and b/bsp3/Designflow/ppr/download/db/vga_pll.lpc.rdb differ
diff --git a/bsp3/Designflow/ppr/download/db/vga_pll.lpc.txt b/bsp3/Designflow/ppr/download/db/vga_pll.lpc.txt
new file mode 100644 (file)
index 0000000..e54f959
--- /dev/null
@@ -0,0 +1,10 @@
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Legal Partition Candidates                                                                                                                                                                                                 ;
++-----------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
+; Hierarchy             ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
++-----------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
+; inst1                 ; 1     ; 0              ; 0            ; 0              ; 1      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|vga_control_unit ; 14    ; 0              ; 0            ; 0              ; 3      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|vga_driver_unit  ; 4     ; 0              ; 0            ; 0              ; 62     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst                  ; 2     ; 0              ; 0            ; 0              ; 89     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
++-----------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
diff --git a/bsp3/Designflow/ppr/download/db/vga_pll.map.cdb b/bsp3/Designflow/ppr/download/db/vga_pll.map.cdb
new file mode 100644 (file)
index 0000000..2ac03ac
Binary files /dev/null and b/bsp3/Designflow/ppr/download/db/vga_pll.map.cdb differ
diff --git a/bsp3/Designflow/ppr/download/db/vga_pll.map.hdb b/bsp3/Designflow/ppr/download/db/vga_pll.map.hdb
new file mode 100644 (file)
index 0000000..5e65aef
Binary files /dev/null and b/bsp3/Designflow/ppr/download/db/vga_pll.map.hdb differ
diff --git a/bsp3/Designflow/ppr/download/db/vga_pll.map.logdb b/bsp3/Designflow/ppr/download/db/vga_pll.map.logdb
new file mode 100644 (file)
index 0000000..626799f
--- /dev/null
@@ -0,0 +1 @@
+v1
diff --git a/bsp3/Designflow/ppr/download/db/vga_pll.map.qmsg b/bsp3/Designflow/ppr/download/db/vga_pll.map.qmsg
new file mode 100644 (file)
index 0000000..a68b756
--- /dev/null
@@ -0,0 +1,21 @@
+{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 132 02/25/2009 SJ Full Version " "Info: Version 9.0 Build 132 02/25/2009 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Thu Oct 29 17:12:28 2009 " "Info: Processing started: Thu Oct 29 17:12:28 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off vga_pll -c vga_pll " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off vga_pll -c vga_pll" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
+{ "Info" "IACF_REVISION_DEFAULT_FILE_CREATED" "vga_pll 6.0 /homes/burban/didelu/dide_16/bsp3/Designflow/ppr/download/vga_pll_assignment_defaults.qdf " "Info: Revision \"vga_pll\" was previously opened in Quartus II software version 6.0. Created Quartus II Default Settings File /homes/burban/didelu/dide_16/bsp3/Designflow/ppr/download/vga_pll_assignment_defaults.qdf, which contains the default assignment setting information from Quartus II software version 6.0." {  } {  } 0 0 "Revision \"%1!s!\" was previously opened in Quartus II software version %2!s!. Created Quartus II Default Settings File %3!s!, which contains the default assignment setting information from Quartus II software version %2!s!." 0 0 "" 0 -1}
+{ "Info" "IACF_WHERE_TO_VIEW_DEFAULT_CHANGES" "/opt/quartus/quartus/linux/assignment_defaults.qdf " "Info: Default assignment values were changed in the current version of the Quartus II software -- changes to default assignments values are contained in file /opt/quartus/quartus/linux/assignment_defaults.qdf" {  } {  } 0 0 "Default assignment values were changed in the current version of the Quartus II software -- changes to default assignments values are contained in file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../src/vga_pll.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../src/vga_pll.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 vga_pll " "Info: Found entity 1: vga_pll" {  } { { "../../src/vga_pll.bdf" "" { Schematic "/homes/burban/didelu/dide_16/bsp3/Designflow/src/vga_pll.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../syn/rev_1/vga.vqm 3 3 " "Info: Found 3 design units, including 3 entities, in source file ../../syn/rev_1/vga.vqm" { { "Info" "ISGN_ENTITY_NAME" "1 vga_driver " "Info: Found entity 1: vga_driver" {  } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 25 18 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "2 vga_control " "Info: Found entity 2: vga_control" {  } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 3149 19 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "3 vga " "Info: Found entity 3: vga" {  } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 3424 11 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../src/vpll.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ../../src/vpll.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 vpll-SYN " "Info: Found design unit 1: vpll-SYN" {  } { { "../../src/vpll.vhd" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/src/vpll.vhd" 57 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 vpll " "Info: Found entity 1: vpll" {  } { { "../../src/vpll.vhd" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/src/vpll.vhd" 45 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_START_ELABORATION_TOP" "vga_pll " "Info: Elaborating entity \"vga_pll\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "vga vga:inst " "Info: Elaborating entity \"vga\" for hierarchy \"vga:inst\"" {  } { { "../../src/vga_pll.bdf" "inst" { Schematic "/homes/burban/didelu/dide_16/bsp3/Designflow/src/vga_pll.bdf" { { 56 696 912 568 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "vga_driver vga:inst\|vga_driver:vga_driver_unit " "Info: Elaborating entity \"vga_driver\" for hierarchy \"vga:inst\|vga_driver:vga_driver_unit\"" {  } { { "../../syn/rev_1/vga.vqm" "vga_driver_unit" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 4836 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "vga_control vga:inst\|vga_control:vga_control_unit " "Info: Elaborating entity \"vga_control\" for hierarchy \"vga:inst\|vga_control:vga_control_unit\"" {  } { { "../../syn/rev_1/vga.vqm" "vga_control_unit" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 4856 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "vpll vpll:inst1 " "Info: Elaborating entity \"vpll\" for hierarchy \"vpll:inst1\"" {  } { { "../../src/vga_pll.bdf" "inst1" { Schematic "/homes/burban/didelu/dide_16/bsp3/Designflow/src/vga_pll.bdf" { { 56 408 504 152 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
+{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "locked vpll.vhd(73) " "Warning (10036): Verilog HDL or VHDL warning at vpll.vhd(73): object \"locked\" assigned a value but never read" {  } { { "../../src/vpll.vhd" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/src/vpll.vhd" 73 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0 -1}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll vpll:inst1\|altpll:altpll_component " "Info: Elaborating entity \"altpll\" for hierarchy \"vpll:inst1\|altpll:altpll_component\"" {  } { { "../../src/vpll.vhd" "altpll_component" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/src/vpll.vhd" 121 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
+{ "Info" "ISGN_ELABORATION_HEADER" "vpll:inst1\|altpll:altpll_component " "Info: Elaborated megafunction instantiation \"vpll:inst1\|altpll:altpll_component\"" {  } { { "../../src/vpll.vhd" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/src/vpll.vhd" 121 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
+{ "Info" "ISGN_MEGAFN_PARAM_TOP" "vpll:inst1\|altpll:altpll_component " "Info: Instantiated megafunction \"vpll:inst1\|altpll:altpll_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "bandwidth_type AUTO " "Info: Parameter \"bandwidth_type\" = \"AUTO\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_duty_cycle 50 " "Info: Parameter \"clk0_duty_cycle\" = \"50\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altpll " "Info: Parameter \"lpm_type\" = \"altpll\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_multiply_by 5435 " "Info: Parameter \"clk0_multiply_by\" = \"5435\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "invalid_lock_multiplier 5 " "Info: Parameter \"invalid_lock_multiplier\" = \"5\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "inclk0_input_frequency 30003 " "Info: Parameter \"inclk0_input_frequency\" = \"30003\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "gate_lock_signal NO " "Info: Parameter \"gate_lock_signal\" = \"NO\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_divide_by 6666 " "Info: Parameter \"clk0_divide_by\" = \"6666\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_type AUTO " "Info: Parameter \"pll_type\" = \"AUTO\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "valid_lock_multiplier 1 " "Info: Parameter \"valid_lock_multiplier\" = \"1\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_time_delay 0 " "Info: Parameter \"clk0_time_delay\" = \"0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "spread_frequency 0 " "Info: Parameter \"spread_frequency\" = \"0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Stratix " "Info: Parameter \"intended_device_family\" = \"Stratix\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode NORMAL " "Info: Parameter \"operation_mode\" = \"NORMAL\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "compensate_clock CLK0 " "Info: Parameter \"compensate_clock\" = \"CLK0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_phase_shift 0 " "Info: Parameter \"clk0_phase_shift\" = \"0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1}  } { { "../../src/vpll.vhd" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/src/vpll.vhd" 121 0 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1}
+{ "Info" "ISCL_SCL_WYSIWYG_UNMAPPED_IO_HDR" "" "Info: WYSIWYG I/O primitives converted to equivalent logic" { { "Info" "ISCL_SCL_WYSIWYG_UNMAPPED_IO" "vga:inst\|clk_pin_in " "Info: WYSIWYG I/O primitive \"vga:inst\|clk_pin_in\" converted to equivalent logic" {  } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 3608 3 0 } } { "../../src/vga_pll.bdf" "" { Schematic "/homes/burban/didelu/dide_16/bsp3/Designflow/src/vga_pll.bdf" { { 56 696 912 568 "inst" "" } } } }  } 0 0 "WYSIWYG I/O primitive \"%1!s!\" converted to equivalent logic" 0 0 "" 0 -1}  } {  } 0 0 "WYSIWYG I/O primitives converted to equivalent logic" 0 0 "" 0 -1}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "235 " "Info: Implemented 235 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_OPINS" "89 " "Info: Implemented 89 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_LCELLS" "143 " "Info: Implemented 143 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_PLLS" "1 " "Info: Implemented 1 ClockLock PLLs" {  } {  } 0 0 "Implemented %1!d! ClockLock PLLs" 0 0 "" 0 -1}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 -1}
+{ "Warning" "WCUT_CUT_YGR_PLL_BAD_FANOUT_CLK3" "clk0 vpll:inst1\|altpll:altpll_component\|pll " "Warning: Output port clk0 of PLL \"vpll:inst1\|altpll:altpll_component\|pll\" feeds an output pin via global clocks -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance" {  } { { "altpll.tdf" "" { Text "/opt/quartus/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } } { "../../src/vpll.vhd" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/src/vpll.vhd" 121 0 0 } } { "../../src/vga_pll.bdf" "" { Schematic "/homes/burban/didelu/dide_16/bsp3/Designflow/src/vga_pll.bdf" { { 56 408 504 152 "inst1" "" } } } }  } 0 0 "Output port %1!s! of PLL \"%2!s!\" feeds an output pin via global clocks -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance" 0 0 "" 0 -1}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 2 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "204 " "Info: Peak virtual memory: 204 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Thu Oct 29 17:12:32 2009 " "Info: Processing ended: Thu Oct 29 17:12:32 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Info: Total CPU time (on all processors): 00:00:03" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
diff --git a/bsp3/Designflow/ppr/download/db/vga_pll.pre_map.cdb b/bsp3/Designflow/ppr/download/db/vga_pll.pre_map.cdb
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diff --git a/bsp3/Designflow/ppr/download/db/vga_pll.pre_map.hdb b/bsp3/Designflow/ppr/download/db/vga_pll.pre_map.hdb
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index 0000000..12ba5ee
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diff --git a/bsp3/Designflow/ppr/download/db/vga_pll.rtlv.hdb b/bsp3/Designflow/ppr/download/db/vga_pll.rtlv.hdb
new file mode 100644 (file)
index 0000000..4c58fe5
Binary files /dev/null and b/bsp3/Designflow/ppr/download/db/vga_pll.rtlv.hdb differ
diff --git a/bsp3/Designflow/ppr/download/db/vga_pll.rtlv_sg.cdb b/bsp3/Designflow/ppr/download/db/vga_pll.rtlv_sg.cdb
new file mode 100644 (file)
index 0000000..48289e1
Binary files /dev/null and b/bsp3/Designflow/ppr/download/db/vga_pll.rtlv_sg.cdb differ
diff --git a/bsp3/Designflow/ppr/download/db/vga_pll.rtlv_sg_swap.cdb b/bsp3/Designflow/ppr/download/db/vga_pll.rtlv_sg_swap.cdb
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index 0000000..5cfbeaa
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diff --git a/bsp3/Designflow/ppr/download/db/vga_pll.sgdiff.cdb b/bsp3/Designflow/ppr/download/db/vga_pll.sgdiff.cdb
new file mode 100644 (file)
index 0000000..5dc944c
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diff --git a/bsp3/Designflow/ppr/download/db/vga_pll.sgdiff.hdb b/bsp3/Designflow/ppr/download/db/vga_pll.sgdiff.hdb
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index 0000000..ceac3fc
Binary files /dev/null and b/bsp3/Designflow/ppr/download/db/vga_pll.sgdiff.hdb differ
diff --git a/bsp3/Designflow/ppr/download/db/vga_pll.sld_design_entry.sci b/bsp3/Designflow/ppr/download/db/vga_pll.sld_design_entry.sci
new file mode 100644 (file)
index 0000000..57580ed
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diff --git a/bsp3/Designflow/ppr/download/db/vga_pll.sld_design_entry_dsc.sci b/bsp3/Designflow/ppr/download/db/vga_pll.sld_design_entry_dsc.sci
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diff --git a/bsp3/Designflow/ppr/download/db/vga_pll.tan.qmsg b/bsp3/Designflow/ppr/download/db/vga_pll.tan.qmsg
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+{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 132 02/25/2009 SJ Full Version " "Info: Version 9.0 Build 132 02/25/2009 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Thu Oct 29 17:13:27 2009 " "Info: Processing started: Thu Oct 29 17:13:27 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off vga_pll -c vga_pll --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off vga_pll -c vga_pll --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Info: Parallel compilation is enabled and will use 2 of the 2 processors detected" {  } {  } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1}
+{ "Warning" "WTAN_USE_ENABLE_CLOCK_LATENCY_FOR_PLL" "" "Warning: Clock latency analysis for PLL offsets is supported for the current device family, but is not enabled" {  } {  } 0 0 "Clock latency analysis for PLL offsets is supported for the current device family, but is not enabled" 0 0 "" 0 -1}
+{ "Info" "ITAN_SLACK_ANALYSIS" "" "Info: Found timing assignments -- calculating delays" {  } {  } 0 0 "Found timing assignments -- calculating delays" 0 0 "" 0 -1}
+{ "Info" "ITDB_FULL_SLACK_RESULT" "vpll:inst1\|altpll:altpll_component\|_clk0 register vga:inst\|vga_driver:vga_driver_unit\|column_counter_sig_9 register vga:inst\|vga_control:vga_control_unit\|b 29.381 ns " "Info: Slack time is 29.381 ns for clock \"vpll:inst1\|altpll:altpll_component\|_clk0\" between source register \"vga:inst\|vga_driver:vga_driver_unit\|column_counter_sig_9\" and destination register \"vga:inst\|vga_control:vga_control_unit\|b\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "135.21 MHz 7.396 ns " "Info: Fmax is 135.21 MHz (period= 7.396 ns)" {  } {  } 0 0 "Fmax is %1!s! (period= %2!s!)" 0 0 "" 0 -1} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "36.604 ns + Largest register register " "Info: + Largest register to register requirement is 36.604 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "36.777 ns + " "Info: + Setup relationship between source and destination is 36.777 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 35.747 ns " "Info: + Latch edge is 35.747 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination vpll:inst1\|altpll:altpll_component\|_clk0 36.777 ns -1.030 ns  50 " "Info: Clock period of Destination clock \"vpll:inst1\|altpll:altpll_component\|_clk0\" is 36.777 ns with  offset of -1.030 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_EDGE_RESULT" "- Launch -1.030 ns " "Info: - Launch edge is -1.030 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source vpll:inst1\|altpll:altpll_component\|_clk0 36.777 ns -1.030 ns  50 " "Info: Clock period of Source clock \"vpll:inst1\|altpll:altpll_component\|_clk0\" is 36.777 ns with  offset of -1.030 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 -1}  } {  } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.013 ns + Largest " "Info: + Largest clock skew is 0.013 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "vpll:inst1\|altpll:altpll_component\|_clk0 destination 2.053 ns + Shortest register " "Info: + Shortest clock path from clock \"vpll:inst1\|altpll:altpll_component\|_clk0\" to destination register is 2.053 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns vpll:inst1\|altpll:altpll_component\|_clk0 1 CLK PLL_1 63 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 63; CLK Node = 'vpll:inst1\|altpll:altpll_component\|_clk0'" {  } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { vpll:inst1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "/opt/quartus/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.493 ns) + CELL(0.560 ns) 2.053 ns vga:inst\|vga_control:vga_control_unit\|b 2 REG LC_X78_Y32_N4 3 " "Info: 2: + IC(1.493 ns) + CELL(0.560 ns) = 2.053 ns; Loc. = LC_X78_Y32_N4; Fanout = 3; REG Node = 'vga:inst\|vga_control:vga_control_unit\|b'" {  } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.053 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_control:vga_control_unit|b } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 3185 11 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.560 ns ( 27.28 % ) " "Info: Total cell delay = 0.560 ns ( 27.28 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.493 ns ( 72.72 % ) " "Info: Total interconnect delay = 1.493 ns ( 72.72 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.053 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_control:vga_control_unit|b } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "2.053 ns" { vpll:inst1|altpll:altpll_component|_clk0 {} vga:inst|vga_control:vga_control_unit|b {} } { 0.000ns 1.493ns } { 0.000ns 0.560ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "vpll:inst1\|altpll:altpll_component\|_clk0 source 2.040 ns - Longest register " "Info: - Longest clock path from clock \"vpll:inst1\|altpll:altpll_component\|_clk0\" to source register is 2.040 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns vpll:inst1\|altpll:altpll_component\|_clk0 1 CLK PLL_1 63 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 63; CLK Node = 'vpll:inst1\|altpll:altpll_component\|_clk0'" {  } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { vpll:inst1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "/opt/quartus/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.480 ns) + CELL(0.560 ns) 2.040 ns vga:inst\|vga_driver:vga_driver_unit\|column_counter_sig_9 2 REG LC_X78_Y33_N0 4 " "Info: 2: + IC(1.480 ns) + CELL(0.560 ns) = 2.040 ns; Loc. = LC_X78_Y33_N0; Fanout = 4; REG Node = 'vga:inst\|vga_driver:vga_driver_unit\|column_counter_sig_9'" {  } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.040 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_driver:vga_driver_unit|column_counter_sig_9 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 128 30 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.560 ns ( 27.45 % ) " "Info: Total cell delay = 0.560 ns ( 27.45 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.480 ns ( 72.55 % ) " "Info: Total interconnect delay = 1.480 ns ( 72.55 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.040 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_driver:vga_driver_unit|column_counter_sig_9 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "2.040 ns" { vpll:inst1|altpll:altpll_component|_clk0 {} vga:inst|vga_driver:vga_driver_unit|column_counter_sig_9 {} } { 0.000ns 1.480ns } { 0.000ns 0.560ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1}  } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.053 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_control:vga_control_unit|b } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "2.053 ns" { vpll:inst1|altpll:altpll_component|_clk0 {} vga:inst|vga_control:vga_control_unit|b {} } { 0.000ns 1.493ns } { 0.000ns 0.560ns } "" } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.040 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_driver:vga_driver_unit|column_counter_sig_9 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "2.040 ns" { vpll:inst1|altpll:altpll_component|_clk0 {} vga:inst|vga_driver:vga_driver_unit|column_counter_sig_9 {} } { 0.000ns 1.480ns } { 0.000ns 0.560ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.176 ns - " "Info: - Micro clock to output delay of source is 0.176 ns" {  } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 128 30 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns - " "Info: - Micro setup delay of destination is 0.010 ns" {  } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 3185 11 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1}  } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.053 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_control:vga_control_unit|b } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "2.053 ns" { vpll:inst1|altpll:altpll_component|_clk0 {} vga:inst|vga_control:vga_control_unit|b {} } { 0.000ns 1.493ns } { 0.000ns 0.560ns } "" } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.040 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_driver:vga_driver_unit|column_counter_sig_9 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "2.040 ns" { vpll:inst1|altpll:altpll_component|_clk0 {} vga:inst|vga_driver:vga_driver_unit|column_counter_sig_9 {} } { 0.000ns 1.480ns } { 0.000ns 0.560ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.223 ns - Longest register register " "Info: - Longest register to register delay is 7.223 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns vga:inst\|vga_driver:vga_driver_unit\|column_counter_sig_9 1 REG LC_X78_Y33_N0 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X78_Y33_N0; Fanout = 4; REG Node = 'vga:inst\|vga_driver:vga_driver_unit\|column_counter_sig_9'" {  } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { vga:inst|vga_driver:vga_driver_unit|column_counter_sig_9 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 128 30 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.360 ns) + CELL(0.087 ns) 2.447 ns vga:inst\|vga_control:vga_control_unit\|r_next_i_o7 2 COMB LC_X56_Y45_N5 3 " "Info: 2: + IC(2.360 ns) + CELL(0.087 ns) = 2.447 ns; Loc. = LC_X56_Y45_N5; Fanout = 3; COMB Node = 'vga:inst\|vga_control:vga_control_unit\|r_next_i_o7'" {  } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.447 ns" { vga:inst|vga_driver:vga_driver_unit|column_counter_sig_9 vga:inst|vga_control:vga_control_unit|r_next_i_o7 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 3207 19 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.773 ns) + CELL(0.332 ns) 5.552 ns vga:inst\|vga_control:vga_control_unit\|N_6_i_0_g0_0 3 COMB LC_X76_Y33_N4 1 " "Info: 3: + IC(2.773 ns) + CELL(0.332 ns) = 5.552 ns; Loc. = LC_X76_Y33_N4; Fanout = 1; COMB Node = 'vga:inst\|vga_control:vga_control_unit\|N_6_i_0_g0_0'" {  } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "3.105 ns" { vga:inst|vga_control:vga_control_unit|r_next_i_o7 vga:inst|vga_control:vga_control_unit|N_6_i_0_g0_0 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 3205 20 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.307 ns) + CELL(0.364 ns) 7.223 ns vga:inst\|vga_control:vga_control_unit\|b 4 REG LC_X78_Y32_N4 3 " "Info: 4: + IC(1.307 ns) + CELL(0.364 ns) = 7.223 ns; Loc. = LC_X78_Y32_N4; Fanout = 3; REG Node = 'vga:inst\|vga_control:vga_control_unit\|b'" {  } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "1.671 ns" { vga:inst|vga_control:vga_control_unit|N_6_i_0_g0_0 vga:inst|vga_control:vga_control_unit|b } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 3185 11 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.783 ns ( 10.84 % ) " "Info: Total cell delay = 0.783 ns ( 10.84 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "6.440 ns ( 89.16 % ) " "Info: Total interconnect delay = 6.440 ns ( 89.16 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "7.223 ns" { vga:inst|vga_driver:vga_driver_unit|column_counter_sig_9 vga:inst|vga_control:vga_control_unit|r_next_i_o7 vga:inst|vga_control:vga_control_unit|N_6_i_0_g0_0 vga:inst|vga_control:vga_control_unit|b } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "7.223 ns" { vga:inst|vga_driver:vga_driver_unit|column_counter_sig_9 {} vga:inst|vga_control:vga_control_unit|r_next_i_o7 {} vga:inst|vga_control:vga_control_unit|N_6_i_0_g0_0 {} vga:inst|vga_control:vga_control_unit|b {} } { 0.000ns 2.360ns 2.773ns 1.307ns } { 0.000ns 0.087ns 0.332ns 0.364ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1}  } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.053 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_control:vga_control_unit|b } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "2.053 ns" { vpll:inst1|altpll:altpll_component|_clk0 {} vga:inst|vga_control:vga_control_unit|b {} } { 0.000ns 1.493ns } { 0.000ns 0.560ns } "" } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.040 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_driver:vga_driver_unit|column_counter_sig_9 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "2.040 ns" { vpll:inst1|altpll:altpll_component|_clk0 {} vga:inst|vga_driver:vga_driver_unit|column_counter_sig_9 {} } { 0.000ns 1.480ns } { 0.000ns 0.560ns } "" } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "7.223 ns" { vga:inst|vga_driver:vga_driver_unit|column_counter_sig_9 vga:inst|vga_control:vga_control_unit|r_next_i_o7 vga:inst|vga_control:vga_control_unit|N_6_i_0_g0_0 vga:inst|vga_control:vga_control_unit|b } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "7.223 ns" { vga:inst|vga_driver:vga_driver_unit|column_counter_sig_9 {} vga:inst|vga_control:vga_control_unit|r_next_i_o7 {} vga:inst|vga_control:vga_control_unit|N_6_i_0_g0_0 {} vga:inst|vga_control:vga_control_unit|b {} } { 0.000ns 2.360ns 2.773ns 1.307ns } { 0.000ns 0.087ns 0.332ns 0.364ns } "" } }  } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0 -1}
+{ "Info" "ITAN_NO_REG2REG_EXIST" "board_clk " "Info: No valid register-to-register data paths exist for clock \"board_clk\"" {  } {  } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0 "" 0 -1}
+{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "vpll:inst1\|altpll:altpll_component\|_clk0 register vga:inst\|vga_driver:vga_driver_unit\|vsync_counter_9 register vga:inst\|vga_driver:vga_driver_unit\|vsync_counter_9 737 ps " "Info: Minimum slack time is 737 ps for clock \"vpll:inst1\|altpll:altpll_component\|_clk0\" between source register \"vga:inst\|vga_driver:vga_driver_unit\|vsync_counter_9\" and destination register \"vga:inst\|vga_driver:vga_driver_unit\|vsync_counter_9\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.661 ns + Shortest register register " "Info: + Shortest register to register delay is 0.661 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns vga:inst\|vga_driver:vga_driver_unit\|vsync_counter_9 1 REG LC_X35_Y33_N9 9 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X35_Y33_N9; Fanout = 9; REG Node = 'vga:inst\|vga_driver:vga_driver_unit\|vsync_counter_9'" {  } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 129 25 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.426 ns) + CELL(0.235 ns) 0.661 ns vga:inst\|vga_driver:vga_driver_unit\|vsync_counter_9 2 REG LC_X35_Y33_N9 9 " "Info: 2: + IC(0.426 ns) + CELL(0.235 ns) = 0.661 ns; Loc. = LC_X35_Y33_N9; Fanout = 9; REG Node = 'vga:inst\|vga_driver:vga_driver_unit\|vsync_counter_9'" {  } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "0.661 ns" { vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 129 25 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.235 ns ( 35.55 % ) " "Info: Total cell delay = 0.235 ns ( 35.55 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "0.426 ns ( 64.45 % ) " "Info: Total interconnect delay = 0.426 ns ( 64.45 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "0.661 ns" { vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "0.661 ns" { vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 {} vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 {} } { 0.000ns 0.426ns } { 0.000ns 0.235ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "-0.076 ns - Smallest register register " "Info: - Smallest register to register requirement is -0.076 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch -1.030 ns " "Info: + Latch edge is -1.030 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination vpll:inst1\|altpll:altpll_component\|_clk0 36.777 ns -1.030 ns  50 " "Info: Clock period of Destination clock \"vpll:inst1\|altpll:altpll_component\|_clk0\" is 36.777 ns with  offset of -1.030 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_EDGE_RESULT" "- Launch -1.030 ns " "Info: - Launch edge is -1.030 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source vpll:inst1\|altpll:altpll_component\|_clk0 36.777 ns -1.030 ns  50 " "Info: Clock period of Source clock \"vpll:inst1\|altpll:altpll_component\|_clk0\" is 36.777 ns with  offset of -1.030 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 -1}  } {  } 0 0 "%2!c! Hold relationship between source and destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Smallest " "Info: + Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "vpll:inst1\|altpll:altpll_component\|_clk0 destination 2.054 ns + Longest register " "Info: + Longest clock path from clock \"vpll:inst1\|altpll:altpll_component\|_clk0\" to destination register is 2.054 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns vpll:inst1\|altpll:altpll_component\|_clk0 1 CLK PLL_1 63 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 63; CLK Node = 'vpll:inst1\|altpll:altpll_component\|_clk0'" {  } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { vpll:inst1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "/opt/quartus/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.494 ns) + CELL(0.560 ns) 2.054 ns vga:inst\|vga_driver:vga_driver_unit\|vsync_counter_9 2 REG LC_X35_Y33_N9 9 " "Info: 2: + IC(1.494 ns) + CELL(0.560 ns) = 2.054 ns; Loc. = LC_X35_Y33_N9; Fanout = 9; REG Node = 'vga:inst\|vga_driver:vga_driver_unit\|vsync_counter_9'" {  } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.054 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 129 25 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.560 ns ( 27.26 % ) " "Info: Total cell delay = 0.560 ns ( 27.26 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.494 ns ( 72.74 % ) " "Info: Total interconnect delay = 1.494 ns ( 72.74 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.054 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "2.054 ns" { vpll:inst1|altpll:altpll_component|_clk0 {} vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 {} } { 0.000ns 1.494ns } { 0.000ns 0.560ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "vpll:inst1\|altpll:altpll_component\|_clk0 source 2.054 ns - Shortest register " "Info: - Shortest clock path from clock \"vpll:inst1\|altpll:altpll_component\|_clk0\" to source register is 2.054 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns vpll:inst1\|altpll:altpll_component\|_clk0 1 CLK PLL_1 63 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 63; CLK Node = 'vpll:inst1\|altpll:altpll_component\|_clk0'" {  } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { vpll:inst1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "/opt/quartus/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.494 ns) + CELL(0.560 ns) 2.054 ns vga:inst\|vga_driver:vga_driver_unit\|vsync_counter_9 2 REG LC_X35_Y33_N9 9 " "Info: 2: + IC(1.494 ns) + CELL(0.560 ns) = 2.054 ns; Loc. = LC_X35_Y33_N9; Fanout = 9; REG Node = 'vga:inst\|vga_driver:vga_driver_unit\|vsync_counter_9'" {  } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.054 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 129 25 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.560 ns ( 27.26 % ) " "Info: Total cell delay = 0.560 ns ( 27.26 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.494 ns ( 72.74 % ) " "Info: Total interconnect delay = 1.494 ns ( 72.74 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.054 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "2.054 ns" { vpll:inst1|altpll:altpll_component|_clk0 {} vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 {} } { 0.000ns 1.494ns } { 0.000ns 0.560ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1}  } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.054 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "2.054 ns" { vpll:inst1|altpll:altpll_component|_clk0 {} vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 {} } { 0.000ns 1.494ns } { 0.000ns 0.560ns } "" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "2.054 ns" { vpll:inst1|altpll:altpll_component|_clk0 {} vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 {} } { 0.000ns 1.494ns } { 0.000ns 0.560ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.176 ns - " "Info: - Micro clock to output delay of source is 0.176 ns" {  } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 129 25 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TH_DELAY" "0.100 ns + " "Info: + Micro hold delay of destination is 0.100 ns" {  } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 129 25 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 -1}  } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.054 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "2.054 ns" { vpll:inst1|altpll:altpll_component|_clk0 {} vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 {} } { 0.000ns 1.494ns } { 0.000ns 0.560ns } "" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "2.054 ns" { vpll:inst1|altpll:altpll_component|_clk0 {} vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 {} } { 0.000ns 1.494ns } { 0.000ns 0.560ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0 -1}  } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "0.661 ns" { vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "0.661 ns" { vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 {} vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 {} } { 0.000ns 0.426ns } { 0.000ns 0.235ns } "" } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.054 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "2.054 ns" { vpll:inst1|altpll:altpll_component|_clk0 {} vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 {} } { 0.000ns 1.494ns } { 0.000ns 0.560ns } "" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "2.054 ns" { vpll:inst1|altpll:altpll_component|_clk0 {} vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 {} } { 0.000ns 1.494ns } { 0.000ns 0.560ns } "" } }  } 0 0 "Minimum slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0 -1}
+{ "Info" "ITDB_TSU_RESULT" "vga:inst\|vga_driver:vga_driver_unit\|h_enable_sig reset board_clk 11.030 ns register " "Info: tsu for register \"vga:inst\|vga_driver:vga_driver_unit\|h_enable_sig\" (data pin = \"reset\", clock pin = \"board_clk\") is 11.030 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "12.049 ns + Longest pin register " "Info: + Longest pin to register delay is 12.049 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.141 ns) 1.141 ns reset 1 PIN PIN_A5 10 " "Info: 1: + IC(0.000 ns) + CELL(1.141 ns) = 1.141 ns; Loc. = PIN_A5; Fanout = 10; PIN Node = 'reset'" {  } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "../../src/vga_pll.bdf" "" { Schematic "/homes/burban/didelu/dide_16/bsp3/Designflow/src/vga_pll.bdf" { { 96 528 696 112 "reset" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(5.711 ns) + CELL(0.459 ns) 7.311 ns vga:inst\|vga_driver:vga_driver_unit\|un6_dly_counter_0_x 2 COMB LC_X36_Y33_N7 32 " "Info: 2: + IC(5.711 ns) + CELL(0.459 ns) = 7.311 ns; Loc. = LC_X36_Y33_N7; Fanout = 32; COMB Node = 'vga:inst\|vga_driver:vga_driver_unit\|un6_dly_counter_0_x'" {  } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "6.170 ns" { reset vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 157 29 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.863 ns) + CELL(0.332 ns) 9.506 ns vga:inst\|vga_driver:vga_driver_unit\|h_enable_sig_1_0_0_0_g0_i_o4 3 COMB LC_X34_Y34_N6 1 " "Info: 3: + IC(1.863 ns) + CELL(0.332 ns) = 9.506 ns; Loc. = LC_X34_Y34_N6; Fanout = 1; COMB Node = 'vga:inst\|vga_driver:vga_driver_unit\|h_enable_sig_1_0_0_0_g0_i_o4'" {  } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.195 ns" { vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x vga:inst|vga_driver:vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 248 36 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.817 ns) + CELL(0.726 ns) 12.049 ns vga:inst\|vga_driver:vga_driver_unit\|h_enable_sig 4 REG LC_X52_Y35_N2 2 " "Info: 4: + IC(1.817 ns) + CELL(0.726 ns) = 12.049 ns; Loc. = LC_X52_Y35_N2; Fanout = 2; REG Node = 'vga:inst\|vga_driver:vga_driver_unit\|h_enable_sig'" {  } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.543 ns" { vga:inst|vga_driver:vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4 vga:inst|vga_driver:vga_driver_unit|h_enable_sig } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 154 22 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.658 ns ( 22.06 % ) " "Info: Total cell delay = 2.658 ns ( 22.06 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "9.391 ns ( 77.94 % ) " "Info: Total interconnect delay = 9.391 ns ( 77.94 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "12.049 ns" { reset vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x vga:inst|vga_driver:vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4 vga:inst|vga_driver:vga_driver_unit|h_enable_sig } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "12.049 ns" { reset {} reset~out0 {} vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x {} vga:inst|vga_driver:vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4 {} vga:inst|vga_driver:vga_driver_unit|h_enable_sig {} } { 0.000ns 0.000ns 5.711ns 1.863ns 1.817ns } { 0.000ns 1.141ns 0.459ns 0.332ns 0.726ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 154 22 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_PLL_OFFSET" "board_clk vpll:inst1\|altpll:altpll_component\|_clk0 -1.030 ns - " "Info: - Offset between input clock \"board_clk\" and output clock \"vpll:inst1\|altpll:altpll_component\|_clk0\" is -1.030 ns" {  } { { "../../src/vga_pll.bdf" "" { Schematic "/homes/burban/didelu/dide_16/bsp3/Designflow/src/vga_pll.bdf" { { 80 240 408 96 "board_clk" "" } } } } { "altpll.tdf" "" { Text "/opt/quartus/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } }  } 0 0 "%4!c! Offset between input clock \"%1!s!\" and output clock \"%2!s!\" is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "vpll:inst1\|altpll:altpll_component\|_clk0 destination 2.059 ns - Shortest register " "Info: - Shortest clock path from clock \"vpll:inst1\|altpll:altpll_component\|_clk0\" to destination register is 2.059 ns" {