bsp3/Designflow/src/vga_pre_tb.vhd

   1 -------------------------------------------------------------------------------
   2 -- Title      : vga testbench
   3 -- Project    :
   4 -------------------------------------------------------------------------------
   5 -- File       : vga_tb.vhd
   6 -- Author     : Thomas Handl
   7 -- Company    : TU Wien
   8 -- Created    : 2004-04-07
   9 -- Last update: 2006-11-21
  10 -- Platform   :
  11 -------------------------------------------------------------------------------
  12 -- Description:
  13 -------------------------------------------------------------------------------
  14 -- Copyright (c) 2004 TU Wien
  15 -------------------------------------------------------------------------------
  16 -- Revisions  :
  17 -- Date        Version  Author  Description
  18 -- 2004-04-07  1.0      handl   Created
  19 -------------------------------------------------------------------------------
  20
  21
  22 -------------------------------------------------------------------------------
  23 -- LIBRARIES
  24 -------------------------------------------------------------------------------
  25
  26 library IEEE;
  27 use IEEE.std_logic_1164.all;
  28 use IEEE.std_logic_unsigned.all;
  29 use IEEE.std_logic_arith.all;
  30
  31 use work.vga_pak.all;
  32
  33
  34 -------------------------------------------------------------------------------
  35 -- ENTITY
  36 -------------------------------------------------------------------------------
  37 entity vga_pre_tb is
  38
  39 end vga_pre_tb;
  40
  41
  42 -------------------------------------------------------------------------------
  43 -- ARCHITECTURE
  44 -------------------------------------------------------------------------------
  45 architecture structure of vga_pre_tb is
  46
  47   constant cc : time := 39.7 ns;        -- test clock period
  48
  49   component vga
  50     port (
  51       clk_pin                                  : in  std_logic;
  52       reset_pin                                : in  std_logic;
  53       r0_pin, r1_pin, r2_pin                   : out std_logic;
  54       g0_pin, g1_pin, g2_pin                   : out std_logic;
  55       b0_pin, b1_pin                           : out std_logic;
  56       hsync_pin                                : out std_logic;
  57       vsync_pin                                : out std_logic;
  58       seven_seg_pin                            : out std_logic_vector(2*SEG_WIDTH-1 downto 0);
  59       d_hsync, d_vsync                         : out std_logic;
  60       d_column_counter                         : out std_logic_vector(COL_CNT_WIDTH-1 downto 0);
  61       d_line_counter                           : out std_logic_vector(LINE_CNT_WIDTH-1 downto 0);
  62       d_set_column_counter, d_set_line_counter : out std_logic;
  63       d_hsync_counter                          : out std_logic_vector(HSYN_CNT_WIDTH-1 downto 0);
  64       d_vsync_counter                          : out std_logic_vector(VSYN_CNT_WIDTH-1 downto 0);
  65       d_set_hsync_counter, d_set_vsync_counter : out std_logic;
  66       d_h_enable                               : out std_logic;
  67       d_v_enable                               : out std_logic;
  68       d_r, d_g, d_b                            : out std_logic;
  69       d_hsync_state                            : out std_logic_vector(0 to 6);
  70       d_vsync_state                            : out std_logic_vector(0 to 6);
  71       d_state_clk                              : out std_logic);
  72   end component;
  73
  74   signal clk_pin                                  : std_logic;
  75   signal reset_pin                                : std_logic;
  76   signal r0_pin, r1_pin, r2_pin                   : std_logic;
  77   signal g0_pin, g1_pin, g2_pin                   : std_logic;
  78   signal b0_pin, b1_pin                           : std_logic;
  79   signal hsync_pin                                : std_logic;
  80   signal vsync_pin                                : std_logic;
  81   signal seven_seg_pin                            : std_logic_vector(2*SEG_WIDTH-1 downto 0);
  82   signal d_hsync, d_vsync                         : std_logic;
  83   signal d_column_counter                         : std_logic_vector(COL_CNT_WIDTH-1 downto 0);
  84   signal d_line_counter                           : std_logic_vector(LINE_CNT_WIDTH-1 downto 0);
  85   signal d_set_column_counter, d_set_line_counter : std_logic;
  86   signal d_hsync_counter                          : std_logic_vector(HSYN_CNT_WIDTH-1 downto 0);
  87   signal d_vsync_counter                          : std_logic_vector(VSYN_CNT_WIDTH-1 downto 0);
  88   signal d_set_hsync_counter, d_set_vsync_counter : std_logic;
  89   signal d_h_enable                               : std_logic;
  90   signal d_v_enable                               : std_logic;
  91   signal d_r, d_g, d_b                            : std_logic;
  92   signal d_hsync_state                            : std_logic_vector(0 to 6);
  93   signal d_vsync_state                            : std_logic_vector(0 to 6);
  94   signal d_state_clk                              : std_logic;
  95   signal clk                                      : std_logic;
  96
  97 begin
  98
  99   vga_unit: vga
 100     port map (
 101       clk_pin              => clk_pin,
 102       reset_pin            => reset_pin,
 103       r0_pin               => r0_pin,
 104       r1_pin               => r1_pin,
 105       r2_pin               => r2_pin,
 106       g0_pin               => g0_pin,
 107       g1_pin               => g1_pin,
 108       g2_pin               => g2_pin,
 109       b0_pin               => b0_pin,
 110       b1_pin               => b1_pin,
 111       hsync_pin            => hsync_pin,
 112       vsync_pin            => vsync_pin,
 113       seven_seg_pin        => seven_seg_pin,
 114       d_hsync              => d_hsync,
 115       d_vsync              => d_vsync,
 116       d_column_counter     => d_column_counter,
 117       d_line_counter       => d_line_counter,
 118       d_set_column_counter => d_set_column_counter,
 119       d_set_line_counter   => d_set_line_counter,
 120       d_hsync_counter      => d_hsync_counter,
 121       d_vsync_counter      => d_vsync_counter,
 122       d_set_hsync_counter  => d_set_hsync_counter,
 123       d_set_vsync_counter  => d_set_vsync_counter,
 124       d_h_enable           => d_h_enable,
 125       d_v_enable           => d_v_enable,
 126       d_r                  => d_r,
 127       d_g                  => d_g,
 128       d_b                  => d_b,
 129       d_hsync_state        => d_hsync_state,
 130       d_vsync_state        => d_vsync_state,
 131       d_state_clk          => d_state_clk);
 132
 133
 134 -------------------------------------------------------------------------------
 135 -- generate simulation clock
 136 -------------------------------------------------------------------------------
 137   CLKGEN : process
 138   begin
 139     clk <= '1';
 140     wait for cc/2;
 141     clk <= '0';
 142     wait for cc/2;
 143   end process CLKGEN;
 144
 145 -------------------------------------------------------------------------------
 146 -- test the design
 147 -------------------------------------------------------------------------------
 148   TEST_IT : process
 149
 150     -- wait for n clock cycles
 151     procedure icwait(cycles : natural) is
 152     begin
 153       for i in 1 to cycles loop
 154         wait until clk = '1' and clk'event;
 155       end loop;
 156     end;
 157
 158   begin
 159     -----------------------------------------------------------------------------
 160     -- initial reset
 161     -----------------------------------------------------------------------------
 162     reset_pin <= '0';
 163     icwait(10);
 164     reset_pin <= '1';
 165     icwait(10000000);
 166
 167     ---------------------------------------------------------------------------
 168     -- exit testbench
 169     ---------------------------------------------------------------------------
 170     assert false
 171       report "Test finished"
 172       severity error;
 173
 174   end process test_it;
 175
 176   clk_pin <= clk;
 177
 178 end structure;
 179
 180 -------------------------------------------------------------------------------
 181 -- configuration
 182 -------------------------------------------------------------------------------
 183 configuration vga_conf_pre of vga_pre_tb is
 184   for structure
 185     for vga_unit : vga use entity work.vga(beh);
 186     end for;
 187   end for;
 188 end vga_conf_pre;
 189
 190
 191