bsp3/Designflow/syn/rev_1/vga.vhm

   1 --
   2 -- Written by Synplicity
   3 -- Product Version "C-2009.06"
   4 -- Program "Synplify Pro", Mapper "map450rc, Build 029R"
   5 -- Thu Oct 29 16:49:33 2009
   6 --
   7
   8 --
   9 -- Written by Synplify Pro version Build 029R
  10 -- Thu Oct 29 16:49:33 2009
  11 --
  12
  13 --
  14 library ieee, stratix;
  15 use ieee.std_logic_1164.all;
  16 use ieee.numeric_std.all;
  17 library synplify;
  18 use synplify.components.all;
  19 use stratix.stratix_components.all;
  20
  21 entity vga_control is
  22 port(
  23   column_counter_sig_1 :  in std_logic;
  24   column_counter_sig_7 :  in std_logic;
  25   column_counter_sig_2 :  in std_logic;
  26   column_counter_sig_0 :  in std_logic;
  27   column_counter_sig_4 :  in std_logic;
  28   column_counter_sig_3 :  in std_logic;
  29   column_counter_sig_5 :  in std_logic;
  30   column_counter_sig_6 :  in std_logic;
  31   h_enable_sig :  in std_logic;
  32   v_enable_sig :  in std_logic;
  33   un10_column_counter_siglt6_1 :  in std_logic;
  34   g :  out std_logic;
  35   un10_column_counter_siglt6_3 :  in std_logic;
  36   r :  out std_logic;
  37   un6_dly_counter_0_x :  in std_logic;
  38   clk_pin_c :  in std_logic;
  39   b :  out std_logic);
  40 end vga_control;
  41
  42 architecture beh of vga_control is
  43   signal devclrn : std_logic := '1';
  44   signal devpor : std_logic := '1';
  45   signal devoe : std_logic := '0';
  46   signal B_NEXT_I_O3_0 : std_logic ;
  47   signal B_NEXT_I_A7_1 : std_logic ;
  48   signal N_6_I_0_G0_0 : std_logic ;
  49   signal N_4_I_0_G0_1 : std_logic ;
  50   signal R_NEXT_I_O7 : std_logic ;
  51   signal N_23_I_0_G0_A : std_logic ;
  52   signal G_NEXT_I_O3 : std_logic ;
  53   signal GND : std_logic ;
  54   signal VCC : std_logic ;
  55 begin
  56 B_Z26: stratix_lcell generic map (
  57     operation_mode => "normal",
  58     output_mode => "reg_only",
  59     synch_mode => "off",
  60      sum_lutc_input => "datac",
  61     lut_mask => "0700")
  62 port map (
  63 regout => b,
  64 clk => clk_pin_c,
  65 dataa => column_counter_sig_6,
  66 datab => B_NEXT_I_O3_0,
  67 datac => B_NEXT_I_A7_1,
  68 datad => N_6_I_0_G0_0,
  69 aclr => un6_dly_counter_0_x,
  70         devpor => devpor,
  71         devclrn => devclrn,
  72         sclr => GND,
  73         sload => GND,
  74         ena => VCC,
  75         cin => GND,
  76         inverta => GND,
  77         aload => GND);
  78 R_Z27: stratix_lcell generic map (
  79     operation_mode => "normal",
  80     output_mode => "reg_only",
  81     synch_mode => "off",
  82      sum_lutc_input => "datac",
  83     lut_mask => "1b00")
  84 port map (
  85 regout => r,
  86 clk => clk_pin_c,
  87 dataa => column_counter_sig_6,
  88 datab => un10_column_counter_siglt6_3,
  89 datac => B_NEXT_I_O3_0,
  90 datad => N_4_I_0_G0_1,
  91 aclr => un6_dly_counter_0_x,
  92         devpor => devpor,
  93         devclrn => devclrn,
  94         sclr => GND,
  95         sload => GND,
  96         ena => VCC,
  97         cin => GND,
  98         inverta => GND,
  99         aload => GND);
 100 G_Z28: stratix_lcell generic map (
 101     operation_mode => "normal",
 102     output_mode => "reg_only",
 103     synch_mode => "off",
 104      sum_lutc_input => "datac",
 105     lut_mask => "0400")
 106 port map (
 107 regout => g,
 108 clk => clk_pin_c,
 109 dataa => column_counter_sig_6,
 110 datab => column_counter_sig_5,
 111 datac => R_NEXT_I_O7,
 112 datad => N_23_I_0_G0_A,
 113 aclr => un6_dly_counter_0_x,
 114         devpor => devpor,
 115         devclrn => devclrn,
 116         sclr => GND,
 117         sload => GND,
 118         ena => VCC,
 119         cin => GND,
 120         inverta => GND,
 121         aload => GND);
 122 N_23_I_0_G0_A_Z29: stratix_lcell generic map (
 123     operation_mode => "normal",
 124     output_mode => "comb_only",
 125     synch_mode => "off",
 126      sum_lutc_input => "datac",
 127     lut_mask => "6c6e")
 128 port map (
 129 combout => N_23_I_0_G0_A,
 130 dataa => column_counter_sig_3,
 131 datab => column_counter_sig_4,
 132 datac => G_NEXT_I_O3,
 133 datad => un10_column_counter_siglt6_1,
 134         devpor => devpor,
 135         devclrn => devclrn,
 136         clk => GND,
 137         aclr => GND,
 138         sclr => GND,
 139         sload => GND,
 140         ena => VCC,
 141         cin => GND,
 142         inverta => GND,
 143         aload => GND);
 144 N_4_I_0_G0_1_Z30: stratix_lcell generic map (
 145     operation_mode => "normal",
 146     output_mode => "comb_only",
 147     synch_mode => "off",
 148      sum_lutc_input => "datac",
 149     lut_mask => "00ec")
 150 port map (
 151 combout => N_4_I_0_G0_1,
 152 dataa => column_counter_sig_5,
 153 datab => column_counter_sig_6,
 154 datac => G_NEXT_I_O3,
 155 datad => R_NEXT_I_O7,
 156         devpor => devpor,
 157         devclrn => devclrn,
 158         clk => GND,
 159         aclr => GND,
 160         sclr => GND,
 161         sload => GND,
 162         ena => VCC,
 163         cin => GND,
 164         inverta => GND,
 165         aload => GND);
 166 N_6_I_0_G0_0_Z31: stratix_lcell generic map (
 167     operation_mode => "normal",
 168     output_mode => "comb_only",
 169     synch_mode => "off",
 170      sum_lutc_input => "datac",
 171     lut_mask => "00ef")
 172 port map (
 173 combout => N_6_I_0_G0_0,
 174 dataa => column_counter_sig_5,
 175 datab => column_counter_sig_6,
 176 datac => un10_column_counter_siglt6_3,
 177 datad => R_NEXT_I_O7,
 178         devpor => devpor,
 179         devclrn => devclrn,
 180         clk => GND,
 181         aclr => GND,
 182         sclr => GND,
 183         sload => GND,
 184         ena => VCC,
 185         cin => GND,
 186         inverta => GND,
 187         aload => GND);
 188 B_NEXT_I_A7_1_Z32: stratix_lcell generic map (
 189     operation_mode => "normal",
 190     output_mode => "comb_only",
 191     synch_mode => "off",
 192      sum_lutc_input => "datac",
 193     lut_mask => "0001")
 194 port map (
 195 combout => B_NEXT_I_A7_1,
 196 dataa => column_counter_sig_5,
 197 datab => column_counter_sig_6,
 198 datac => column_counter_sig_0,
 199 datad => G_NEXT_I_O3,
 200         devpor => devpor,
 201         devclrn => devclrn,
 202         clk => GND,
 203         aclr => GND,
 204         sclr => GND,
 205         sload => GND,
 206         ena => VCC,
 207         cin => GND,
 208         inverta => GND,
 209         aload => GND);
 210 B_NEXT_I_O3_0_Z33: stratix_lcell generic map (
 211     operation_mode => "normal",
 212     output_mode => "comb_only",
 213     synch_mode => "off",
 214      sum_lutc_input => "datac",
 215     lut_mask => "ff80")
 216 port map (
 217 combout => B_NEXT_I_O3_0,
 218 dataa => column_counter_sig_3,
 219 datab => column_counter_sig_4,
 220 datac => column_counter_sig_2,
 221 datad => column_counter_sig_5,
 222         devpor => devpor,
 223         devclrn => devclrn,
 224         clk => GND,
 225         aclr => GND,
 226         sclr => GND,
 227         sload => GND,
 228         ena => VCC,
 229         cin => GND,
 230         inverta => GND,
 231         aload => GND);
 232 R_NEXT_I_O7_Z34: stratix_lcell generic map (
 233     operation_mode => "normal",
 234     output_mode => "comb_only",
 235     synch_mode => "off",
 236      sum_lutc_input => "datac",
 237     lut_mask => "bfbf")
 238 port map (
 239 combout => R_NEXT_I_O7,
 240 dataa => column_counter_sig_7,
 241 datab => v_enable_sig,
 242 datac => h_enable_sig,
 243         devpor => devpor,
 244         devclrn => devclrn,
 245         clk => GND,
 246         datad => VCC,
 247         aclr => GND,
 248         sclr => GND,
 249         sload => GND,
 250         ena => VCC,
 251         cin => GND,
 252         inverta => GND,
 253         aload => GND);
 254 G_NEXT_I_O3_Z35: stratix_lcell generic map (
 255     operation_mode => "normal",
 256     output_mode => "comb_only",
 257     synch_mode => "off",
 258      sum_lutc_input => "datac",
 259     lut_mask => "eeee")
 260 port map (
 261 combout => G_NEXT_I_O3,
 262 dataa => column_counter_sig_2,
 263 datab => column_counter_sig_1,
 264         devpor => devpor,
 265         devclrn => devclrn,
 266         clk => GND,
 267         datac => VCC,
 268         datad => VCC,
 269         aclr => GND,
 270         sclr => GND,
 271         sload => GND,
 272         ena => VCC,
 273         cin => GND,
 274         inverta => GND,
 275         aload => GND);
 276 GND <= '0';
 277 VCC <= '1';
 278 end beh;
 279
 280 --
 281 library ieee, stratix;
 282 use ieee.std_logic_1164.all;
 283 use ieee.numeric_std.all;
 284 library synplify;
 285 use synplify.components.all;
 286 use stratix.stratix_components.all;
 287
 288 entity vga_driver is
 289 port(
 290 line_counter_sig_0 :  out std_logic;
 291 line_counter_sig_1 :  out std_logic;
 292 line_counter_sig_2 :  out std_logic;
 293 line_counter_sig_3 :  out std_logic;
 294 line_counter_sig_4 :  out std_logic;
 295 line_counter_sig_5 :  out std_logic;
 296 line_counter_sig_6 :  out std_logic;
 297 line_counter_sig_7 :  out std_logic;
 298 line_counter_sig_8 :  out std_logic;
 299 dly_counter_1 :  in std_logic;
 300 dly_counter_0 :  in std_logic;
 301 vsync_state_2 :  out std_logic;
 302 vsync_state_5 :  out std_logic;
 303 vsync_state_3 :  out std_logic;
 304 vsync_state_6 :  out std_logic;
 305 vsync_state_4 :  out std_logic;
 306 vsync_state_1 :  out std_logic;
 307 vsync_state_0 :  out std_logic;
 308 hsync_state_2 :  out std_logic;
 309 hsync_state_4 :  out std_logic;
 310 hsync_state_0 :  out std_logic;
 311 hsync_state_5 :  out std_logic;
 312 hsync_state_1 :  out std_logic;
 313 hsync_state_3 :  out std_logic;
 314 hsync_state_6 :  out std_logic;
 315 column_counter_sig_0 :  out std_logic;
 316 column_counter_sig_1 :  out std_logic;
 317 column_counter_sig_2 :  out std_logic;
 318 column_counter_sig_3 :  out std_logic;
 319 column_counter_sig_4 :  out std_logic;
 320 column_counter_sig_5 :  out std_logic;
 321 column_counter_sig_6 :  out std_logic;
 322 column_counter_sig_7 :  out std_logic;
 323 column_counter_sig_8 :  out std_logic;
 324 column_counter_sig_9 :  out std_logic;
 325 vsync_counter_9 :  out std_logic;
 326 vsync_counter_8 :  out std_logic;
 327 vsync_counter_7 :  out std_logic;
 328 vsync_counter_6 :  out std_logic;
 329 vsync_counter_5 :  out std_logic;
 330 vsync_counter_4 :  out std_logic;
 331 vsync_counter_3 :  out std_logic;
 332 vsync_counter_2 :  out std_logic;
 333 vsync_counter_1 :  out std_logic;
 334 vsync_counter_0 :  out std_logic;
 335 hsync_counter_9 :  out std_logic;
 336 hsync_counter_8 :  out std_logic;
 337 hsync_counter_7 :  out std_logic;
 338 hsync_counter_6 :  out std_logic;
 339 hsync_counter_5 :  out std_logic;
 340 hsync_counter_4 :  out std_logic;
 341 hsync_counter_3 :  out std_logic;
 342 hsync_counter_2 :  out std_logic;
 343 hsync_counter_1 :  out std_logic;
 344 hsync_counter_0 :  out std_logic;
 345 d_set_vsync_counter :  out std_logic;
 346 un10_column_counter_siglt6_1 :  out std_logic;
 347 un10_column_counter_siglt6_3 :  out std_logic;
 348 v_sync :  out std_logic;
 349 h_sync :  out std_logic;
 350 h_enable_sig :  out std_logic;
 351 v_enable_sig :  out std_logic;
 352 reset_pin_c :  in std_logic;
 353 un6_dly_counter_0_x :  out std_logic;
 354 d_set_hsync_counter :  out std_logic;
 355 clk_pin_c :  in std_logic);
 356 end vga_driver;
 357
 358 architecture beh of vga_driver is
 359 signal devclrn : std_logic := '1';
 360 signal devpor : std_logic := '1';
 361 signal devoe : std_logic := '0';
 362 signal HSYNC_COUNTER_COUT : std_logic_vector(8 downto 0);
 363 signal VSYNC_COUNTER_COUT : std_logic_vector(8 downto 0);
 364 signal UN2_COLUMN_COUNTER_NEXT_COMBOUT : std_logic_vector(9 downto 1);
 365 signal UN1_LINE_COUNTER_SIG_COMBOUT : std_logic_vector(9 downto 1);
 366 signal UN1_LINE_COUNTER_SIG_COUT : std_logic_vector(7 downto 1);
 367 signal UN1_LINE_COUNTER_SIG_A_COUT : std_logic_vector(1 to 1);
 368 signal UN2_COLUMN_COUNTER_NEXT_COUT : std_logic_vector(7 downto 0);
 369 signal HSYNC_COUNTER_NEXT_1_SQMUXA : std_logic ;
 370 signal G_2_I : std_logic ;
 371 signal UN9_HSYNC_COUNTERLT9 : std_logic ;
 372 signal VSYNC_COUNTER_NEXT_1_SQMUXA : std_logic ;
 373 signal G_16_I : std_logic ;
 374 signal UN9_VSYNC_COUNTERLT9 : std_logic ;
 375 signal UN10_COLUMN_COUNTER_SIGLTO9 : std_logic ;
 376 signal COLUMN_COUNTER_NEXT_0_SQMUXA_1_1 : std_logic ;
 377 signal UN6_DLY_COUNTER_0_X_58 : std_logic ;
 378 signal \VSYNC_STATE_3_IV_0_0__G0_0_A3_0\ : std_logic ;
 379 signal VSYNC_STATE_NEXT_2_SQMUXA : std_logic ;
 380 signal UN12_VSYNC_COUNTER_7 : std_logic ;
 381 signal UN13_VSYNC_COUNTER_4 : std_logic ;
 382 signal UN10_LINE_COUNTER_SIGLTO8 : std_logic ;
 383 signal LINE_COUNTER_NEXT_0_SQMUXA_1_1 : std_logic ;
 384 signal V_ENABLE_SIG_1_0_0_0_G0_I_O4 : std_logic ;
 385 signal H_ENABLE_SIG_1_0_0_0_G0_I_O4 : std_logic ;
 386 signal H_SYNC_1_0_0_0_G1 : std_logic ;
 387 signal V_SYNC_1_0_0_0_G1 : std_logic ;
 388 signal UN14_VSYNC_COUNTER_8 : std_logic ;
 389 signal \HSYNC_STATE_3_0_0_0__G0_0\ : std_logic ;
 390 signal UN10_HSYNC_COUNTER_3 : std_logic ;
 391 signal UN10_HSYNC_COUNTER_1 : std_logic ;
 392 signal UN10_HSYNC_COUNTER_4 : std_logic ;
 393 signal UN12_HSYNC_COUNTER : std_logic ;
 394 signal UN11_HSYNC_COUNTER_2 : std_logic ;
 395 signal UN11_HSYNC_COUNTER_3 : std_logic ;
 396 signal UN13_HSYNC_COUNTER : std_logic ;
 397 signal VSYNC_STATE_NEXT_1_SQMUXA_1 : std_logic ;
 398 signal VSYNC_STATE_NEXT_1_SQMUXA_3 : std_logic ;
 399 signal UN1_VSYNC_STATE_NEXT_1_SQMUXA_0 : std_logic ;
 400 signal HSYNC_STATE_NEXT_1_SQMUXA_1 : std_logic ;
 401 signal HSYNC_STATE_NEXT_1_SQMUXA_2 : std_logic ;
 402 signal UN1_HSYNC_STATE_NEXT_1_SQMUXA_0 : std_logic ;
 403 signal UN12_VSYNC_COUNTER_6 : std_logic ;
 404 signal UN15_VSYNC_COUNTER_4 : std_logic ;
 405 signal VSYNC_STATE_NEXT_1_SQMUXA_2 : std_logic ;
 406 signal UN10_COLUMN_COUNTER_SIGLT6 : std_logic ;
 407 signal UN10_LINE_COUNTER_SIGLTO5 : std_logic ;
 408 signal UN9_VSYNC_COUNTERLT9_5 : std_logic ;
 409 signal UN9_VSYNC_COUNTERLT9_6 : std_logic ;
 410 signal UN12_HSYNC_COUNTER_3 : std_logic ;
 411 signal UN12_HSYNC_COUNTER_4 : std_logic ;
 412 signal UN13_HSYNC_COUNTER_2 : std_logic ;
 413 signal UN13_HSYNC_COUNTER_7 : std_logic ;
 414 signal UN9_HSYNC_COUNTERLT9_3 : std_logic ;
 415 signal UN10_LINE_COUNTER_SIGLT4_2 : std_logic ;
 416 signal UN13_VSYNC_COUNTER_3 : std_logic ;
 417 signal UN15_VSYNC_COUNTER_3 : std_logic ;
 418 signal V_SYNC_56 : std_logic ;
 419 signal UN1_VSYNC_STATE_2_0 : std_logic ;
 420 signal D_SET_HSYNC_COUNTER_59 : std_logic ;
 421 signal H_SYNC_57 : std_logic ;
 422 signal UN1_HSYNC_STATE_3_0 : std_logic ;
 423 signal UN10_COLUMN_COUNTER_SIGLT6_54 : std_logic ;
 424 signal D_SET_VSYNC_COUNTER_53 : std_logic ;
 425 signal UN10_COLUMN_COUNTER_SIGLT6_55 : std_logic ;
 426 signal VCC : std_logic ;
 427 signal LINE_COUNTER_SIG_0_0 : std_logic ;
 428 signal LINE_COUNTER_SIG_1_0 : std_logic ;
 429 signal LINE_COUNTER_SIG_2_0 : std_logic ;
 430 signal LINE_COUNTER_SIG_3_0 : std_logic ;
 431 signal LINE_COUNTER_SIG_4_0 : std_logic ;
 432 signal LINE_COUNTER_SIG_5_0 : std_logic ;
 433 signal LINE_COUNTER_SIG_6_0 : std_logic ;
 434 signal LINE_COUNTER_SIG_7_0 : std_logic ;
 435 signal LINE_COUNTER_SIG_8_0 : std_logic ;
 436 signal VSYNC_STATE_9 : std_logic ;
 437 signal VSYNC_STATE_10 : std_logic ;
 438 signal VSYNC_STATE_11 : std_logic ;
 439 signal VSYNC_STATE_12 : std_logic ;
 440 signal VSYNC_STATE_13 : std_logic ;
 441 signal VSYNC_STATE_14 : std_logic ;
 442 signal VSYNC_STATE_15 : std_logic ;
 443 signal HSYNC_STATE_16 : std_logic ;
 444 signal HSYNC_STATE_17 : std_logic ;
 445 signal HSYNC_STATE_18 : std_logic ;
 446 signal HSYNC_STATE_19 : std_logic ;
 447 signal HSYNC_STATE_20 : std_logic ;
 448 signal HSYNC_STATE_21 : std_logic ;
 449 signal HSYNC_STATE_22 : std_logic ;
 450 signal COLUMN_COUNTER_SIG_23 : std_logic ;
 451 signal COLUMN_COUNTER_SIG_24 : std_logic ;
 452 signal COLUMN_COUNTER_SIG_25 : std_logic ;
 453 signal COLUMN_COUNTER_SIG_26 : std_logic ;
 454 signal COLUMN_COUNTER_SIG_27 : std_logic ;
 455 signal COLUMN_COUNTER_SIG_28 : std_logic ;
 456 signal COLUMN_COUNTER_SIG_29 : std_logic ;
 457 signal COLUMN_COUNTER_SIG_30 : std_logic ;
 458 signal COLUMN_COUNTER_SIG_31 : std_logic ;
 459 signal COLUMN_COUNTER_SIG_32 : std_logic ;
 460 signal VSYNC_COUNTER_33 : std_logic ;
 461 signal VSYNC_COUNTER_34 : std_logic ;
 462 signal VSYNC_COUNTER_35 : std_logic ;
 463 signal VSYNC_COUNTER_36 : std_logic ;
 464 signal VSYNC_COUNTER_37 : std_logic ;
 465 signal VSYNC_COUNTER_38 : std_logic ;
 466 signal VSYNC_COUNTER_39 : std_logic ;
 467 signal VSYNC_COUNTER_40 : std_logic ;
 468 signal VSYNC_COUNTER_41 : std_logic ;
 469 signal VSYNC_COUNTER_42 : std_logic ;
 470 signal HSYNC_COUNTER_43 : std_logic ;
 471 signal HSYNC_COUNTER_44 : std_logic ;
 472 signal HSYNC_COUNTER_45 : std_logic ;
 473 signal HSYNC_COUNTER_46 : std_logic ;
 474 signal HSYNC_COUNTER_47 : std_logic ;
 475 signal HSYNC_COUNTER_48 : std_logic ;
 476 signal HSYNC_COUNTER_49 : std_logic ;
 477 signal HSYNC_COUNTER_50 : std_logic ;
 478 signal HSYNC_COUNTER_51 : std_logic ;
 479 signal HSYNC_COUNTER_52 : std_logic ;
 480 signal GND : std_logic ;
 481 signal LINE_COUNTER_NEXT_0_SQMUXA_1_1_I : std_logic ;
 482 signal COLUMN_COUNTER_NEXT_0_SQMUXA_1_1_I : std_logic ;
 483 signal G_16_I_I : std_logic ;
 484 signal UN9_VSYNC_COUNTERLT9_I : std_logic ;
 485 signal G_2_I_I : std_logic ;
 486 signal UN9_HSYNC_COUNTERLT9_I : std_logic ;
 487 begin
 488 \HSYNC_COUNTER_0_\: stratix_lcell generic map (
 489     operation_mode => "arithmetic",
 490     output_mode => "reg_and_comb",
 491     synch_mode => "on",
 492      sum_lutc_input => "datac",
 493     lut_mask => "55aa")
 494 port map (
 495 regout => HSYNC_COUNTER_52,
 496 cout => HSYNC_COUNTER_COUT(0),
 497 clk => clk_pin_c,
 498 dataa => HSYNC_COUNTER_52,
 499 datab => VCC,
 500 datac => HSYNC_COUNTER_NEXT_1_SQMUXA,
 501 sclr => G_2_I_I,
 502 sload => UN9_HSYNC_COUNTERLT9_I,
 503         devpor => devpor,
 504         devclrn => devclrn,
 505         datad => VCC,
 506         aclr => GND,
 507         ena => VCC,
 508         cin => GND,
 509         inverta => GND,
 510         aload => GND);
 511 \HSYNC_COUNTER_1_\: stratix_lcell generic map (
 512     operation_mode => "arithmetic",
 513     output_mode => "reg_and_comb",
 514     synch_mode => "on",
 515      sum_lutc_input => "cin",
 516      cin_used => "true",
 517     lut_mask => "5aa0")
 518 port map (
 519 regout => HSYNC_COUNTER_51,
 520 cout => HSYNC_COUNTER_COUT(1),
 521 clk => clk_pin_c,
 522 dataa => HSYNC_COUNTER_51,
 523 datac => HSYNC_COUNTER_NEXT_1_SQMUXA,
 524 sclr => G_2_I_I,
 525 sload => UN9_HSYNC_COUNTERLT9_I,
 526 cin => HSYNC_COUNTER_COUT(0),
 527         devpor => devpor,
 528         devclrn => devclrn,
 529         datab => VCC,
 530         datad => VCC,
 531         aclr => GND,
 532         ena => VCC,
 533         inverta => GND,
 534         aload => GND);
 535 \HSYNC_COUNTER_2_\: stratix_lcell generic map (
 536     operation_mode => "arithmetic",
 537     output_mode => "reg_and_comb",
 538     synch_mode => "on",
 539      sum_lutc_input => "cin",
 540      cin_used => "true",
 541     lut_mask => "5aa0")
 542 port map (
 543 regout => HSYNC_COUNTER_50,
 544 cout => HSYNC_COUNTER_COUT(2),
 545 clk => clk_pin_c,
 546 dataa => HSYNC_COUNTER_50,
 547 datac => HSYNC_COUNTER_NEXT_1_SQMUXA,
 548 sclr => G_2_I_I,
 549 sload => UN9_HSYNC_COUNTERLT9_I,
 550 cin => HSYNC_COUNTER_COUT(1),
 551         devpor => devpor,
 552         devclrn => devclrn,
 553         datab => VCC,
 554         datad => VCC,
 555         aclr => GND,
 556         ena => VCC,
 557         inverta => GND,
 558         aload => GND);
 559 \HSYNC_COUNTER_3_\: stratix_lcell generic map (
 560     operation_mode => "arithmetic",
 561     output_mode => "reg_and_comb",
 562     synch_mode => "on",
 563      sum_lutc_input => "cin",
 564      cin_used => "true",
 565     lut_mask => "5aa0")
 566 port map (
 567 regout => HSYNC_COUNTER_49,
 568 cout => HSYNC_COUNTER_COUT(3),
 569 clk => clk_pin_c,
 570 dataa => HSYNC_COUNTER_49,
 571 datac => HSYNC_COUNTER_NEXT_1_SQMUXA,
 572 sclr => G_2_I_I,
 573 sload => UN9_HSYNC_COUNTERLT9_I,
 574 cin => HSYNC_COUNTER_COUT(2),
 575         devpor => devpor,
 576         devclrn => devclrn,
 577         datab => VCC,
 578         datad => VCC,
 579         aclr => GND,
 580         ena => VCC,
 581         inverta => GND,
 582         aload => GND);
 583 \HSYNC_COUNTER_4_\: stratix_lcell generic map (
 584     operation_mode => "arithmetic",
 585     output_mode => "reg_and_comb",
 586     synch_mode => "on",
 587      sum_lutc_input => "cin",
 588      cin_used => "true",
 589     lut_mask => "5aa0")
 590 port map (
 591 regout => HSYNC_COUNTER_48,
 592 cout => HSYNC_COUNTER_COUT(4),
 593 clk => clk_pin_c,
 594 dataa => HSYNC_COUNTER_48,
 595 datac => HSYNC_COUNTER_NEXT_1_SQMUXA,
 596 sclr => G_2_I_I,
 597 sload => UN9_HSYNC_COUNTERLT9_I,
 598 cin => HSYNC_COUNTER_COUT(3),
 599         devpor => devpor,
 600         devclrn => devclrn,
 601         datab => VCC,
 602         datad => VCC,
 603         aclr => GND,
 604         ena => VCC,
 605         inverta => GND,
 606         aload => GND);
 607 \HSYNC_COUNTER_5_\: stratix_lcell generic map (
 608     operation_mode => "arithmetic",
 609     output_mode => "reg_and_comb",
 610     synch_mode => "on",
 611      sum_lutc_input => "cin",
 612      cin_used => "true",
 613     lut_mask => "5aa0")
 614 port map (
 615 regout => HSYNC_COUNTER_47,
 616 cout => HSYNC_COUNTER_COUT(5),
 617 clk => clk_pin_c,
 618 dataa => HSYNC_COUNTER_47,
 619 datac => HSYNC_COUNTER_NEXT_1_SQMUXA,
 620 sclr => G_2_I_I,
 621 sload => UN9_HSYNC_COUNTERLT9_I,
 622 cin => HSYNC_COUNTER_COUT(4),
 623         devpor => devpor,
 624         devclrn => devclrn,
 625         datab => VCC,
 626         datad => VCC,
 627         aclr => GND,
 628         ena => VCC,
 629         inverta => GND,
 630         aload => GND);
 631 \HSYNC_COUNTER_6_\: stratix_lcell generic map (
 632     operation_mode => "arithmetic",
 633     output_mode => "reg_and_comb",
 634     synch_mode => "on",
 635      sum_lutc_input => "cin",
 636      cin_used => "true",
 637     lut_mask => "5aa0")
 638 port map (
 639 regout => HSYNC_COUNTER_46,
 640 cout => HSYNC_COUNTER_COUT(6),
 641 clk => clk_pin_c,
 642 dataa => HSYNC_COUNTER_46,
 643 datac => HSYNC_COUNTER_NEXT_1_SQMUXA,
 644 sclr => G_2_I_I,
 645 sload => UN9_HSYNC_COUNTERLT9_I,
 646 cin => HSYNC_COUNTER_COUT(5),
 647         devpor => devpor,
 648         devclrn => devclrn,
 649         datab => VCC,
 650         datad => VCC,
 651         aclr => GND,
 652         ena => VCC,
 653         inverta => GND,
 654         aload => GND);
 655 \HSYNC_COUNTER_7_\: stratix_lcell generic map (
 656     operation_mode => "arithmetic",
 657     output_mode => "reg_and_comb",
 658     synch_mode => "on",
 659      sum_lutc_input => "cin",
 660      cin_used => "true",
 661     lut_mask => "5aa0")
 662 port map (
 663 regout => HSYNC_COUNTER_45,
 664 cout => HSYNC_COUNTER_COUT(7),
 665 clk => clk_pin_c,
 666 dataa => HSYNC_COUNTER_45,
 667 datac => HSYNC_COUNTER_NEXT_1_SQMUXA,
 668 sclr => G_2_I_I,
 669 sload => UN9_HSYNC_COUNTERLT9_I,
 670 cin => HSYNC_COUNTER_COUT(6),
 671         devpor => devpor,
 672         devclrn => devclrn,
 673         datab => VCC,
 674         datad => VCC,
 675         aclr => GND,
 676         ena => VCC,
 677         inverta => GND,
 678         aload => GND);
 679 \HSYNC_COUNTER_8_\: stratix_lcell generic map (
 680     operation_mode => "arithmetic",
 681     output_mode => "reg_and_comb",
 682     synch_mode => "on",
 683      sum_lutc_input => "cin",
 684      cin_used => "true",
 685     lut_mask => "5aa0")
 686 port map (
 687 regout => HSYNC_COUNTER_44,
 688 cout => HSYNC_COUNTER_COUT(8),
 689 clk => clk_pin_c,
 690 dataa => HSYNC_COUNTER_44,
 691 datac => HSYNC_COUNTER_NEXT_1_SQMUXA,
 692 sclr => G_2_I_I,
 693 sload => UN9_HSYNC_COUNTERLT9_I,
 694 cin => HSYNC_COUNTER_COUT(7),
 695         devpor => devpor,
 696         devclrn => devclrn,
 697         datab => VCC,
 698         datad => VCC,
 699         aclr => GND,
 700         ena => VCC,
 701         inverta => GND,
 702         aload => GND);
 703 \HSYNC_COUNTER_9_\: stratix_lcell generic map (
 704     operation_mode => "normal",
 705     output_mode => "reg_only",
 706     synch_mode => "on",
 707      sum_lutc_input => "cin",
 708      cin_used => "true",
 709     lut_mask => "5a5a")
 710 port map (
 711 regout => HSYNC_COUNTER_43,
 712 clk => clk_pin_c,
 713 dataa => HSYNC_COUNTER_43,
 714 datac => HSYNC_COUNTER_NEXT_1_SQMUXA,
 715 sclr => G_2_I_I,
 716 sload => UN9_HSYNC_COUNTERLT9_I,
 717 cin => HSYNC_COUNTER_COUT(8),
 718         devpor => devpor,
 719         devclrn => devclrn,
 720         datab => VCC,
 721         datad => VCC,
 722         aclr => GND,
 723         ena => VCC,
 724         inverta => GND,
 725         aload => GND);
 726 \VSYNC_COUNTER_0_\: stratix_lcell generic map (
 727     operation_mode => "arithmetic",
 728     output_mode => "reg_and_comb",
 729     synch_mode => "on",
 730      sum_lutc_input => "datac",
 731     lut_mask => "6688")
 732 port map (
 733 regout => VSYNC_COUNTER_42,
 734 cout => VSYNC_COUNTER_COUT(0),
 735 clk => clk_pin_c,
 736 dataa => VSYNC_COUNTER_42,
 737 datab => D_SET_HSYNC_COUNTER_59,
 738 datac => VSYNC_COUNTER_NEXT_1_SQMUXA,
 739 sclr => G_16_I_I,
 740 sload => UN9_VSYNC_COUNTERLT9_I,
 741         devpor => devpor,
 742         devclrn => devclrn,
 743         datad => VCC,
 744         aclr => GND,
 745         ena => VCC,
 746         cin => GND,
 747         inverta => GND,
 748         aload => GND);
 749 \VSYNC_COUNTER_1_\: stratix_lcell generic map (
 750     operation_mode => "arithmetic",
 751     output_mode => "reg_and_comb",
 752     synch_mode => "on",
 753      sum_lutc_input => "cin",
 754      cin_used => "true",
 755     lut_mask => "5aa0")
 756 port map (
 757 regout => VSYNC_COUNTER_41,
 758 cout => VSYNC_COUNTER_COUT(1),
 759 clk => clk_pin_c,
 760 dataa => VSYNC_COUNTER_41,
 761 datac => VSYNC_COUNTER_NEXT_1_SQMUXA,
 762 sclr => G_16_I_I,
 763 sload => UN9_VSYNC_COUNTERLT9_I,
 764 cin => VSYNC_COUNTER_COUT(0),
 765         devpor => devpor,
 766         devclrn => devclrn,
 767         datab => VCC,
 768         datad => VCC,
 769         aclr => GND,
 770         ena => VCC,
 771         inverta => GND,
 772         aload => GND);
 773 \VSYNC_COUNTER_2_\: stratix_lcell generic map (
 774     operation_mode => "arithmetic",
 775     output_mode => "reg_and_comb",
 776     synch_mode => "on",
 777      sum_lutc_input => "cin",
 778      cin_used => "true",
 779     lut_mask => "5aa0")
 780 port map (
 781 regout => VSYNC_COUNTER_40,
 782 cout => VSYNC_COUNTER_COUT(2),
 783 clk => clk_pin_c,
 784 dataa => VSYNC_COUNTER_40,
 785 datac => VSYNC_COUNTER_NEXT_1_SQMUXA,
 786 sclr => G_16_I_I,
 787 sload => UN9_VSYNC_COUNTERLT9_I,
 788 cin => VSYNC_COUNTER_COUT(1),
 789         devpor => devpor,
 790         devclrn => devclrn,
 791         datab => VCC,
 792         datad => VCC,
 793         aclr => GND,
 794         ena => VCC,
 795         inverta => GND,
 796         aload => GND);
 797 \VSYNC_COUNTER_3_\: stratix_lcell generic map (
 798     operation_mode => "arithmetic",
 799     output_mode => "reg_and_comb",
 800     synch_mode => "on",
 801      sum_lutc_input => "cin",
 802      cin_used => "true",
 803     lut_mask => "5aa0")
 804 port map (
 805 regout => VSYNC_COUNTER_39,
 806 cout => VSYNC_COUNTER_COUT(3),
 807 clk => clk_pin_c,
 808 dataa => VSYNC_COUNTER_39,
 809 datac => VSYNC_COUNTER_NEXT_1_SQMUXA,
 810 sclr => G_16_I_I,
 811 sload => UN9_VSYNC_COUNTERLT9_I,
 812 cin => VSYNC_COUNTER_COUT(2),
 813         devpor => devpor,
 814         devclrn => devclrn,
 815         datab => VCC,
 816         datad => VCC,
 817         aclr => GND,
 818         ena => VCC,
 819         inverta => GND,
 820         aload => GND);
 821 \VSYNC_COUNTER_4_\: stratix_lcell generic map (
 822     operation_mode => "arithmetic",
 823     output_mode => "reg_and_comb",
 824     synch_mode => "on",
 825      sum_lutc_input => "cin",
 826      cin_used => "true",
 827     lut_mask => "5aa0")
 828 port map (
 829 regout => VSYNC_COUNTER_38,
 830 cout => VSYNC_COUNTER_COUT(4),
 831 clk => clk_pin_c,
 832 dataa => VSYNC_COUNTER_38,
 833 datac => VSYNC_COUNTER_NEXT_1_SQMUXA,
 834 sclr => G_16_I_I,
 835 sload => UN9_VSYNC_COUNTERLT9_I,
 836 cin => VSYNC_COUNTER_COUT(3),
 837         devpor => devpor,
 838         devclrn => devclrn,
 839         datab => VCC,
 840         datad => VCC,
 841         aclr => GND,
 842         ena => VCC,
 843         inverta => GND,
 844         aload => GND);
 845 \VSYNC_COUNTER_5_\: stratix_lcell generic map (
 846     operation_mode => "arithmetic",
 847     output_mode => "reg_and_comb",
 848     synch_mode => "on",
 849      sum_lutc_input => "cin",
 850      cin_used => "true",
 851     lut_mask => "5aa0")
 852 port map (
 853 regout => VSYNC_COUNTER_37,
 854 cout => VSYNC_COUNTER_COUT(5),
 855 clk => clk_pin_c,
 856 dataa => VSYNC_COUNTER_37,
 857 datac => VSYNC_COUNTER_NEXT_1_SQMUXA,
 858 sclr => G_16_I_I,
 859 sload => UN9_VSYNC_COUNTERLT9_I,
 860 cin => VSYNC_COUNTER_COUT(4),
 861         devpor => devpor,
 862         devclrn => devclrn,
 863         datab => VCC,
 864         datad => VCC,
 865         aclr => GND,
 866         ena => VCC,
 867         inverta => GND,
 868         aload => GND);
 869 \VSYNC_COUNTER_6_\: stratix_lcell generic map (
 870     operation_mode => "arithmetic",
 871     output_mode => "reg_and_comb",
 872     synch_mode => "on",
 873      sum_lutc_input => "cin",
 874      cin_used => "true",
 875     lut_mask => "5aa0")
 876 port map (
 877 regout => VSYNC_COUNTER_36,
 878 cout => VSYNC_COUNTER_COUT(6),
 879 clk => clk_pin_c,
 880 dataa => VSYNC_COUNTER_36,
 881 datac => VSYNC_COUNTER_NEXT_1_SQMUXA,
 882 sclr => G_16_I_I,
 883 sload => UN9_VSYNC_COUNTERLT9_I,
 884 cin => VSYNC_COUNTER_COUT(5),
 885         devpor => devpor,
 886         devclrn => devclrn,
 887         datab => VCC,
 888         datad => VCC,
 889         aclr => GND,
 890         ena => VCC,
 891         inverta => GND,
 892         aload => GND);
 893 \VSYNC_COUNTER_7_\: stratix_lcell generic map (
 894     operation_mode => "arithmetic",
 895     output_mode => "reg_and_comb",
 896     synch_mode => "on",
 897      sum_lutc_input => "cin",
 898      cin_used => "true",
 899     lut_mask => "5aa0")
 900 port map (
 901 regout => VSYNC_COUNTER_35,
 902 cout => VSYNC_COUNTER_COUT(7),
 903 clk => clk_pin_c,
 904 dataa => VSYNC_COUNTER_35,
 905 datac => VSYNC_COUNTER_NEXT_1_SQMUXA,
 906 sclr => G_16_I_I,
 907 sload => UN9_VSYNC_COUNTERLT9_I,
 908 cin => VSYNC_COUNTER_COUT(6),
 909         devpor => devpor,
 910         devclrn => devclrn,
 911         datab => VCC,
 912         datad => VCC,
 913         aclr => GND,
 914         ena => VCC,
 915         inverta => GND,
 916         aload => GND);
 917 \VSYNC_COUNTER_8_\: stratix_lcell generic map (
 918     operation_mode => "arithmetic",
 919     output_mode => "reg_and_comb",
 920     synch_mode => "on",
 921      sum_lutc_input => "cin",
 922      cin_used => "true",
 923     lut_mask => "5aa0")
 924 port map (
 925 regout => VSYNC_COUNTER_34,
 926 cout => VSYNC_COUNTER_COUT(8),
 927 clk => clk_pin_c,
 928 dataa => VSYNC_COUNTER_34,
 929 datac => VSYNC_COUNTER_NEXT_1_SQMUXA,
 930 sclr => G_16_I_I,
 931 sload => UN9_VSYNC_COUNTERLT9_I,
 932 cin => VSYNC_COUNTER_COUT(7),
 933         devpor => devpor,
 934         devclrn => devclrn,
 935         datab => VCC,
 936         datad => VCC,
 937         aclr => GND,
 938         ena => VCC,
 939         inverta => GND,
 940         aload => GND);
 941 \VSYNC_COUNTER_9_\: stratix_lcell generic map (
 942     operation_mode => "normal",
 943     output_mode => "reg_only",
 944     synch_mode => "on",
 945      sum_lutc_input => "cin",
 946      cin_used => "true",
 947     lut_mask => "5a5a")
 948 port map (
 949 regout => VSYNC_COUNTER_33,
 950 clk => clk_pin_c,
 951 dataa => VSYNC_COUNTER_33,
 952 datac => VSYNC_COUNTER_NEXT_1_SQMUXA,
 953 sclr => G_16_I_I,
 954 sload => UN9_VSYNC_COUNTERLT9_I,
 955 cin => VSYNC_COUNTER_COUT(8),
 956         devpor => devpor,
 957         devclrn => devclrn,
 958         datab => VCC,
 959         datad => VCC,
 960         aclr => GND,
 961         ena => VCC,
 962         inverta => GND,
 963         aload => GND);
 964 \COLUMN_COUNTER_SIG_9_\: stratix_lcell generic map (
 965     operation_mode => "normal",
 966     output_mode => "reg_only",
 967     synch_mode => "on",
 968      sum_lutc_input => "datac",
 969     lut_mask => "bbbb")
 970 port map (
 971 regout => COLUMN_COUNTER_SIG_32,
 972 clk => clk_pin_c,
 973 dataa => UN2_COLUMN_COUNTER_NEXT_COMBOUT(9),
 974 datab => UN10_COLUMN_COUNTER_SIGLTO9,
 975 sclr => COLUMN_COUNTER_NEXT_0_SQMUXA_1_1_I,
 976         devpor => devpor,
 977         devclrn => devclrn,
 978         datac => VCC,
 979         datad => VCC,
 980         aclr => GND,
 981         sload => GND,
 982         ena => VCC,
 983         cin => GND,
 984         inverta => GND,
 985         aload => GND);
 986 \COLUMN_COUNTER_SIG_8_\: stratix_lcell generic map (
 987     operation_mode => "normal",
 988     output_mode => "reg_only",
 989     synch_mode => "off",
 990      sum_lutc_input => "datac",
 991     lut_mask => "8080")
 992 port map (
 993 regout => COLUMN_COUNTER_SIG_31,
 994 clk => clk_pin_c,
 995 dataa => UN2_COLUMN_COUNTER_NEXT_COMBOUT(8),
 996 datab => COLUMN_COUNTER_NEXT_0_SQMUXA_1_1,
 997 datac => UN10_COLUMN_COUNTER_SIGLTO9,
 998         devpor => devpor,
 999         devclrn => devclrn,
1000         datad => VCC,
1001         aclr => GND,
1002         sclr => GND,
1003         sload => GND,
1004         ena => VCC,
1005         cin => GND,
1006         inverta => GND,
1007         aload => GND);
1008 \COLUMN_COUNTER_SIG_7_\: stratix_lcell generic map (
1009     operation_mode => "normal",
1010     output_mode => "reg_only",
1011     synch_mode => "off",
1012      sum_lutc_input => "datac",
1013     lut_mask => "8080")
1014 port map (
1015 regout => COLUMN_COUNTER_SIG_30,
1016 clk => clk_pin_c,
1017 dataa => UN2_COLUMN_COUNTER_NEXT_COMBOUT(7),
1018 datab => COLUMN_COUNTER_NEXT_0_SQMUXA_1_1,
1019 datac => UN10_COLUMN_COUNTER_SIGLTO9,
1020         devpor => devpor,
1021         devclrn => devclrn,
1022         datad => VCC,
1023         aclr => GND,
1024         sclr => GND,
1025         sload => GND,
1026         ena => VCC,
1027         cin => GND,
1028         inverta => GND,
1029         aload => GND);
1030 \COLUMN_COUNTER_SIG_6_\: stratix_lcell generic map (
1031     operation_mode => "normal",
1032     output_mode => "reg_only",
1033     synch_mode => "on",
1034      sum_lutc_input => "datac",
1035     lut_mask => "bbbb")
1036 port map (
1037 regout => COLUMN_COUNTER_SIG_29,
1038 clk => clk_pin_c,
1039 dataa => UN2_COLUMN_COUNTER_NEXT_COMBOUT(6),
1040 datab => UN10_COLUMN_COUNTER_SIGLTO9,
1041 sclr => COLUMN_COUNTER_NEXT_0_SQMUXA_1_1_I,
1042         devpor => devpor,
1043         devclrn => devclrn,
1044         datac => VCC,
1045         datad => VCC,
1046         aclr => GND,
1047         sload => GND,
1048         ena => VCC,
1049         cin => GND,
1050         inverta => GND,
1051         aload => GND);
1052 \COLUMN_COUNTER_SIG_5_\: stratix_lcell generic map (
1053     operation_mode => "normal",
1054     output_mode => "reg_only",
1055     synch_mode => "on",
1056      sum_lutc_input => "datac",
1057     lut_mask => "bbbb")
1058 port map (
1059 regout => COLUMN_COUNTER_SIG_28,
1060 clk => clk_pin_c,
1061 dataa => UN2_COLUMN_COUNTER_NEXT_COMBOUT(5),
1062 datab => UN10_COLUMN_COUNTER_SIGLTO9,
1063 sclr => COLUMN_COUNTER_NEXT_0_SQMUXA_1_1_I,
1064         devpor => devpor,
1065         devclrn => devclrn,
1066         datac => VCC,
1067         datad => VCC,
1068         aclr => GND,
1069         sload => GND,
1070         ena => VCC,
1071         cin => GND,
1072         inverta => GND,
1073         aload => GND);
1074 \COLUMN_COUNTER_SIG_4_\: stratix_lcell generic map (
1075     operation_mode => "normal",
1076     output_mode => "reg_only",
1077     synch_mode => "on",
1078      sum_lutc_input => "datac",
1079     lut_mask => "bbbb")
1080 port map (
1081 regout => COLUMN_COUNTER_SIG_27,
1082 clk => clk_pin_c,
1083 dataa => UN2_COLUMN_COUNTER_NEXT_COMBOUT(4),
1084 datab => UN10_COLUMN_COUNTER_SIGLTO9,
1085 sclr => COLUMN_COUNTER_NEXT_0_SQMUXA_1_1_I,
1086         devpor => devpor,
1087         devclrn => devclrn,
1088         datac => VCC,
1089         datad => VCC,
1090         aclr => GND,
1091         sload => GND,
1092         ena => VCC,
1093         cin => GND,
1094         inverta => GND,
1095         aload => GND);
1096 \COLUMN_COUNTER_SIG_3_\: stratix_lcell generic map (
1097     operation_mode => "normal",
1098     output_mode => "reg_only",
1099     synch_mode => "on",
1100      sum_lutc_input => "datac",
1101     lut_mask => "bbbb")
1102 port map (
1103 regout => COLUMN_COUNTER_SIG_26,
1104 clk => clk_pin_c,
1105 dataa => UN2_COLUMN_COUNTER_NEXT_COMBOUT(3),
1106 datab => UN10_COLUMN_COUNTER_SIGLTO9,
1107 sclr => COLUMN_COUNTER_NEXT_0_SQMUXA_1_1_I,
1108         devpor => devpor,
1109         devclrn => devclrn,
1110         datac => VCC,
1111         datad => VCC,
1112         aclr => GND,
1113         sload => GND,
1114         ena => VCC,
1115         cin => GND,
1116         inverta => GND,
1117         aload => GND);
1118 \COLUMN_COUNTER_SIG_2_\: stratix_lcell generic map (
1119     operation_mode => "normal",
1120     output_mode => "reg_only",
1121     synch_mode => "on",
1122      sum_lutc_input => "datac",
1123     lut_mask => "bbbb")
1124 port map (
1125 regout => COLUMN_COUNTER_SIG_25,
1126 clk => clk_pin_c,
1127 dataa => UN2_COLUMN_COUNTER_NEXT_COMBOUT(2),
1128 datab => UN10_COLUMN_COUNTER_SIGLTO9,
1129 sclr => COLUMN_COUNTER_NEXT_0_SQMUXA_1_1_I,
1130         devpor => devpor,
1131         devclrn => devclrn,
1132         datac => VCC,
1133         datad => VCC,
1134         aclr => GND,
1135         sload => GND,
1136         ena => VCC,
1137         cin => GND,
1138         inverta => GND,
1139         aload => GND);
1140 \COLUMN_COUNTER_SIG_1_\: stratix_lcell generic map (
1141     operation_mode => "normal",
1142     output_mode => "reg_only",
1143     synch_mode => "on",
1144      sum_lutc_input => "datac",
1145     lut_mask => "bbbb")
1146 port map (
1147 regout => COLUMN_COUNTER_SIG_24,
1148 clk => clk_pin_c,
1149 dataa => UN2_COLUMN_COUNTER_NEXT_COMBOUT(1),
1150 datab => UN10_COLUMN_COUNTER_SIGLTO9,
1151 sclr => COLUMN_COUNTER_NEXT_0_SQMUXA_1_1_I,
1152         devpor => devpor,
1153         devclrn => devclrn,
1154         datac => VCC,
1155         datad => VCC,
1156         aclr => GND,
1157         sload => GND,
1158         ena => VCC,
1159         cin => GND,
1160         inverta => GND,
1161         aload => GND);
1162 \COLUMN_COUNTER_SIG_0_\: stratix_lcell generic map (
1163     operation_mode => "normal",
1164     output_mode => "reg_only",
1165     synch_mode => "on",
1166      sum_lutc_input => "datac",
1167     lut_mask => "7777")
1168 port map (
1169 regout => COLUMN_COUNTER_SIG_23,
1170 clk => clk_pin_c,
1171 dataa => COLUMN_COUNTER_SIG_23,
1172 datab => UN10_COLUMN_COUNTER_SIGLTO9,
1173 sclr => COLUMN_COUNTER_NEXT_0_SQMUXA_1_1_I,
1174         devpor => devpor,
1175         devclrn => devclrn,
1176         datac => VCC,
1177         datad => VCC,
1178         aclr => GND,
1179         sload => GND,
1180         ena => VCC,
1181         cin => GND,
1182         inverta => GND,
1183         aload => GND);
1184 \HSYNC_STATE_6_\: stratix_lcell generic map (
1185     operation_mode => "normal",
1186     output_mode => "reg_only",
1187     synch_mode => "off",
1188      sum_lutc_input => "datac",
1189     lut_mask => "ff00")
1190 port map (
1191 regout => HSYNC_STATE_22,
1192 clk => clk_pin_c,
1193 datad => UN6_DLY_COUNTER_0_X_58,
1194         devpor => devpor,
1195         devclrn => devclrn,
1196         dataa => VCC,
1197         datab => VCC,
1198         datac => VCC,
1199         aclr => GND,
1200         sclr => GND,
1201         sload => GND,
1202         ena => VCC,
1203         cin => GND,
1204         inverta => GND,
1205         aload => GND);
1206 \VSYNC_STATE_0_\: stratix_lcell generic map (
1207     operation_mode => "normal",
1208     output_mode => "reg_only",
1209     synch_mode => "off",
1210      sum_lutc_input => "datac",
1211     lut_mask => "30ba")
1212 port map (
1213 regout => VSYNC_STATE_15,
1214 clk => clk_pin_c,
1215 dataa => VSYNC_STATE_15,
1216 datab => UN6_DLY_COUNTER_0_X_58,
1217 datac => \VSYNC_STATE_3_IV_0_0__G0_0_A3_0\,
1218 datad => VSYNC_STATE_NEXT_2_SQMUXA,
1219         devpor => devpor,
1220         devclrn => devclrn,
1221         aclr => GND,
1222         sclr => GND,
1223         sload => GND,
1224         ena => VCC,
1225         cin => GND,
1226         inverta => GND,
1227         aload => GND);
1228 \VSYNC_STATE_1_\: stratix_lcell generic map (
1229     operation_mode => "normal",
1230     output_mode => "reg_only",
1231     synch_mode => "off",
1232      sum_lutc_input => "datac",
1233     lut_mask => "0080")
1234 port map (
1235 regout => VSYNC_STATE_14,
1236 clk => clk_pin_c,
1237 dataa => VSYNC_STATE_13,
1238 datab => UN12_VSYNC_COUNTER_7,
1239 datac => UN13_VSYNC_COUNTER_4,
1240 datad => UN6_DLY_COUNTER_0_X_58,
1241         devpor => devpor,
1242         devclrn => devclrn,
1243         aclr => GND,
1244         sclr => GND,
1245         sload => GND,
1246         ena => VCC,
1247         cin => GND,
1248         inverta => GND,
1249         aload => GND);
1250 \VSYNC_STATE_6_\: stratix_lcell generic map (
1251     operation_mode => "normal",
1252     output_mode => "reg_and_comb",
1253     synch_mode => "off",
1254      sum_lutc_input => "datac",
1255     lut_mask => "7f7f")
1256 port map (
1257 combout => UN6_DLY_COUNTER_0_X_58,
1258 regout => VSYNC_STATE_12,
1259 clk => clk_pin_c,
1260 dataa => reset_pin_c,
1261 datab => dly_counter_0,
1262 datac => dly_counter_1,
1263         devpor => devpor,
1264         devclrn => devclrn,
1265         datad => VCC,
1266         aclr => GND,
1267         sclr => GND,
1268         sload => GND,
1269         ena => VCC,
1270         cin => GND,
1271         inverta => GND,
1272         aload => GND);
1273 \LINE_COUNTER_SIG_8_\: stratix_lcell generic map (
1274     operation_mode => "normal",
1275     output_mode => "reg_only",
1276     synch_mode => "on",
1277      sum_lutc_input => "datac",
1278     lut_mask => "dddd")
1279 port map (
1280 regout => LINE_COUNTER_SIG_8_0,
1281 clk => clk_pin_c,
1282 dataa => UN10_LINE_COUNTER_SIGLTO8,
1283 datab => UN1_LINE_COUNTER_SIG_COMBOUT(9),
1284 sclr => LINE_COUNTER_NEXT_0_SQMUXA_1_1_I,
1285         devpor => devpor,
1286         devclrn => devclrn,
1287         datac => VCC,
1288         datad => VCC,
1289         aclr => GND,
1290         sload => GND,
1291         ena => VCC,
1292         cin => GND,
1293         inverta => GND,
1294         aload => GND);
1295 \LINE_COUNTER_SIG_7_\: stratix_lcell generic map (
1296     operation_mode => "normal",
1297     output_mode => "reg_only",
1298     synch_mode => "on",
1299      sum_lutc_input => "datac",
1300     lut_mask => "dddd")
1301 port map (
1302 regout => LINE_COUNTER_SIG_7_0,
1303 clk => clk_pin_c,
1304 dataa => UN10_LINE_COUNTER_SIGLTO8,
1305 datab => UN1_LINE_COUNTER_SIG_COMBOUT(8),
1306 sclr => LINE_COUNTER_NEXT_0_SQMUXA_1_1_I,
1307         devpor => devpor,
1308         devclrn => devclrn,
1309         datac => VCC,
1310         datad => VCC,
1311         aclr => GND,
1312         sload => GND,
1313         ena => VCC,
1314         cin => GND,
1315         inverta => GND,
1316         aload => GND);
1317 \LINE_COUNTER_SIG_6_\: stratix_lcell generic map (
1318     operation_mode => "normal",
1319     output_mode => "reg_only",
1320     synch_mode => "on",
1321      sum_lutc_input => "datac",
1322     lut_mask => "dddd")
1323 port map (
1324 regout => LINE_COUNTER_SIG_6_0,
1325 clk => clk_pin_c,
1326 dataa => UN10_LINE_COUNTER_SIGLTO8,
1327 datab => UN1_LINE_COUNTER_SIG_COMBOUT(7),
1328 sclr => LINE_COUNTER_NEXT_0_SQMUXA_1_1_I,
1329         devpor => devpor,
1330         devclrn => devclrn,
1331         datac => VCC,
1332         datad => VCC,
1333         aclr => GND,
1334         sload => GND,
1335         ena => VCC,
1336         cin => GND,
1337         inverta => GND,
1338         aload => GND);
1339 \LINE_COUNTER_SIG_5_\: stratix_lcell generic map (
1340     operation_mode => "normal",
1341     output_mode => "reg_only",
1342     synch_mode => "off",
1343      sum_lutc_input => "datac",
1344     lut_mask => "8080")
1345 port map (
1346 regout => LINE_COUNTER_SIG_5_0,
1347 clk => clk_pin_c,
1348 dataa => UN10_LINE_COUNTER_SIGLTO8,
1349 datab => LINE_COUNTER_NEXT_0_SQMUXA_1_1,
1350 datac => UN1_LINE_COUNTER_SIG_COMBOUT(6),
1351         devpor => devpor,
1352         devclrn => devclrn,
1353         datad => VCC,
1354         aclr => GND,
1355         sclr => GND,
1356         sload => GND,
1357         ena => VCC,
1358         cin => GND,
1359         inverta => GND,
1360         aload => GND);
1361 \LINE_COUNTER_SIG_4_\: stratix_lcell generic map (
1362     operation_mode => "normal",
1363     output_mode => "reg_only",
1364     synch_mode => "on",
1365      sum_lutc_input => "datac",
1366     lut_mask => "dddd")
1367 port map (
1368 regout => LINE_COUNTER_SIG_4_0,
1369 clk => clk_pin_c,
1370 dataa => UN10_LINE_COUNTER_SIGLTO8,
1371 datab => UN1_LINE_COUNTER_SIG_COMBOUT(5),
1372 sclr => LINE_COUNTER_NEXT_0_SQMUXA_1_1_I,
1373         devpor => devpor,
1374         devclrn => devclrn,
1375         datac => VCC,
1376         datad => VCC,
1377         aclr => GND,
1378         sload => GND,
1379         ena => VCC,
1380         cin => GND,
1381         inverta => GND,
1382         aload => GND);
1383 \LINE_COUNTER_SIG_3_\: stratix_lcell generic map (
1384     operation_mode => "normal",
1385     output_mode => "reg_only",
1386     synch_mode => "on",
1387      sum_lutc_input => "datac",
1388     lut_mask => "dddd")
1389 port map (
1390 regout => LINE_COUNTER_SIG_3_0,
1391 clk => clk_pin_c,
1392 dataa => UN10_LINE_COUNTER_SIGLTO8,
1393 datab => UN1_LINE_COUNTER_SIG_COMBOUT(4),
1394 sclr => LINE_COUNTER_NEXT_0_SQMUXA_1_1_I,
1395         devpor => devpor,
1396         devclrn => devclrn,
1397         datac => VCC,
1398         datad => VCC,
1399         aclr => GND,
1400         sload => GND,
1401         ena => VCC,
1402         cin => GND,
1403         inverta => GND,
1404         aload => GND);
1405 \LINE_COUNTER_SIG_2_\: stratix_lcell generic map (
1406     operation_mode => "normal",
1407     output_mode => "reg_only",
1408     synch_mode => "on",
1409      sum_lutc_input => "datac",
1410     lut_mask => "dddd")
1411 port map (
1412 regout => LINE_COUNTER_SIG_2_0,
1413 clk => clk_pin_c,
1414 dataa => UN10_LINE_COUNTER_SIGLTO8,
1415 datab => UN1_LINE_COUNTER_SIG_COMBOUT(3),
1416 sclr => LINE_COUNTER_NEXT_0_SQMUXA_1_1_I,
1417         devpor => devpor,
1418         devclrn => devclrn,
1419         datac => VCC,
1420         datad => VCC,
1421         aclr => GND,
1422         sload => GND,
1423         ena => VCC,
1424         cin => GND,
1425         inverta => GND,
1426         aload => GND);
1427 \LINE_COUNTER_SIG_1_\: stratix_lcell generic map (
1428     operation_mode => "normal",
1429     output_mode => "reg_only",
1430     synch_mode => "on",
1431      sum_lutc_input => "datac",
1432     lut_mask => "dddd")
1433 port map (
1434 regout => LINE_COUNTER_SIG_1_0,
1435 clk => clk_pin_c,
1436 dataa => UN10_LINE_COUNTER_SIGLTO8,
1437 datab => UN1_LINE_COUNTER_SIG_COMBOUT(2),
1438 sclr => LINE_COUNTER_NEXT_0_SQMUXA_1_1_I,
1439         devpor => devpor,
1440         devclrn => devclrn,
1441         datac => VCC,
1442         datad => VCC,
1443         aclr => GND,
1444         sload => GND,
1445         ena => VCC,
1446         cin => GND,
1447         inverta => GND,
1448         aload => GND);
1449 \LINE_COUNTER_SIG_0_\: stratix_lcell generic map (
1450     operation_mode => "normal",
1451     output_mode => "reg_only",
1452     synch_mode => "on",
1453      sum_lutc_input => "datac",
1454     lut_mask => "bbbb")
1455 port map (
1456 regout => LINE_COUNTER_SIG_0_0,
1457 clk => clk_pin_c,
1458 dataa => UN1_LINE_COUNTER_SIG_COMBOUT(1),
1459 datab => UN10_LINE_COUNTER_SIGLTO8,
1460 sclr => LINE_COUNTER_NEXT_0_SQMUXA_1_1_I,
1461         devpor => devpor,
1462         devclrn => devclrn,
1463         datac => VCC,
1464         datad => VCC,
1465         aclr => GND,
1466         sload => GND,
1467         ena => VCC,
1468         cin => GND,
1469         inverta => GND,
1470         aload => GND);
1471 V_ENABLE_SIG_Z286: stratix_lcell generic map (
1472     operation_mode => "normal",
1473     output_mode => "reg_only",
1474     synch_mode => "on",
1475      sum_lutc_input => "datac",
1476     lut_mask => "eeee")
1477 port map (
1478 regout => v_enable_sig,
1479 clk => clk_pin_c,
1480 dataa => HSYNC_STATE_21,
1481 datab => HSYNC_STATE_20,
1482 sclr => UN6_DLY_COUNTER_0_X_58,
1483 ena => V_ENABLE_SIG_1_0_0_0_G0_I_O4,
1484         devpor => devpor,
1485         devclrn => devclrn,
1486         datac => VCC,
1487         datad => VCC,
1488         aclr => GND,
1489         sload => GND,
1490         cin => GND,
1491         inverta => GND,
1492         aload => GND);
1493 H_ENABLE_SIG_Z287: stratix_lcell generic map (
1494     operation_mode => "normal",
1495     output_mode => "reg_only",
1496     synch_mode => "on",
1497      sum_lutc_input => "datac",
1498     lut_mask => "eeee")
1499 port map (
1500 regout => h_enable_sig,
1501 clk => clk_pin_c,
1502 dataa => VSYNC_STATE_11,
1503 datab => VSYNC_STATE_14,
1504 sclr => UN6_DLY_COUNTER_0_X_58,
1505 ena => H_ENABLE_SIG_1_0_0_0_G0_I_O4,
1506         devpor => devpor,
1507         devclrn => devclrn,
1508         datac => VCC,
1509         datad => VCC,
1510         aclr => GND,
1511         sload => GND,
1512         cin => GND,
1513         inverta => GND,
1514         aload => GND);
1515 H_SYNC_Z288: stratix_lcell generic map (
1516     operation_mode => "normal",
1517     output_mode => "reg_only",
1518     synch_mode => "off",
1519      sum_lutc_input => "datac",
1520     lut_mask => "ff7f")
1521 port map (
1522 regout => H_SYNC_57,
1523 clk => clk_pin_c,
1524 dataa => reset_pin_c,
1525 datab => dly_counter_0,
1526 datac => dly_counter_1,
1527 datad => H_SYNC_1_0_0_0_G1,
1528         devpor => devpor,
1529         devclrn => devclrn,
1530         aclr => GND,
1531         sclr => GND,
1532         sload => GND,
1533         ena => VCC,
1534         cin => GND,
1535         inverta => GND,
1536         aload => GND);
1537 V_SYNC_Z289: stratix_lcell generic map (
1538     operation_mode => "normal",
1539     output_mode => "reg_only",
1540     synch_mode => "off",
1541      sum_lutc_input => "datac",
1542     lut_mask => "ff7f")
1543 port map (
1544 regout => V_SYNC_56,
1545 clk => clk_pin_c,
1546 dataa => reset_pin_c,
1547 datab => dly_counter_0,
1548 datac => dly_counter_1,
1549 datad => V_SYNC_1_0_0_0_G1,
1550         devpor => devpor,
1551         devclrn => devclrn,
1552         aclr => GND,
1553         sclr => GND,
1554         sload => GND,
1555         ena => VCC,
1556         cin => GND,
1557         inverta => GND,
1558         aload => GND);
1559 \VSYNC_STATE_5_\: stratix_lcell generic map (
1560     operation_mode => "normal",
1561     output_mode => "reg_only",
1562     synch_mode => "on",
1563      sum_lutc_input => "datac",
1564     lut_mask => "eeee")
1565 port map (
1566 regout => VSYNC_STATE_10,
1567 clk => clk_pin_c,
1568 dataa => VSYNC_STATE_12,
1569 datab => VSYNC_STATE_15,
1570 sclr => UN6_DLY_COUNTER_0_X_58,
1571 ena => VSYNC_STATE_NEXT_2_SQMUXA,
1572         devpor => devpor,
1573         devclrn => devclrn,
1574         datac => VCC,
1575         datad => VCC,
1576         aclr => GND,
1577         sload => GND,
1578         cin => GND,
1579         inverta => GND,
1580         aload => GND);
1581 \VSYNC_STATE_4_\: stratix_lcell generic map (
1582     operation_mode => "normal",
1583     output_mode => "reg_only",
1584     synch_mode => "on",
1585      sum_lutc_input => "datac",
1586     lut_mask => "2000")
1587 port map (
1588 regout => VSYNC_STATE_13,
1589 clk => clk_pin_c,
1590 dataa => VSYNC_COUNTER_42,
1591 datab => VSYNC_COUNTER_33,
1592 datac => VSYNC_STATE_10,
1593 datad => UN14_VSYNC_COUNTER_8,
1594 sclr => UN6_DLY_COUNTER_0_X_58,
1595 ena => VSYNC_STATE_NEXT_2_SQMUXA,
1596         devpor => devpor,
1597         devclrn => devclrn,
1598         aclr => GND,
1599         sload => GND,
1600         cin => GND,
1601         inverta => GND,
1602         aload => GND);
1603 \VSYNC_STATE_3_\: stratix_lcell generic map (
1604     operation_mode => "normal",
1605     output_mode => "reg_only",
1606     synch_mode => "on",
1607      sum_lutc_input => "datac",
1608     lut_mask => "aaaa")
1609 port map (
1610 regout => VSYNC_STATE_11,
1611 clk => clk_pin_c,
1612 dataa => VSYNC_STATE_14,
1613 sclr => UN6_DLY_COUNTER_0_X_58,
1614 ena => VSYNC_STATE_NEXT_2_SQMUXA,
1615         devpor => devpor,
1616         devclrn => devclrn,
1617         datab => VCC,
1618         datac => VCC,
1619         datad => VCC,
1620         aclr => GND,
1621         sload => GND,
1622         cin => GND,
1623         inverta => GND,
1624         aload => GND);
1625 \VSYNC_STATE_2_\: stratix_lcell generic map (
1626     operation_mode => "normal",
1627     output_mode => "reg_only",
1628     synch_mode => "on",
1629      sum_lutc_input => "datac",
1630     lut_mask => "8000")
1631 port map (
1632 regout => VSYNC_STATE_9,
1633 clk => clk_pin_c,
1634 dataa => VSYNC_COUNTER_42,
1635 datab => VSYNC_COUNTER_33,
1636 datac => VSYNC_STATE_11,
1637 datad => UN14_VSYNC_COUNTER_8,
1638 sclr => UN6_DLY_COUNTER_0_X_58,
1639 ena => VSYNC_STATE_NEXT_2_SQMUXA,
1640         devpor => devpor,
1641         devclrn => devclrn,
1642         aclr => GND,
1643         sload => GND,
1644         cin => GND,
1645         inverta => GND,
1646         aload => GND);
1647 \HSYNC_STATE_5_\: stratix_lcell generic map (
1648     operation_mode => "normal",
1649     output_mode => "reg_only",
1650     synch_mode => "on",
1651      sum_lutc_input => "datac",
1652     lut_mask => "eeee")
1653 port map (
1654 regout => HSYNC_STATE_19,
1655 clk => clk_pin_c,
1656 dataa => HSYNC_STATE_22,
1657 datab => HSYNC_STATE_18,
1658 sclr => UN6_DLY_COUNTER_0_X_58,
1659 ena => \HSYNC_STATE_3_0_0_0__G0_0\,
1660         devpor => devpor,
1661         devclrn => devclrn,
1662         datac => VCC,
1663         datad => VCC,
1664         aclr => GND,
1665         sload => GND,
1666         cin => GND,
1667         inverta => GND,
1668         aload => GND);
1669 \HSYNC_STATE_4_\: stratix_lcell generic map (
1670     operation_mode => "normal",
1671     output_mode => "reg_only",
1672     synch_mode => "on",
1673      sum_lutc_input => "datac",
1674     lut_mask => "8000")
1675 port map (
1676 regout => HSYNC_STATE_17,
1677 clk => clk_pin_c,
1678 dataa => HSYNC_STATE_19,
1679 datab => UN10_HSYNC_COUNTER_3,
1680 datac => UN10_HSYNC_COUNTER_1,
1681 datad => UN10_HSYNC_COUNTER_4,
1682 sclr => UN6_DLY_COUNTER_0_X_58,
1683 ena => \HSYNC_STATE_3_0_0_0__G0_0\,
1684         devpor => devpor,
1685         devclrn => devclrn,
1686         aclr => GND,
1687         sload => GND,
1688         cin => GND,
1689         inverta => GND,
1690         aload => GND);
1691 \HSYNC_STATE_3_\: stratix_lcell generic map (
1692     operation_mode => "normal",
1693     output_mode => "reg_only",
1694     synch_mode => "on",
1695      sum_lutc_input => "datac",
1696     lut_mask => "aaaa")
1697 port map (
1698 regout => HSYNC_STATE_21,
1699 clk => clk_pin_c,
1700 dataa => HSYNC_STATE_20,
1701 sclr => UN6_DLY_COUNTER_0_X_58,
1702 ena => \HSYNC_STATE_3_0_0_0__G0_0\,
1703         devpor => devpor,
1704         devclrn => devclrn,
1705         datab => VCC,
1706         datac => VCC,
1707         datad => VCC,
1708         aclr => GND,
1709         sload => GND,
1710         cin => GND,
1711         inverta => GND,
1712         aload => GND);
1713 \HSYNC_STATE_2_\: stratix_lcell generic map (
1714     operation_mode => "normal",
1715     output_mode => "reg_only",
1716     synch_mode => "on",
1717      sum_lutc_input => "datac",
1718     lut_mask => "8888")
1719 port map (
1720 regout => HSYNC_STATE_16,
1721 clk => clk_pin_c,
1722 dataa => HSYNC_STATE_21,
1723 datab => UN12_HSYNC_COUNTER,
1724 sclr => UN6_DLY_COUNTER_0_X_58,
1725 ena => \HSYNC_STATE_3_0_0_0__G0_0\,
1726         devpor => devpor,
1727         devclrn => devclrn,
1728         datac => VCC,
1729         datad => VCC,
1730         aclr => GND,
1731         sload => GND,
1732         cin => GND,
1733         inverta => GND,
1734         aload => GND);
1735 \HSYNC_STATE_1_\: stratix_lcell generic map (
1736     operation_mode => "normal",
1737     output_mode => "reg_only",
1738     synch_mode => "on",
1739      sum_lutc_input => "datac",
1740     lut_mask => "8000")
1741 port map (
1742 regout => HSYNC_STATE_20,
1743 clk => clk_pin_c,
1744 dataa => HSYNC_STATE_17,
1745 datab => UN11_HSYNC_COUNTER_2,
1746 datac => UN10_HSYNC_COUNTER_1,
1747 datad => UN11_HSYNC_COUNTER_3,
1748 sclr => UN6_DLY_COUNTER_0_X_58,
1749 ena => \HSYNC_STATE_3_0_0_0__G0_0\,
1750         devpor => devpor,
1751         devclrn => devclrn,
1752         aclr => GND,
1753         sload => GND,
1754         cin => GND,
1755         inverta => GND,
1756         aload => GND);
1757 \HSYNC_STATE_0_\: stratix_lcell generic map (
1758     operation_mode => "normal",
1759     output_mode => "reg_only",
1760     synch_mode => "on",
1761      sum_lutc_input => "datac",
1762     lut_mask => "8888")
1763 port map (
1764 regout => HSYNC_STATE_18,
1765 clk => clk_pin_c,
1766 dataa => HSYNC_STATE_16,
1767 datab => UN13_HSYNC_COUNTER,
1768 sclr => UN6_DLY_COUNTER_0_X_58,
1769 ena => \HSYNC_STATE_3_0_0_0__G0_0\,
1770         devpor => devpor,
1771         devclrn => devclrn,
1772         datac => VCC,
1773         datad => VCC,
1774         aclr => GND,
1775         sload => GND,
1776         cin => GND,
1777         inverta => GND,
1778         aload => GND);
1779 VSYNC_STATE_NEXT_2_SQMUXA_Z300: stratix_lcell generic map (
1780     operation_mode => "normal",
1781     output_mode => "comb_only",
1782     synch_mode => "off",
1783      sum_lutc_input => "datac",
1784     lut_mask => "aaab")
1785 port map (
1786 combout => VSYNC_STATE_NEXT_2_SQMUXA,
1787 dataa => UN6_DLY_COUNTER_0_X_58,
1788 datab => VSYNC_STATE_NEXT_1_SQMUXA_1,
1789 datac => VSYNC_STATE_NEXT_1_SQMUXA_3,
1790 datad => UN1_VSYNC_STATE_NEXT_1_SQMUXA_0,
1791         devpor => devpor,
1792         devclrn => devclrn,
1793         clk => GND,
1794         aclr => GND,
1795         sclr => GND,
1796         sload => GND,
1797         ena => VCC,
1798         cin => GND,
1799         inverta => GND,
1800         aload => GND);
1801 \HSYNC_STATE_3_0_0_0__G0_0_Z301\: stratix_lcell generic map (
1802     operation_mode => "normal",
1803     output_mode => "comb_only",
1804     synch_mode => "off",
1805      sum_lutc_input => "datac",
1806     lut_mask => "f0f1")
1807 port map (
1808 combout => \HSYNC_STATE_3_0_0_0__G0_0\,
1809 dataa => HSYNC_STATE_NEXT_1_SQMUXA_1,
1810 datab => HSYNC_STATE_NEXT_1_SQMUXA_2,
1811 datac => UN6_DLY_COUNTER_0_X_58,
1812 datad => UN1_HSYNC_STATE_NEXT_1_SQMUXA_0,
1813         devpor => devpor,
1814         devclrn => devclrn,
1815         clk => GND,
1816         aclr => GND,
1817         sclr => GND,
1818         sload => GND,
1819         ena => VCC,
1820         cin => GND,
1821         inverta => GND,
1822         aload => GND);
1823 UN1_HSYNC_STATE_NEXT_1_SQMUXA_0_Z302: stratix_lcell generic map (
1824     operation_mode => "normal",
1825     output_mode => "comb_only",
1826     synch_mode => "off",
1827      sum_lutc_input => "datac",
1828     lut_mask => "0ace")
1829 port map (
1830 combout => UN1_HSYNC_STATE_NEXT_1_SQMUXA_0,
1831 dataa => HSYNC_STATE_16,
1832 datab => HSYNC_STATE_21,
1833 datac => UN13_HSYNC_COUNTER,
1834 datad => UN12_HSYNC_COUNTER,
1835         devpor => devpor,
1836         devclrn => devclrn,
1837         clk => GND,
1838         aclr => GND,
1839         sclr => GND,
1840         sload => GND,
1841         ena => VCC,
1842         cin => GND,
1843         inverta => GND,
1844         aload => GND);
1845 UN1_VSYNC_STATE_NEXT_1_SQMUXA_0_Z303: stratix_lcell generic map (
1846     operation_mode => "normal",
1847     output_mode => "comb_only",
1848     synch_mode => "off",
1849      sum_lutc_input => "datac",
1850     lut_mask => "ff2a")
1851 port map (
1852 combout => UN1_VSYNC_STATE_NEXT_1_SQMUXA_0,
1853 dataa => VSYNC_STATE_9,
1854 datab => UN12_VSYNC_COUNTER_6,
1855 datac => UN15_VSYNC_COUNTER_4,
1856 datad => VSYNC_STATE_NEXT_1_SQMUXA_2,
1857         devpor => devpor,
1858         devclrn => devclrn,
1859         clk => GND,
1860         aclr => GND,
1861         sclr => GND,
1862         sload => GND,
1863         ena => VCC,
1864         cin => GND,
1865         inverta => GND,
1866         aload => GND);
1867 COLUMN_COUNT_NEXT_UN10_COLUMN_COUNTER_SIGLTO9: stratix_lcell generic map (
1868     operation_mode => "normal",
1869     output_mode => "comb_only",
1870     synch_mode => "off",
1871      sum_lutc_input => "datac",
1872     lut_mask => "1f0f")
1873 port map (
1874 combout => UN10_COLUMN_COUNTER_SIGLTO9,
1875 dataa => COLUMN_COUNTER_SIG_30,
1876 datab => COLUMN_COUNTER_SIG_31,
1877 datac => COLUMN_COUNTER_SIG_32,
1878 datad => UN10_COLUMN_COUNTER_SIGLT6,
1879         devpor => devpor,
1880         devclrn => devclrn,
1881         clk => GND,
1882         aclr => GND,
1883         sclr => GND,
1884         sload => GND,
1885         ena => VCC,
1886         cin => GND,
1887         inverta => GND,
1888         aload => GND);
1889 \VSYNC_STATE_3_IV_0_0__G0_0_A3_0_Z305\: stratix_lcell generic map (
1890     operation_mode => "normal",
1891     output_mode => "comb_only",
1892     synch_mode => "off",
1893      sum_lutc_input => "datac",
1894     lut_mask => "8080")
1895 port map (
1896 combout => \VSYNC_STATE_3_IV_0_0__G0_0_A3_0\,
1897 dataa => VSYNC_STATE_9,
1898 datab => UN12_VSYNC_COUNTER_6,
1899 datac => UN15_VSYNC_COUNTER_4,
1900         devpor => devpor,
1901         devclrn => devclrn,
1902         clk => GND,
1903         datad => VCC,
1904         aclr => GND,
1905         sclr => GND,
1906         sload => GND,
1907         ena => VCC,
1908         cin => GND,
1909         inverta => GND,
1910         aload => GND);
1911 LINE_COUNT_NEXT_UN10_LINE_COUNTER_SIGLTO8: stratix_lcell generic map (
1912     operation_mode => "normal",
1913     output_mode => "comb_only",
1914     synch_mode => "off",
1915      sum_lutc_input => "datac",
1916     lut_mask => "ff7f")
1917 port map (
1918 combout => UN10_LINE_COUNTER_SIGLTO8,
1919 dataa => LINE_COUNTER_SIG_6_0,
1920 datab => LINE_COUNTER_SIG_7_0,
1921 datac => LINE_COUNTER_SIG_8_0,
1922 datad => UN10_LINE_COUNTER_SIGLTO5,
1923         devpor => devpor,
1924         devclrn => devclrn,
1925         clk => GND,
1926         aclr => GND,
1927         sclr => GND,
1928         sload => GND,
1929         ena => VCC,
1930         cin => GND,
1931         inverta => GND,
1932         aload => GND);
1933 VSYNC_STATE_NEXT_1_SQMUXA_1_Z307: stratix_lcell generic map (
1934     operation_mode => "normal",
1935     output_mode => "comb_only",
1936     synch_mode => "off",
1937      sum_lutc_input => "datac",
1938     lut_mask => "d0f0")
1939 port map (
1940 combout => VSYNC_STATE_NEXT_1_SQMUXA_1,
1941 dataa => VSYNC_COUNTER_42,
1942 datab => VSYNC_COUNTER_33,
1943 datac => VSYNC_STATE_10,
1944 datad => UN14_VSYNC_COUNTER_8,
1945         devpor => devpor,
1946         devclrn => devclrn,
1947         clk => GND,
1948         aclr => GND,
1949         sclr => GND,
1950         sload => GND,
1951         ena => VCC,
1952         cin => GND,
1953         inverta => GND,
1954         aload => GND);
1955 VSYNC_STATE_NEXT_1_SQMUXA_2_Z308: stratix_lcell generic map (
1956     operation_mode => "normal",
1957     output_mode => "comb_only",
1958     synch_mode => "off",
1959      sum_lutc_input => "datac",
1960     lut_mask => "2a2a")
1961 port map (
1962 combout => VSYNC_STATE_NEXT_1_SQMUXA_2,
1963 dataa => VSYNC_STATE_13,
1964 datab => UN12_VSYNC_COUNTER_7,
1965 datac => UN13_VSYNC_COUNTER_4,
1966         devpor => devpor,
1967         devclrn => devclrn,
1968         clk => GND,
1969         datad => VCC,
1970         aclr => GND,
1971         sclr => GND,
1972         sload => GND,
1973         ena => VCC,
1974         cin => GND,
1975         inverta => GND,
1976         aload => GND);
1977 VSYNC_STATE_NEXT_1_SQMUXA_3_Z309: stratix_lcell generic map (
1978     operation_mode => "normal",
1979     output_mode => "comb_only",
1980     synch_mode => "off",
1981      sum_lutc_input => "datac",
1982     lut_mask => "70f0")
1983 port map (
1984 combout => VSYNC_STATE_NEXT_1_SQMUXA_3,
1985 dataa => VSYNC_COUNTER_42,
1986 datab => VSYNC_COUNTER_33,
1987 datac => VSYNC_STATE_11,
1988 datad => UN14_VSYNC_COUNTER_8,
1989         devpor => devpor,
1990         devclrn => devclrn,
1991         clk => GND,
1992         aclr => GND,
1993         sclr => GND,
1994         sload => GND,
1995         ena => VCC,
1996         cin => GND,
1997         inverta => GND,
1998         aload => GND);
1999 G_16: stratix_lcell generic map (
2000     operation_mode => "normal",
2001     output_mode => "comb_only",
2002     synch_mode => "off",
2003      sum_lutc_input => "datac",
2004     lut_mask => "0f1f")
2005 port map (
2006 combout => G_16_I,
2007 dataa => VSYNC_STATE_15,
2008 datab => VSYNC_STATE_12,
2009 datac => UN9_VSYNC_COUNTERLT9,
2010 datad => UN6_DLY_COUNTER_0_X_58,
2011         devpor => devpor,
2012         devclrn => devclrn,
2013         clk => GND,
2014         aclr => GND,
2015         sclr => GND,
2016         sload => GND,
2017         ena => VCC,
2018         cin => GND,
2019         inverta => GND,
2020         aload => GND);
2021 G_2: stratix_lcell generic map (
2022     operation_mode => "normal",
2023     output_mode => "comb_only",
2024     synch_mode => "off",
2025      sum_lutc_input => "datac",
2026     lut_mask => "0f1f")
2027 port map (
2028 combout => G_2_I,
2029 dataa => HSYNC_STATE_18,
2030 datab => HSYNC_STATE_22,
2031 datac => UN9_HSYNC_COUNTERLT9,
2032 datad => UN6_DLY_COUNTER_0_X_58,
2033         devpor => devpor,
2034         devclrn => devclrn,
2035         clk => GND,
2036         aclr => GND,
2037         sclr => GND,
2038         sload => GND,
2039         ena => VCC,
2040         cin => GND,
2041         inverta => GND,
2042         aload => GND);
2043 HSYNC_STATE_NEXT_1_SQMUXA_2_Z312: stratix_lcell generic map (
2044     operation_mode => "normal",
2045     output_mode => "comb_only",
2046     synch_mode => "off",
2047      sum_lutc_input => "datac",
2048     lut_mask => "2aaa")
2049 port map (
2050 combout => HSYNC_STATE_NEXT_1_SQMUXA_2,
2051 dataa => HSYNC_STATE_17,
2052 datab => UN11_HSYNC_COUNTER_2,
2053 datac => UN10_HSYNC_COUNTER_1,
2054 datad => UN11_HSYNC_COUNTER_3,
2055         devpor => devpor,
2056         devclrn => devclrn,
2057         clk => GND,
2058         aclr => GND,
2059         sclr => GND,
2060         sload => GND,
2061         ena => VCC,
2062         cin => GND,
2063         inverta => GND,
2064         aload => GND);
2065 HSYNC_STATE_NEXT_1_SQMUXA_1_Z313: stratix_lcell generic map (
2066     operation_mode => "normal",
2067     output_mode => "comb_only",
2068     synch_mode => "off",
2069      sum_lutc_input => "datac",
2070     lut_mask => "2aaa")
2071 port map (
2072 combout => HSYNC_STATE_NEXT_1_SQMUXA_1,
2073 dataa => HSYNC_STATE_19,
2074 datab => UN10_HSYNC_COUNTER_3,
2075 datac => UN10_HSYNC_COUNTER_1,
2076 datad => UN10_HSYNC_COUNTER_4,
2077         devpor => devpor,
2078         devclrn => devclrn,
2079         clk => GND,
2080         aclr => GND,
2081         sclr => GND,
2082         sload => GND,
2083         ena => VCC,
2084         cin => GND,
2085         inverta => GND,
2086         aload => GND);
2087 VSYNC_COUNT_NEXT_UN9_VSYNC_COUNTERLT9: stratix_lcell generic map (
2088     operation_mode => "normal",
2089     output_mode => "comb_only",
2090     synch_mode => "off",
2091      sum_lutc_input => "datac",
2092     lut_mask => "fff7")
2093 port map (
2094 combout => UN9_VSYNC_COUNTERLT9,
2095 dataa => VSYNC_COUNTER_38,
2096 datab => VSYNC_COUNTER_37,
2097 datac => UN9_VSYNC_COUNTERLT9_5,
2098 datad => UN9_VSYNC_COUNTERLT9_6,
2099         devpor => devpor,
2100         devclrn => devclrn,
2101         clk => GND,
2102         aclr => GND,
2103         sclr => GND,
2104         sload => GND,
2105         ena => VCC,
2106         cin => GND,
2107         inverta => GND,
2108         aload => GND);
2109 COLUMN_COUNT_NEXT_UN10_COLUMN_COUNTER_SIGLT6: stratix_lcell generic map (
2110     operation_mode => "normal",
2111     output_mode => "comb_only",
2112     synch_mode => "off",
2113      sum_lutc_input => "datac",
2114     lut_mask => "fff7")
2115 port map (
2116 combout => UN10_COLUMN_COUNTER_SIGLT6,
2117 dataa => COLUMN_COUNTER_SIG_26,
2118 datab => COLUMN_COUNTER_SIG_27,
2119 datac => UN10_COLUMN_COUNTER_SIGLT6_55,
2120 datad => UN10_COLUMN_COUNTER_SIGLT6_54,
2121         devpor => devpor,
2122         devclrn => devclrn,
2123         clk => GND,
2124         aclr => GND,
2125         sclr => GND,
2126         sload => GND,
2127         ena => VCC,
2128         cin => GND,
2129         inverta => GND,
2130         aload => GND);
2131 HSYNC_FSM_NEXT_UN12_HSYNC_COUNTER: stratix_lcell generic map (
2132     operation_mode => "normal",
2133     output_mode => "comb_only",
2134     synch_mode => "off",
2135      sum_lutc_input => "datac",
2136     lut_mask => "8000")
2137 port map (
2138 combout => UN12_HSYNC_COUNTER,
2139 dataa => HSYNC_COUNTER_52,
2140 datab => HSYNC_COUNTER_51,
2141 datac => UN12_HSYNC_COUNTER_3,
2142 datad => UN12_HSYNC_COUNTER_4,
2143         devpor => devpor,
2144         devclrn => devclrn,
2145         clk => GND,
2146         aclr => GND,
2147         sclr => GND,
2148         sload => GND,
2149         ena => VCC,
2150         cin => GND,
2151         inverta => GND,
2152         aload => GND);
2153 HSYNC_FSM_NEXT_UN13_HSYNC_COUNTER: stratix_lcell generic map (
2154     operation_mode => "normal",
2155     output_mode => "comb_only",
2156     synch_mode => "off",
2157      sum_lutc_input => "datac",
2158     lut_mask => "1000")
2159 port map (
2160 combout => UN13_HSYNC_COUNTER,
2161 dataa => HSYNC_COUNTER_46,
2162 datab => HSYNC_COUNTER_45,
2163 datac => UN13_HSYNC_COUNTER_2,
2164 datad => UN13_HSYNC_COUNTER_7,
2165         devpor => devpor,
2166         devclrn => devclrn,
2167         clk => GND,
2168         aclr => GND,
2169         sclr => GND,
2170         sload => GND,
2171         ena => VCC,
2172         cin => GND,
2173         inverta => GND,
2174         aload => GND);
2175 HSYNC_COUNT_NEXT_UN9_HSYNC_COUNTERLT9: stratix_lcell generic map (
2176     operation_mode => "normal",
2177     output_mode => "comb_only",
2178     synch_mode => "off",
2179      sum_lutc_input => "datac",
2180     lut_mask => "f7ff")
2181 port map (
2182 combout => UN9_HSYNC_COUNTERLT9,
2183 dataa => HSYNC_COUNTER_48,
2184 datab => HSYNC_COUNTER_47,
2185 datac => UN9_HSYNC_COUNTERLT9_3,
2186 datad => UN13_HSYNC_COUNTER_7,
2187         devpor => devpor,
2188         devclrn => devclrn,
2189         clk => GND,
2190         aclr => GND,
2191         sclr => GND,
2192         sload => GND,
2193         ena => VCC,
2194         cin => GND,
2195         inverta => GND,
2196         aload => GND);
2197 LINE_COUNT_NEXT_UN10_LINE_COUNTER_SIGLTO5: stratix_lcell generic map (
2198     operation_mode => "normal",
2199     output_mode => "comb_only",
2200     synch_mode => "off",
2201      sum_lutc_input => "datac",
2202     lut_mask => "0f07")
2203 port map (
2204 combout => UN10_LINE_COUNTER_SIGLTO5,
2205 dataa => LINE_COUNTER_SIG_1_0,
2206 datab => LINE_COUNTER_SIG_2_0,
2207 datac => LINE_COUNTER_SIG_5_0,
2208 datad => UN10_LINE_COUNTER_SIGLT4_2,
2209         devpor => devpor,
2210         devclrn => devclrn,
2211         clk => GND,
2212         aclr => GND,
2213         sclr => GND,
2214         sload => GND,
2215         ena => VCC,
2216         cin => GND,
2217         inverta => GND,
2218         aload => GND);
2219 VSYNC_FSM_NEXT_UN13_VSYNC_COUNTER_4: stratix_lcell generic map (
2220     operation_mode => "normal",
2221     output_mode => "comb_only",
2222     synch_mode => "off",
2223      sum_lutc_input => "datac",
2224     lut_mask => "8080")
2225 port map (
2226 combout => UN13_VSYNC_COUNTER_4,
2227 dataa => VSYNC_COUNTER_42,
2228 datab => VSYNC_COUNTER_37,
2229 datac => UN13_VSYNC_COUNTER_3,
2230         devpor => devpor,
2231         devclrn => devclrn,
2232         clk => GND,
2233         datad => VCC,
2234         aclr => GND,
2235         sclr => GND,
2236         sload => GND,
2237         ena => VCC,
2238         cin => GND,
2239         inverta => GND,
2240         aload => GND);
2241 VSYNC_FSM_NEXT_UN15_VSYNC_COUNTER_4: stratix_lcell generic map (
2242     operation_mode => "normal",
2243     output_mode => "comb_only",
2244     synch_mode => "off",
2245      sum_lutc_input => "datac",
2246     lut_mask => "1010")
2247 port map (
2248 combout => UN15_VSYNC_COUNTER_4,
2249 dataa => VSYNC_COUNTER_41,
2250 datab => VSYNC_COUNTER_38,
2251 datac => UN15_VSYNC_COUNTER_3,
2252         devpor => devpor,
2253         devclrn => devclrn,
2254         clk => GND,
2255         datad => VCC,
2256         aclr => GND,
2257         sclr => GND,
2258         sload => GND,
2259         ena => VCC,
2260         cin => GND,
2261         inverta => GND,
2262         aload => GND);
2263 LINE_COUNTER_NEXT_0_SQMUXA_1_1_Z322: stratix_lcell generic map (
2264     operation_mode => "normal",
2265     output_mode => "comb_only",
2266     synch_mode => "off",
2267      sum_lutc_input => "datac",
2268     lut_mask => "0080")
2269 port map (
2270 combout => LINE_COUNTER_NEXT_0_SQMUXA_1_1,
2271 dataa => reset_pin_c,
2272 datab => dly_counter_0,
2273 datac => dly_counter_1,
2274 datad => VSYNC_STATE_14,
2275         devpor => devpor,
2276         devclrn => devclrn,
2277         clk => GND,
2278         aclr => GND,
2279         sclr => GND,
2280         sload => GND,
2281         ena => VCC,
2282         cin => GND,
2283         inverta => GND,
2284         aload => GND);
2285 V_SYNC_1_0_0_0_G1_Z323: stratix_lcell generic map (
2286     operation_mode => "normal",
2287     output_mode => "comb_only",
2288     synch_mode => "off",
2289      sum_lutc_input => "datac",
2290     lut_mask => "ccd8")
2291 port map (
2292 combout => V_SYNC_1_0_0_0_G1,
2293 dataa => VSYNC_STATE_9,
2294 datab => V_SYNC_56,
2295 datac => VSYNC_STATE_13,
2296 datad => UN1_VSYNC_STATE_2_0,
2297         devpor => devpor,
2298         devclrn => devclrn,
2299         clk => GND,
2300         aclr => GND,
2301         sclr => GND,
2302         sload => GND,
2303         ena => VCC,
2304         cin => GND,
2305         inverta => GND,
2306         aload => GND);
2307 H_ENABLE_SIG_1_0_0_0_G0_I_O4_Z324: stratix_lcell generic map (
2308     operation_mode => "normal",
2309     output_mode => "comb_only",
2310     synch_mode => "off",
2311      sum_lutc_input => "datac",
2312     lut_mask => "f1f1")
2313 port map (
2314 combout => H_ENABLE_SIG_1_0_0_0_G0_I_O4,
2315 dataa => VSYNC_STATE_13,
2316 datab => VSYNC_STATE_10,
2317 datac => UN6_DLY_COUNTER_0_X_58,
2318         devpor => devpor,
2319         devclrn => devclrn,
2320         clk => GND,
2321         datad => VCC,
2322         aclr => GND,
2323         sclr => GND,
2324         sload => GND,
2325         ena => VCC,
2326         cin => GND,
2327         inverta => GND,
2328         aload => GND);
2329 VSYNC_COUNTER_NEXT_1_SQMUXA_Z325: stratix_lcell generic map (
2330     operation_mode => "normal",
2331     output_mode => "comb_only",
2332     synch_mode => "off",
2333      sum_lutc_input => "datac",
2334     lut_mask => "0080")
2335 port map (
2336 combout => VSYNC_COUNTER_NEXT_1_SQMUXA,
2337 dataa => reset_pin_c,
2338 datab => dly_counter_0,
2339 datac => dly_counter_1,
2340 datad => D_SET_VSYNC_COUNTER_53,
2341         devpor => devpor,
2342         devclrn => devclrn,
2343         clk => GND,
2344         aclr => GND,
2345         sclr => GND,
2346         sload => GND,
2347         ena => VCC,
2348         cin => GND,
2349         inverta => GND,
2350         aload => GND);
2351 VSYNC_FSM_NEXT_UN14_VSYNC_COUNTER_8: stratix_lcell generic map (
2352     operation_mode => "normal",
2353     output_mode => "comb_only",
2354     synch_mode => "off",
2355      sum_lutc_input => "datac",
2356     lut_mask => "8888")
2357 port map (
2358 combout => UN14_VSYNC_COUNTER_8,
2359 dataa => UN12_VSYNC_COUNTER_6,
2360 datab => UN12_VSYNC_COUNTER_7,
2361         devpor => devpor,
2362         devclrn => devclrn,
2363         clk => GND,
2364         datac => VCC,
2365         datad => VCC,
2366         aclr => GND,
2367         sclr => GND,
2368         sload => GND,
2369         ena => VCC,
2370         cin => GND,
2371         inverta => GND,
2372         aload => GND);
2373 HSYNC_COUNTER_NEXT_1_SQMUXA_Z327: stratix_lcell generic map (
2374     operation_mode => "normal",
2375     output_mode => "comb_only",
2376     synch_mode => "off",
2377      sum_lutc_input => "datac",
2378     lut_mask => "0080")
2379 port map (
2380 combout => HSYNC_COUNTER_NEXT_1_SQMUXA,
2381 dataa => reset_pin_c,
2382 datab => dly_counter_0,
2383 datac => dly_counter_1,
2384 datad => D_SET_HSYNC_COUNTER_59,
2385         devpor => devpor,
2386         devclrn => devclrn,
2387         clk => GND,
2388         aclr => GND,
2389         sclr => GND,
2390         sload => GND,
2391         ena => VCC,
2392         cin => GND,
2393         inverta => GND,
2394         aload => GND);
2395 COLUMN_COUNTER_NEXT_0_SQMUXA_1_1_Z328: stratix_lcell generic map (
2396     operation_mode => "normal",
2397     output_mode => "comb_only",
2398     synch_mode => "off",
2399      sum_lutc_input => "datac",
2400     lut_mask => "0080")
2401 port map (
2402 combout => COLUMN_COUNTER_NEXT_0_SQMUXA_1_1,
2403 dataa => reset_pin_c,
2404 datab => dly_counter_0,
2405 datac => dly_counter_1,
2406 datad => HSYNC_STATE_20,
2407         devpor => devpor,
2408         devclrn => devclrn,
2409         clk => GND,
2410         aclr => GND,
2411         sclr => GND,
2412         sload => GND,
2413         ena => VCC,
2414         cin => GND,
2415         inverta => GND,
2416         aload => GND);
2417 H_SYNC_1_0_0_0_G1_Z329: stratix_lcell generic map (
2418     operation_mode => "normal",
2419     output_mode => "comb_only",
2420     synch_mode => "off",
2421      sum_lutc_input => "datac",
2422     lut_mask => "ccd8")
2423 port map (
2424 combout => H_SYNC_1_0_0_0_G1,
2425 dataa => HSYNC_STATE_16,
2426 datab => H_SYNC_57,
2427 datac => HSYNC_STATE_17,
2428 datad => UN1_HSYNC_STATE_3_0,
2429         devpor => devpor,
2430         devclrn => devclrn,
2431         clk => GND,
2432         aclr => GND,
2433         sclr => GND,
2434         sload => GND,
2435         ena => VCC,
2436         cin => GND,
2437         inverta => GND,
2438         aload => GND);
2439 V_ENABLE_SIG_1_0_0_0_G0_I_O4_Z330: stratix_lcell generic map (
2440     operation_mode => "normal",
2441     output_mode => "comb_only",
2442     synch_mode => "off",
2443      sum_lutc_input => "datac",
2444     lut_mask => "f1f1")
2445 port map (
2446 combout => V_ENABLE_SIG_1_0_0_0_G0_I_O4,
2447 dataa => HSYNC_STATE_17,
2448 datab => HSYNC_STATE_19,
2449 datac => UN6_DLY_COUNTER_0_X_58,
2450         devpor => devpor,
2451         devclrn => devclrn,
2452         clk => GND,
2453         datad => VCC,
2454         aclr => GND,
2455         sclr => GND,
2456         sload => GND,
2457         ena => VCC,
2458         cin => GND,
2459         inverta => GND,
2460         aload => GND);
2461 HSYNC_FSM_NEXT_UN12_HSYNC_COUNTER_4: stratix_lcell generic map (
2462     operation_mode => "normal",
2463     output_mode => "comb_only",
2464     synch_mode => "off",
2465      sum_lutc_input => "datac",
2466     lut_mask => "0010")
2467 port map (
2468 combout => UN12_HSYNC_COUNTER_4,
2469 dataa => HSYNC_COUNTER_46,
2470 datab => HSYNC_COUNTER_45,
2471 datac => HSYNC_COUNTER_44,
2472 datad => HSYNC_COUNTER_48,
2473         devpor => devpor,
2474         devclrn => devclrn,
2475         clk => GND,
2476         aclr => GND,
2477         sclr => GND,
2478         sload => GND,
2479         ena => VCC,
2480         cin => GND,
2481         inverta => GND,
2482         aload => GND);
2483 HSYNC_FSM_NEXT_UN12_HSYNC_COUNTER_3: stratix_lcell generic map (
2484     operation_mode => "normal",
2485     output_mode => "comb_only",
2486     synch_mode => "off",
2487      sum_lutc_input => "datac",
2488     lut_mask => "0020")
2489 port map (
2490 combout => UN12_HSYNC_COUNTER_3,
2491 dataa => HSYNC_COUNTER_43,
2492 datab => HSYNC_COUNTER_47,
2493 datac => HSYNC_COUNTER_50,
2494 datad => HSYNC_COUNTER_49,
2495         devpor => devpor,
2496         devclrn => devclrn,
2497         clk => GND,
2498         aclr => GND,
2499         sclr => GND,
2500         sload => GND,
2501         ena => VCC,
2502         cin => GND,
2503         inverta => GND,
2504         aload => GND);
2505 HSYNC_FSM_NEXT_UN11_HSYNC_COUNTER_3: stratix_lcell generic map (
2506     operation_mode => "normal",
2507     output_mode => "comb_only",
2508     synch_mode => "off",
2509      sum_lutc_input => "datac",
2510     lut_mask => "0008")
2511 port map (
2512 combout => UN11_HSYNC_COUNTER_3,
2513 dataa => HSYNC_COUNTER_52,
2514 datab => HSYNC_COUNTER_51,
2515 datac => HSYNC_COUNTER_49,
2516 datad => HSYNC_COUNTER_48,
2517         devpor => devpor,
2518         devclrn => devclrn,
2519         clk => GND,
2520         aclr => GND,
2521         sclr => GND,
2522         sload => GND,
2523         ena => VCC,
2524         cin => GND,
2525         inverta => GND,
2526         aload => GND);
2527 HSYNC_FSM_NEXT_UN11_HSYNC_COUNTER_2: stratix_lcell generic map (
2528     operation_mode => "normal",
2529     output_mode => "comb_only",
2530     synch_mode => "off",
2531      sum_lutc_input => "datac",
2532     lut_mask => "0808")
2533 port map (
2534 combout => UN11_HSYNC_COUNTER_2,
2535 dataa => HSYNC_COUNTER_50,
2536 datab => HSYNC_COUNTER_45,
2537 datac => HSYNC_COUNTER_46,
2538         devpor => devpor,
2539         devclrn => devclrn,
2540         clk => GND,
2541         datad => VCC,
2542         aclr => GND,
2543         sclr => GND,
2544         sload => GND,
2545         ena => VCC,
2546         cin => GND,
2547         inverta => GND,
2548         aload => GND);
2549 HSYNC_COUNT_NEXT_UN9_HSYNC_COUNTERLT9_3: stratix_lcell generic map (
2550     operation_mode => "normal",
2551     output_mode => "comb_only",
2552     synch_mode => "off",
2553      sum_lutc_input => "datac",
2554     lut_mask => "7fff")
2555 port map (
2556 combout => UN9_HSYNC_COUNTERLT9_3,
2557 dataa => HSYNC_COUNTER_46,
2558 datab => HSYNC_COUNTER_45,
2559 datac => HSYNC_COUNTER_44,
2560 datad => HSYNC_COUNTER_43,
2561         devpor => devpor,
2562         devclrn => devclrn,
2563         clk => GND,
2564         aclr => GND,
2565         sclr => GND,
2566         sload => GND,
2567         ena => VCC,
2568         cin => GND,
2569         inverta => GND,
2570         aload => GND);
2571 HSYNC_FSM_NEXT_UN13_HSYNC_COUNTER_2: stratix_lcell generic map (
2572     operation_mode => "normal",
2573     output_mode => "comb_only",
2574     synch_mode => "off",
2575      sum_lutc_input => "datac",
2576     lut_mask => "0080")
2577 port map (
2578 combout => UN13_HSYNC_COUNTER_2,
2579 dataa => HSYNC_COUNTER_44,
2580 datab => HSYNC_COUNTER_43,
2581 datac => HSYNC_COUNTER_48,
2582 datad => HSYNC_COUNTER_47,
2583         devpor => devpor,
2584         devclrn => devclrn,
2585         clk => GND,
2586         aclr => GND,
2587         sclr => GND,
2588         sload => GND,
2589         ena => VCC,
2590         cin => GND,
2591         inverta => GND,
2592         aload => GND);
2593 VSYNC_COUNT_NEXT_UN9_VSYNC_COUNTERLT9_6: stratix_lcell generic map (
2594     operation_mode => "normal",
2595     output_mode => "comb_only",
2596     synch_mode => "off",
2597      sum_lutc_input => "datac",
2598     lut_mask => "7fff")
2599 port map (
2600 combout => UN9_VSYNC_COUNTERLT9_6,
2601 dataa => VSYNC_COUNTER_40,
2602 datab => VSYNC_COUNTER_39,
2603 datac => VSYNC_COUNTER_42,
2604 datad => VSYNC_COUNTER_41,
2605         devpor => devpor,
2606         devclrn => devclrn,
2607         clk => GND,
2608         aclr => GND,
2609         sclr => GND,
2610         sload => GND,
2611         ena => VCC,
2612         cin => GND,
2613         inverta => GND,
2614         aload => GND);
2615 VSYNC_COUNT_NEXT_UN9_VSYNC_COUNTERLT9_5: stratix_lcell generic map (
2616     operation_mode => "normal",
2617     output_mode => "comb_only",
2618     synch_mode => "off",
2619      sum_lutc_input => "datac",
2620     lut_mask => "7fff")
2621 port map (
2622 combout => UN9_VSYNC_COUNTERLT9_5,
2623 dataa => VSYNC_COUNTER_34,
2624 datab => VSYNC_COUNTER_33,
2625 datac => VSYNC_COUNTER_36,
2626 datad => VSYNC_COUNTER_35,
2627         devpor => devpor,
2628         devclrn => devclrn,
2629         clk => GND,
2630         aclr => GND,
2631         sclr => GND,
2632         sload => GND,
2633         ena => VCC,
2634         cin => GND,
2635         inverta => GND,
2636         aload => GND);
2637 VSYNC_FSM_NEXT_UN13_VSYNC_COUNTER_3: stratix_lcell generic map (
2638     operation_mode => "normal",
2639     output_mode => "comb_only",
2640     synch_mode => "off",
2641      sum_lutc_input => "datac",
2642     lut_mask => "0001")
2643 port map (
2644 combout => UN13_VSYNC_COUNTER_3,
2645 dataa => VSYNC_COUNTER_36,
2646 datab => VSYNC_COUNTER_35,
2647 datac => VSYNC_COUNTER_34,
2648 datad => VSYNC_COUNTER_33,
2649         devpor => devpor,
2650         devclrn => devclrn,
2651         clk => GND,
2652         aclr => GND,
2653         sclr => GND,
2654         sload => GND,
2655         ena => VCC,
2656         cin => GND,
2657         inverta => GND,
2658         aload => GND);
2659 VSYNC_FSM_NEXT_UN15_VSYNC_COUNTER_3: stratix_lcell generic map (
2660     operation_mode => "normal",
2661     output_mode => "comb_only",
2662     synch_mode => "off",
2663      sum_lutc_input => "datac",
2664     lut_mask => "0008")
2665 port map (
2666 combout => UN15_VSYNC_COUNTER_3,
2667 dataa => VSYNC_COUNTER_39,
2668 datab => VSYNC_COUNTER_33,
2669 datac => VSYNC_COUNTER_42,
2670 datad => VSYNC_COUNTER_40,
2671         devpor => devpor,
2672         devclrn => devclrn,
2673         clk => GND,
2674         aclr => GND,
2675         sclr => GND,
2676         sload => GND,
2677         ena => VCC,
2678         cin => GND,
2679         inverta => GND,
2680         aload => GND);
2681 HSYNC_FSM_NEXT_UN10_HSYNC_COUNTER_4: stratix_lcell generic map (
2682     operation_mode => "normal",
2683     output_mode => "comb_only",
2684     synch_mode => "off",
2685      sum_lutc_input => "datac",
2686     lut_mask => "8000")
2687 port map (
2688 combout => UN10_HSYNC_COUNTER_4,
2689 dataa => HSYNC_COUNTER_48,
2690 datab => HSYNC_COUNTER_46,
2691 datac => HSYNC_COUNTER_51,
2692 datad => HSYNC_COUNTER_49,
2693         devpor => devpor,
2694         devclrn => devclrn,
2695         clk => GND,
2696         aclr => GND,
2697         sclr => GND,
2698         sload => GND,
2699         ena => VCC,
2700         cin => GND,
2701         inverta => GND,
2702         aload => GND);
2703 HSYNC_FSM_NEXT_UN10_HSYNC_COUNTER_3: stratix_lcell generic map (
2704     operation_mode => "normal",
2705     output_mode => "comb_only",
2706     synch_mode => "off",
2707      sum_lutc_input => "datac",
2708     lut_mask => "0101")
2709 port map (
2710 combout => UN10_HSYNC_COUNTER_3,
2711 dataa => HSYNC_COUNTER_52,
2712 datab => HSYNC_COUNTER_45,
2713 datac => HSYNC_COUNTER_50,
2714         devpor => devpor,
2715         devclrn => devclrn,
2716         clk => GND,
2717         datad => VCC,
2718         aclr => GND,
2719         sclr => GND,
2720         sload => GND,
2721         ena => VCC,
2722         cin => GND,
2723         inverta => GND,
2724         aload => GND);
2725 LINE_COUNT_NEXT_UN10_LINE_COUNTER_SIGLT4_2: stratix_lcell generic map (
2726     operation_mode => "normal",
2727     output_mode => "comb_only",
2728     synch_mode => "off",
2729      sum_lutc_input => "datac",
2730     lut_mask => "7f7f")
2731 port map (
2732 combout => UN10_LINE_COUNTER_SIGLT4_2,
2733 dataa => LINE_COUNTER_SIG_3_0,
2734 datab => LINE_COUNTER_SIG_4_0,
2735 datac => LINE_COUNTER_SIG_0_0,
2736         devpor => devpor,
2737         devclrn => devclrn,
2738         clk => GND,
2739         datad => VCC,
2740         aclr => GND,
2741         sclr => GND,
2742         sload => GND,
2743         ena => VCC,
2744         cin => GND,
2745         inverta => GND,
2746         aload => GND);
2747 VSYNC_FSM_NEXT_UN12_VSYNC_COUNTER_6: stratix_lcell generic map (
2748     operation_mode => "normal",
2749     output_mode => "comb_only",
2750     synch_mode => "off",
2751      sum_lutc_input => "datac",
2752     lut_mask => "0001")
2753 port map (
2754 combout => UN12_VSYNC_COUNTER_6,
2755 dataa => VSYNC_COUNTER_35,
2756 datab => VSYNC_COUNTER_34,
2757 datac => VSYNC_COUNTER_37,
2758 datad => VSYNC_COUNTER_36,
2759         devpor => devpor,
2760         devclrn => devclrn,
2761         clk => GND,
2762         aclr => GND,
2763         sclr => GND,
2764         sload => GND,
2765         ena => VCC,
2766         cin => GND,
2767         inverta => GND,
2768         aload => GND);
2769 VSYNC_FSM_NEXT_UN12_VSYNC_COUNTER_7: stratix_lcell generic map (
2770     operation_mode => "normal",
2771     output_mode => "comb_only",
2772     synch_mode => "off",
2773      sum_lutc_input => "datac",
2774     lut_mask => "0001")
2775 port map (
2776 combout => UN12_VSYNC_COUNTER_7,
2777 dataa => VSYNC_COUNTER_39,
2778 datab => VSYNC_COUNTER_38,
2779 datac => VSYNC_COUNTER_41,
2780 datad => VSYNC_COUNTER_40,
2781         devpor => devpor,
2782         devclrn => devclrn,
2783         clk => GND,
2784         aclr => GND,
2785         sclr => GND,
2786         sload => GND,
2787         ena => VCC,
2788         cin => GND,
2789         inverta => GND,
2790         aload => GND);
2791 COLUMN_COUNT_NEXT_UN10_COLUMN_COUNTER_SIGLT6_1: stratix_lcell generic map (
2792     operation_mode => "normal",
2793     output_mode => "comb_only",
2794     synch_mode => "off",
2795      sum_lutc_input => "datac",
2796     lut_mask => "7f7f")
2797 port map (
2798 combout => UN10_COLUMN_COUNTER_SIGLT6_54,
2799 dataa => COLUMN_COUNTER_SIG_23,
2800 datab => COLUMN_COUNTER_SIG_25,
2801 datac => COLUMN_COUNTER_SIG_24,
2802         devpor => devpor,
2803         devclrn => devclrn,
2804         clk => GND,
2805         datad => VCC,
2806         aclr => GND,
2807         sclr => GND,
2808         sload => GND,
2809         ena => VCC,
2810         cin => GND,
2811         inverta => GND,
2812         aload => GND);
2813 HSYNC_FSM_NEXT_UN13_HSYNC_COUNTER_7: stratix_lcell generic map (
2814     operation_mode => "normal",
2815     output_mode => "comb_only",
2816     synch_mode => "off",
2817      sum_lutc_input => "datac",
2818     lut_mask => "8000")
2819 port map (
2820 combout => UN13_HSYNC_COUNTER_7,
2821 dataa => HSYNC_COUNTER_50,
2822 datab => HSYNC_COUNTER_49,
2823 datac => HSYNC_COUNTER_52,
2824 datad => HSYNC_COUNTER_51,
2825         devpor => devpor,
2826         devclrn => devclrn,
2827         clk => GND,
2828         aclr => GND,
2829         sclr => GND,
2830         sload => GND,
2831         ena => VCC,
2832         cin => GND,
2833         inverta => GND,
2834         aload => GND);
2835 HSYNC_FSM_NEXT_UN10_HSYNC_COUNTER_1: stratix_lcell generic map (
2836     operation_mode => "normal",
2837     output_mode => "comb_only",
2838     synch_mode => "off",
2839      sum_lutc_input => "datac",
2840     lut_mask => "0101")
2841 port map (
2842 combout => UN10_HSYNC_COUNTER_1,
2843 dataa => HSYNC_COUNTER_47,
2844 datab => HSYNC_COUNTER_44,
2845 datac => HSYNC_COUNTER_43,
2846         devpor => devpor,
2847         devclrn => devclrn,
2848         clk => GND,
2849         datad => VCC,
2850         aclr => GND,
2851         sclr => GND,
2852         sload => GND,
2853         ena => VCC,
2854         cin => GND,
2855         inverta => GND,
2856         aload => GND);
2857 UN1_HSYNC_STATE_3_0_Z349: stratix_lcell generic map (
2858     operation_mode => "normal",
2859     output_mode => "comb_only",
2860     synch_mode => "off",
2861      sum_lutc_input => "datac",
2862     lut_mask => "eeee")
2863 port map (
2864 combout => UN1_HSYNC_STATE_3_0,
2865 dataa => HSYNC_STATE_21,
2866 datab => HSYNC_STATE_20,
2867         devpor => devpor,
2868         devclrn => devclrn,
2869         clk => GND,
2870         datac => VCC,
2871         datad => VCC,
2872         aclr => GND,
2873         sclr => GND,
2874         sload => GND,
2875         ena => VCC,
2876         cin => GND,
2877         inverta => GND,
2878         aload => GND);
2879 UN1_VSYNC_STATE_2_0_Z350: stratix_lcell generic map (
2880     operation_mode => "normal",
2881     output_mode => "comb_only",
2882     synch_mode => "off",
2883      sum_lutc_input => "datac",
2884     lut_mask => "eeee")
2885 port map (
2886 combout => UN1_VSYNC_STATE_2_0,
2887 dataa => VSYNC_STATE_11,
2888 datab => VSYNC_STATE_14,
2889         devpor => devpor,
2890         devclrn => devclrn,
2891         clk => GND,
2892         datac => VCC,
2893         datad => VCC,
2894         aclr => GND,
2895         sclr => GND,
2896         sload => GND,
2897         ena => VCC,
2898         cin => GND,
2899         inverta => GND,
2900         aload => GND);
2901 D_SET_VSYNC_COUNTER_Z351: stratix_lcell generic map (
2902     operation_mode => "normal",
2903     output_mode => "comb_only",
2904     synch_mode => "off",
2905      sum_lutc_input => "datac",
2906     lut_mask => "eeee")
2907 port map (
2908 combout => D_SET_VSYNC_COUNTER_53,
2909 dataa => VSYNC_STATE_12,
2910 datab => VSYNC_STATE_15,
2911         devpor => devpor,
2912         devclrn => devclrn,
2913         clk => GND,
2914         datac => VCC,
2915         datad => VCC,
2916         aclr => GND,
2917         sclr => GND,
2918         sload => GND,
2919         ena => VCC,
2920         cin => GND,
2921         inverta => GND,
2922         aload => GND);
2923 COLUMN_COUNT_NEXT_UN10_COLUMN_COUNTER_SIGLT6_3: stratix_lcell generic map (
2924     operation_mode => "normal",
2925     output_mode => "comb_only",
2926     synch_mode => "off",
2927      sum_lutc_input => "datac",
2928     lut_mask => "7777")
2929 port map (
2930 combout => UN10_COLUMN_COUNTER_SIGLT6_55,
2931 dataa => COLUMN_COUNTER_SIG_29,
2932 datab => COLUMN_COUNTER_SIG_28,
2933         devpor => devpor,
2934         devclrn => devclrn,
2935         clk => GND,
2936         datac => VCC,
2937         datad => VCC,
2938         aclr => GND,
2939         sclr => GND,
2940         sload => GND,
2941         ena => VCC,
2942         cin => GND,
2943         inverta => GND,
2944         aload => GND);
2945 D_SET_HSYNC_COUNTER_Z353: stratix_lcell generic map (
2946     operation_mode => "normal",
2947     output_mode => "comb_only",
2948     synch_mode => "off",
2949      sum_lutc_input => "datac",
2950     lut_mask => "eeee")
2951 port map (
2952 combout => D_SET_HSYNC_COUNTER_59,
2953 dataa => HSYNC_STATE_22,
2954 datab => HSYNC_STATE_18,
2955         devpor => devpor,
2956         devclrn => devclrn,
2957         clk => GND,
2958         datac => VCC,
2959         datad => VCC,
2960         aclr => GND,
2961         sclr => GND,
2962         sload => GND,
2963         ena => VCC,
2964         cin => GND,
2965         inverta => GND,
2966         aload => GND);
2967 \UN1_LINE_COUNTER_SIG_9_\: stratix_lcell generic map (
2968     operation_mode => "normal",
2969     output_mode => "comb_only",
2970     synch_mode => "off",
2971      sum_lutc_input => "cin",
2972      cin_used => "true",
2973     lut_mask => "6c6c")
2974 port map (
2975 combout => UN1_LINE_COUNTER_SIG_COMBOUT(9),
2976 dataa => LINE_COUNTER_SIG_7_0,
2977 datab => LINE_COUNTER_SIG_8_0,
2978 cin => UN1_LINE_COUNTER_SIG_COUT(7),
2979         devpor => devpor,
2980         devclrn => devclrn,
2981         clk => GND,
2982         datac => VCC,
2983         datad => VCC,
2984         aclr => GND,
2985         sclr => GND,
2986         sload => GND,
2987         ena => VCC,
2988         inverta => GND,
2989         aload => GND);
2990 \UN1_LINE_COUNTER_SIG_8_\: stratix_lcell generic map (
2991     operation_mode => "normal",
2992     output_mode => "comb_only",
2993     synch_mode => "off",
2994      sum_lutc_input => "cin",
2995      cin_used => "true",
2996     lut_mask => "5a5a")
2997 port map (
2998 combout => UN1_LINE_COUNTER_SIG_COMBOUT(8),
2999 dataa => LINE_COUNTER_SIG_7_0,
3000 cin => UN1_LINE_COUNTER_SIG_COUT(6),
3001         devpor => devpor,
3002         devclrn => devclrn,
3003         clk => GND,
3004         datab => VCC,
3005         datac => VCC,
3006         datad => VCC,
3007         aclr => GND,
3008         sclr => GND,
3009         sload => GND,
3010         ena => VCC,
3011         inverta => GND,
3012         aload => GND);
3013 \UN1_LINE_COUNTER_SIG_7_\: stratix_lcell generic map (
3014     operation_mode => "arithmetic",
3015     output_mode => "comb_only",
3016     synch_mode => "off",
3017      sum_lutc_input => "cin",
3018      cin_used => "true",
3019     lut_mask => "6c80")
3020 port map (
3021 combout => UN1_LINE_COUNTER_SIG_COMBOUT(7),
3022 cout => UN1_LINE_COUNTER_SIG_COUT(7),
3023 dataa => LINE_COUNTER_SIG_5_0,
3024 datab => LINE_COUNTER_SIG_6_0,
3025 cin => UN1_LINE_COUNTER_SIG_COUT(5),
3026         devpor => devpor,
3027         devclrn => devclrn,
3028         clk => GND,
3029         datac => VCC,
3030         datad => VCC,
3031         aclr => GND,
3032         sclr => GND,
3033         sload => GND,
3034         ena => VCC,
3035         inverta => GND,
3036         aload => GND);
3037 \UN1_LINE_COUNTER_SIG_6_\: stratix_lcell generic map (
3038     operation_mode => "arithmetic",
3039     output_mode => "comb_only",
3040     synch_mode => "off",
3041      sum_lutc_input => "cin",
3042      cin_used => "true",
3043     lut_mask => "5a80")
3044 port map (
3045 combout => UN1_LINE_COUNTER_SIG_COMBOUT(6),
3046 cout => UN1_LINE_COUNTER_SIG_COUT(6),
3047 dataa => LINE_COUNTER_SIG_5_0,
3048 datab => LINE_COUNTER_SIG_6_0,
3049 cin => UN1_LINE_COUNTER_SIG_COUT(4),
3050         devpor => devpor,
3051         devclrn => devclrn,
3052         clk => GND,
3053         datac => VCC,
3054         datad => VCC,
3055         aclr => GND,
3056         sclr => GND,
3057         sload => GND,
3058         ena => VCC,
3059         inverta => GND,
3060         aload => GND);
3061 \UN1_LINE_COUNTER_SIG_5_\: stratix_lcell generic map (
3062     operation_mode => "arithmetic",
3063     output_mode => "comb_only",
3064     synch_mode => "off",
3065      sum_lutc_input => "cin",
3066      cin_used => "true",
3067     lut_mask => "6c80")
3068 port map (
3069 combout => UN1_LINE_COUNTER_SIG_COMBOUT(5),
3070 cout => UN1_LINE_COUNTER_SIG_COUT(5),
3071 dataa => LINE_COUNTER_SIG_3_0,
3072 datab => LINE_COUNTER_SIG_4_0,
3073 cin => UN1_LINE_COUNTER_SIG_COUT(3),
3074         devpor => devpor,
3075         devclrn => devclrn,
3076         clk => GND,
3077         datac => VCC,
3078         datad => VCC,
3079         aclr => GND,
3080         sclr => GND,
3081         sload => GND,
3082         ena => VCC,
3083         inverta => GND,
3084         aload => GND);
3085 \UN1_LINE_COUNTER_SIG_4_\: stratix_lcell generic map (
3086     operation_mode => "arithmetic",
3087     output_mode => "comb_only",
3088     synch_mode => "off",
3089      sum_lutc_input => "cin",
3090      cin_used => "true",
3091     lut_mask => "5a80")
3092 port map (
3093 combout => UN1_LINE_COUNTER_SIG_COMBOUT(4),
3094 cout => UN1_LINE_COUNTER_SIG_COUT(4),
3095 dataa => LINE_COUNTER_SIG_3_0,
3096 datab => LINE_COUNTER_SIG_4_0,
3097 cin => UN1_LINE_COUNTER_SIG_COUT(2),
3098         devpor => devpor,
3099         devclrn => devclrn,
3100         clk => GND,
3101         datac => VCC,
3102         datad => VCC,
3103         aclr => GND,
3104         sclr => GND,
3105         sload => GND,
3106         ena => VCC,
3107         inverta => GND,
3108         aload => GND);
3109 \UN1_LINE_COUNTER_SIG_3_\: stratix_lcell generic map (
3110     operation_mode => "arithmetic",
3111     output_mode => "comb_only",
3112     synch_mode => "off",
3113      sum_lutc_input => "cin",
3114      cin_used => "true",
3115     lut_mask => "6c80")
3116 port map (
3117 combout => UN1_LINE_COUNTER_SIG_COMBOUT(3),
3118 cout => UN1_LINE_COUNTER_SIG_COUT(3),
3119 dataa => LINE_COUNTER_SIG_1_0,
3120 datab => LINE_COUNTER_SIG_2_0,
3121 cin => UN1_LINE_COUNTER_SIG_COUT(1),
3122         devpor => devpor,
3123         devclrn => devclrn,
3124         clk => GND,
3125         datac => VCC,
3126         datad => VCC,
3127         aclr => GND,
3128         sclr => GND,
3129         sload => GND,
3130         ena => VCC,
3131         inverta => GND,
3132         aload => GND);
3133 \UN1_LINE_COUNTER_SIG_2_\: stratix_lcell generic map (
3134     operation_mode => "arithmetic",
3135     output_mode => "comb_only",
3136     synch_mode => "off",
3137      sum_lutc_input => "cin",
3138      cin_used => "true",
3139     lut_mask => "5a80")
3140 port map (
3141 combout => UN1_LINE_COUNTER_SIG_COMBOUT(2),
3142 cout => UN1_LINE_COUNTER_SIG_COUT(2),
3143 dataa => LINE_COUNTER_SIG_1_0,
3144 datab => LINE_COUNTER_SIG_2_0,
3145 cin => UN1_LINE_COUNTER_SIG_A_COUT(1),
3146         devpor => devpor,
3147         devclrn => devclrn,
3148         clk => GND,
3149         datac => VCC,
3150         datad => VCC,
3151         aclr => GND,
3152         sclr => GND,
3153         sload => GND,
3154         ena => VCC,
3155         inverta => GND,
3156         aload => GND);
3157 \UN1_LINE_COUNTER_SIG_A_1_\: stratix_lcell generic map (
3158     operation_mode => "arithmetic",
3159     output_mode => "comb_only",
3160     synch_mode => "off",
3161      sum_lutc_input => "datac",
3162     lut_mask => "0088")
3163 port map (
3164 cout => UN1_LINE_COUNTER_SIG_A_COUT(1),
3165 dataa => D_SET_HSYNC_COUNTER_59,
3166 datab => LINE_COUNTER_SIG_0_0,
3167         devpor => devpor,
3168         devclrn => devclrn,
3169         clk => GND,
3170         datac => VCC,
3171         datad => VCC,
3172         aclr => GND,
3173         sclr => GND,
3174         sload => GND,
3175         ena => VCC,
3176         cin => GND,
3177         inverta => GND,
3178         aload => GND);
3179 \UN1_LINE_COUNTER_SIG_1_\: stratix_lcell generic map (
3180     operation_mode => "arithmetic",
3181     output_mode => "comb_only",
3182     synch_mode => "off",
3183      sum_lutc_input => "datac",
3184     lut_mask => "6688")
3185 port map (
3186 combout => UN1_LINE_COUNTER_SIG_COMBOUT(1),
3187 cout => UN1_LINE_COUNTER_SIG_COUT(1),
3188 dataa => D_SET_HSYNC_COUNTER_59,
3189 datab => LINE_COUNTER_SIG_0_0,
3190         devpor => devpor,
3191         devclrn => devclrn,
3192         clk => GND,
3193         datac => VCC,
3194         datad => VCC,
3195         aclr => GND,
3196         sclr => GND,
3197         sload => GND,
3198         ena => VCC,
3199         cin => GND,
3200         inverta => GND,
3201         aload => GND);
3202 \UN2_COLUMN_COUNTER_NEXT_9_\: stratix_lcell generic map (
3203     operation_mode => "normal",
3204     output_mode => "comb_only",
3205     synch_mode => "off",
3206      sum_lutc_input => "cin",
3207      cin_used => "true",
3208     lut_mask => "6c6c")
3209 port map (
3210 combout => UN2_COLUMN_COUNTER_NEXT_COMBOUT(9),
3211 dataa => COLUMN_COUNTER_SIG_31,
3212 datab => COLUMN_COUNTER_SIG_32,
3213 cin => UN2_COLUMN_COUNTER_NEXT_COUT(7),
3214         devpor => devpor,
3215         devclrn => devclrn,
3216         clk => GND,
3217         datac => VCC,
3218         datad => VCC,
3219         aclr => GND,
3220         sclr => GND,
3221         sload => GND,
3222         ena => VCC,
3223         inverta => GND,
3224         aload => GND);
3225 \UN2_COLUMN_COUNTER_NEXT_8_\: stratix_lcell generic map (
3226     operation_mode => "normal",
3227     output_mode => "comb_only",
3228     synch_mode => "off",
3229      sum_lutc_input => "cin",
3230      cin_used => "true",
3231     lut_mask => "5a5a")
3232 port map (
3233 combout => UN2_COLUMN_COUNTER_NEXT_COMBOUT(8),
3234 dataa => COLUMN_COUNTER_SIG_31,
3235 cin => UN2_COLUMN_COUNTER_NEXT_COUT(6),
3236         devpor => devpor,
3237         devclrn => devclrn,
3238         clk => GND,
3239         datab => VCC,
3240         datac => VCC,
3241         datad => VCC,
3242         aclr => GND,
3243         sclr => GND,
3244         sload => GND,
3245         ena => VCC,
3246         inverta => GND,
3247         aload => GND);
3248 \UN2_COLUMN_COUNTER_NEXT_7_\: stratix_lcell generic map (
3249     operation_mode => "arithmetic",
3250     output_mode => "comb_only",
3251     synch_mode => "off",
3252      sum_lutc_input => "cin",
3253      cin_used => "true",
3254     lut_mask => "6c80")
3255 port map (
3256 combout => UN2_COLUMN_COUNTER_NEXT_COMBOUT(7),
3257 cout => UN2_COLUMN_COUNTER_NEXT_COUT(7),
3258 dataa => COLUMN_COUNTER_SIG_29,
3259 datab => COLUMN_COUNTER_SIG_30,
3260 cin => UN2_COLUMN_COUNTER_NEXT_COUT(5),
3261         devpor => devpor,
3262         devclrn => devclrn,
3263         clk => GND,
3264         datac => VCC,
3265         datad => VCC,
3266         aclr => GND,
3267         sclr => GND,
3268         sload => GND,
3269         ena => VCC,
3270         inverta => GND,
3271         aload => GND);
3272 \UN2_COLUMN_COUNTER_NEXT_6_\: stratix_lcell generic map (
3273     operation_mode => "arithmetic",
3274     output_mode => "comb_only",
3275     synch_mode => "off",
3276      sum_lutc_input => "cin",
3277      cin_used => "true",
3278     lut_mask => "5a80")
3279 port map (
3280 combout => UN2_COLUMN_COUNTER_NEXT_COMBOUT(6),
3281 cout => UN2_COLUMN_COUNTER_NEXT_COUT(6),
3282 dataa => COLUMN_COUNTER_SIG_29,
3283 datab => COLUMN_COUNTER_SIG_30,
3284 cin => UN2_COLUMN_COUNTER_NEXT_COUT(4),
3285         devpor => devpor,
3286         devclrn => devclrn,
3287         clk => GND,
3288         datac => VCC,
3289         datad => VCC,
3290         aclr => GND,
3291         sclr => GND,
3292         sload => GND,
3293         ena => VCC,
3294         inverta => GND,
3295         aload => GND);
3296 \UN2_COLUMN_COUNTER_NEXT_5_\: stratix_lcell generic map (
3297     operation_mode => "arithmetic",
3298     output_mode => "comb_only",
3299     synch_mode => "off",
3300      sum_lutc_input => "cin",
3301      cin_used => "true",
3302     lut_mask => "6c80")
3303 port map (
3304 combout => UN2_COLUMN_COUNTER_NEXT_COMBOUT(5),
3305 cout => UN2_COLUMN_COUNTER_NEXT_COUT(5),
3306 dataa => COLUMN_COUNTER_SIG_27,
3307 datab => COLUMN_COUNTER_SIG_28,
3308 cin => UN2_COLUMN_COUNTER_NEXT_COUT(3),
3309         devpor => devpor,
3310         devclrn => devclrn,
3311         clk => GND,
3312         datac => VCC,
3313         datad => VCC,
3314         aclr => GND,
3315         sclr => GND,
3316         sload => GND,
3317         ena => VCC,
3318         inverta => GND,
3319         aload => GND);
3320 \UN2_COLUMN_COUNTER_NEXT_4_\: stratix_lcell generic map (
3321     operation_mode => "arithmetic",
3322     output_mode => "comb_only",
3323     synch_mode => "off",
3324      sum_lutc_input => "cin",
3325      cin_used => "true",
3326     lut_mask => "5a80")
3327 port map (
3328 combout => UN2_COLUMN_COUNTER_NEXT_COMBOUT(4),
3329 cout => UN2_COLUMN_COUNTER_NEXT_COUT(4),
3330 dataa => COLUMN_COUNTER_SIG_27,
3331 datab => COLUMN_COUNTER_SIG_28,
3332 cin => UN2_COLUMN_COUNTER_NEXT_COUT(2),
3333         devpor => devpor,
3334         devclrn => devclrn,
3335         clk => GND,
3336         datac => VCC,
3337         datad => VCC,
3338         aclr => GND,
3339         sclr => GND,
3340         sload => GND,
3341         ena => VCC,
3342         inverta => GND,
3343         aload => GND);
3344 \UN2_COLUMN_COUNTER_NEXT_3_\: stratix_lcell generic map (
3345     operation_mode => "arithmetic",
3346     output_mode => "comb_only",
3347     synch_mode => "off",
3348      sum_lutc_input => "cin",
3349      cin_used => "true",
3350     lut_mask => "6c80")
3351 port map (
3352 combout => UN2_COLUMN_COUNTER_NEXT_COMBOUT(3),
3353 cout => UN2_COLUMN_COUNTER_NEXT_COUT(3),
3354 dataa => COLUMN_COUNTER_SIG_25,
3355 datab => COLUMN_COUNTER_SIG_26,
3356 cin => UN2_COLUMN_COUNTER_NEXT_COUT(1),
3357         devpor => devpor,
3358         devclrn => devclrn,
3359         clk => GND,
3360         datac => VCC,
3361         datad => VCC,
3362         aclr => GND,
3363         sclr => GND,
3364         sload => GND,
3365         ena => VCC,
3366         inverta => GND,
3367         aload => GND);
3368 \UN2_COLUMN_COUNTER_NEXT_2_\: stratix_lcell generic map (
3369     operation_mode => "arithmetic",
3370     output_mode => "comb_only",
3371     synch_mode => "off",
3372      sum_lutc_input => "cin",
3373      cin_used => "true",
3374     lut_mask => "5a80")
3375 port map (
3376 combout => UN2_COLUMN_COUNTER_NEXT_COMBOUT(2),
3377 cout => UN2_COLUMN_COUNTER_NEXT_COUT(2),
3378 dataa => COLUMN_COUNTER_SIG_25,
3379 datab => COLUMN_COUNTER_SIG_26,
3380 cin => UN2_COLUMN_COUNTER_NEXT_COUT(0),
3381         devpor => devpor,
3382         devclrn => devclrn,
3383         clk => GND,
3384         datac => VCC,
3385         datad => VCC,
3386         aclr => GND,
3387         sclr => GND,
3388         sload => GND,
3389         ena => VCC,
3390         inverta => GND,
3391         aload => GND);
3392 \UN2_COLUMN_COUNTER_NEXT_1_\: stratix_lcell generic map (
3393     operation_mode => "arithmetic",
3394     output_mode => "comb_only",
3395     synch_mode => "off",
3396      sum_lutc_input => "datac",
3397     lut_mask => "6688")
3398 port map (
3399 combout => UN2_COLUMN_COUNTER_NEXT_COMBOUT(1),
3400 cout => UN2_COLUMN_COUNTER_NEXT_COUT(1),
3401 dataa => COLUMN_COUNTER_SIG_23,
3402 datab => COLUMN_COUNTER_SIG_24,
3403         devpor => devpor,
3404         devclrn => devclrn,
3405         clk => GND,
3406         datac => VCC,
3407         datad => VCC,
3408         aclr => GND,
3409         sclr => GND,
3410         sload => GND,
3411         ena => VCC,
3412         cin => GND,
3413         inverta => GND,
3414         aload => GND);
3415 \UN2_COLUMN_COUNTER_NEXT_0_\: stratix_lcell generic map (
3416     operation_mode => "arithmetic",
3417     output_mode => "comb_only",
3418     synch_mode => "off",
3419      sum_lutc_input => "datac",
3420     lut_mask => "5588")
3421 port map (
3422 cout => UN2_COLUMN_COUNTER_NEXT_COUT(0),
3423 dataa => COLUMN_COUNTER_SIG_23,
3424 datab => COLUMN_COUNTER_SIG_24,
3425         devpor => devpor,
3426         devclrn => devclrn,
3427         clk => GND,
3428         datac => VCC,
3429         datad => VCC,
3430         aclr => GND,
3431         sclr => GND,
3432         sload => GND,
3433         ena => VCC,
3434         cin => GND,
3435         inverta => GND,
3436         aload => GND);
3437 VCC <= '1';
3438 GND <= '0';
3439 LINE_COUNTER_NEXT_0_SQMUXA_1_1_I <= not LINE_COUNTER_NEXT_0_SQMUXA_1_1;
3440 COLUMN_COUNTER_NEXT_0_SQMUXA_1_1_I <= not COLUMN_COUNTER_NEXT_0_SQMUXA_1_1;
3441 G_16_I_I <= not G_16_I;
3442 UN9_VSYNC_COUNTERLT9_I <= not UN9_VSYNC_COUNTERLT9;
3443 G_2_I_I <= not G_2_I;
3444 UN9_HSYNC_COUNTERLT9_I <= not UN9_HSYNC_COUNTERLT9;
3445 line_counter_sig_0 <= LINE_COUNTER_SIG_0_0;
3446 line_counter_sig_1 <= LINE_COUNTER_SIG_1_0;
3447 line_counter_sig_2 <= LINE_COUNTER_SIG_2_0;
3448 line_counter_sig_3 <= LINE_COUNTER_SIG_3_0;
3449 line_counter_sig_4 <= LINE_COUNTER_SIG_4_0;
3450 line_counter_sig_5 <= LINE_COUNTER_SIG_5_0;
3451 line_counter_sig_6 <= LINE_COUNTER_SIG_6_0;
3452 line_counter_sig_7 <= LINE_COUNTER_SIG_7_0;
3453 line_counter_sig_8 <= LINE_COUNTER_SIG_8_0;
3454 vsync_state_2 <= VSYNC_STATE_9;
3455 vsync_state_5 <= VSYNC_STATE_10;
3456 vsync_state_3 <= VSYNC_STATE_11;
3457 vsync_state_6 <= VSYNC_STATE_12;
3458 vsync_state_4 <= VSYNC_STATE_13;
3459 vsync_state_1 <= VSYNC_STATE_14;
3460 vsync_state_0 <= VSYNC_STATE_15;
3461 hsync_state_2 <= HSYNC_STATE_16;
3462 hsync_state_4 <= HSYNC_STATE_17;
3463 hsync_state_0 <= HSYNC_STATE_18;
3464 hsync_state_5 <= HSYNC_STATE_19;
3465 hsync_state_1 <= HSYNC_STATE_20;
3466 hsync_state_3 <= HSYNC_STATE_21;
3467 hsync_state_6 <= HSYNC_STATE_22;
3468 column_counter_sig_0 <= COLUMN_COUNTER_SIG_23;
3469 column_counter_sig_1 <= COLUMN_COUNTER_SIG_24;
3470 column_counter_sig_2 <= COLUMN_COUNTER_SIG_25;
3471 column_counter_sig_3 <= COLUMN_COUNTER_SIG_26;
3472 column_counter_sig_4 <= COLUMN_COUNTER_SIG_27;
3473 column_counter_sig_5 <= COLUMN_COUNTER_SIG_28;
3474 column_counter_sig_6 <= COLUMN_COUNTER_SIG_29;
3475 column_counter_sig_7 <= COLUMN_COUNTER_SIG_30;
3476 column_counter_sig_8 <= COLUMN_COUNTER_SIG_31;
3477 column_counter_sig_9 <= COLUMN_COUNTER_SIG_32;
3478 vsync_counter_9 <= VSYNC_COUNTER_33;
3479 vsync_counter_8 <= VSYNC_COUNTER_34;
3480 vsync_counter_7 <= VSYNC_COUNTER_35;
3481 vsync_counter_6 <= VSYNC_COUNTER_36;
3482 vsync_counter_5 <= VSYNC_COUNTER_37;
3483 vsync_counter_4 <= VSYNC_COUNTER_38;
3484 vsync_counter_3 <= VSYNC_COUNTER_39;
3485 vsync_counter_2 <= VSYNC_COUNTER_40;
3486 vsync_counter_1 <= VSYNC_COUNTER_41;
3487 vsync_counter_0 <= VSYNC_COUNTER_42;
3488 hsync_counter_9 <= HSYNC_COUNTER_43;
3489 hsync_counter_8 <= HSYNC_COUNTER_44;
3490 hsync_counter_7 <= HSYNC_COUNTER_45;
3491 hsync_counter_6 <= HSYNC_COUNTER_46;
3492 hsync_counter_5 <= HSYNC_COUNTER_47;
3493 hsync_counter_4 <= HSYNC_COUNTER_48;
3494 hsync_counter_3 <= HSYNC_COUNTER_49;
3495 hsync_counter_2 <= HSYNC_COUNTER_50;
3496 hsync_counter_1 <= HSYNC_COUNTER_51;
3497 hsync_counter_0 <= HSYNC_COUNTER_52;
3498 d_set_vsync_counter <= D_SET_VSYNC_COUNTER_53;
3499 un10_column_counter_siglt6_1 <= UN10_COLUMN_COUNTER_SIGLT6_54;
3500 un10_column_counter_siglt6_3 <= UN10_COLUMN_COUNTER_SIGLT6_55;
3501 v_sync <= V_SYNC_56;
3502 h_sync <= H_SYNC_57;
3503 un6_dly_counter_0_x <= UN6_DLY_COUNTER_0_X_58;
3504 d_set_hsync_counter <= D_SET_HSYNC_COUNTER_59;
3505 end beh;
3506
3507 --
3508 library ieee, stratix;
3509 use ieee.std_logic_1164.all;
3510 use ieee.numeric_std.all;
3511 library synplify;
3512 use synplify.components.all;
3513 use stratix.stratix_components.all;
3514
3515 entity vga is
3516 port(
3517 clk_pin :  in std_logic;
3518 reset_pin :  in std_logic;
3519 r0_pin :  out std_logic;
3520 r1_pin :  out std_logic;
3521 r2_pin :  out std_logic;
3522 g0_pin :  out std_logic;
3523 g1_pin :  out std_logic;
3524 g2_pin :  out std_logic;
3525 b0_pin :  out std_logic;
3526 b1_pin :  out std_logic;
3527 hsync_pin :  out std_logic;
3528 vsync_pin :  out std_logic;
3529 seven_seg_pin : out std_logic_vector(13 downto 0);
3530 d_hsync :  out std_logic;
3531 d_vsync :  out std_logic;
3532 d_column_counter : out std_logic_vector(9 downto 0);
3533 d_line_counter : out std_logic_vector(8 downto 0);
3534 d_set_column_counter :  out std_logic;
3535 d_set_line_counter :  out std_logic;
3536 d_hsync_counter : out std_logic_vector(9 downto 0);
3537 d_vsync_counter : out std_logic_vector(9 downto 0);
3538 d_set_hsync_counter :  out std_logic;
3539 d_set_vsync_counter :  out std_logic;
3540 d_h_enable :  out std_logic;
3541 d_v_enable :  out std_logic;
3542 d_r :  out std_logic;
3543 d_g :  out std_logic;
3544 d_b :  out std_logic;
3545 d_hsync_state : out std_logic_vector(0 to 6);
3546 d_vsync_state : out std_logic_vector(0 to 6);
3547 d_state_clk :  out std_logic);
3548 end vga;
3549
3550 architecture beh of vga is
3551 signal devclrn : std_logic := '1';
3552 signal devpor : std_logic := '1';
3553 signal devoe : std_logic := '0';
3554 signal DLY_COUNTER : std_logic_vector(1 downto 0);
3555 signal \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\ : std_logic_vector(9 downto 0);
3556 signal \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\ : std_logic_vector(8 downto 0);
3557 signal \VGA_DRIVER_UNIT.HSYNC_COUNTER\ : std_logic_vector(9 downto 0);
3558 signal \VGA_DRIVER_UNIT.VSYNC_COUNTER\ : std_logic_vector(9 downto 0);
3559 signal \VGA_DRIVER_UNIT.HSYNC_STATE\ : std_logic_vector(6 downto 0);
3560 signal \VGA_DRIVER_UNIT.VSYNC_STATE\ : std_logic_vector(6 downto 0);
3561 signal SEVEN_SEG_PINZ : std_logic_vector(13 downto 0);
3562 signal D_COLUMN_COUNTERZ : std_logic_vector(9 downto 0);
3563 signal D_LINE_COUNTERZ : std_logic_vector(8 downto 0);
3564 signal D_HSYNC_COUNTERZ : std_logic_vector(9 downto 0);
3565 signal D_VSYNC_COUNTERZ : std_logic_vector(9 downto 0);
3566 signal D_HSYNC_STATEZ : std_logic_vector(6 downto 0);
3567 signal D_VSYNC_STATEZ : std_logic_vector(6 downto 0);
3568 signal VCC : std_logic ;
3569 signal GND : std_logic ;
3570 signal \VGA_DRIVER_UNIT.COLUMN_COUNT_NEXT.UN10_COLUMN_COUNTER_SIGLT6_1\ : std_logic ;
3571 signal \VGA_DRIVER_UNIT.COLUMN_COUNT_NEXT.UN10_COLUMN_COUNTER_SIGLT6_3\ : std_logic ;
3572 signal \DELAY_RESET_NEXT.UN6_DLY_COUNTER_0_X\ : std_logic ;
3573 signal \VGA_DRIVER_UNIT.H_SYNC\ : std_logic ;
3574 signal \VGA_DRIVER_UNIT.V_SYNC\ : std_logic ;
3575 signal \VGA_DRIVER_UNIT.D_SET_HSYNC_COUNTER\ : std_logic ;
3576 signal \VGA_DRIVER_UNIT.D_SET_VSYNC_COUNTER\ : std_logic ;
3577 signal \VGA_DRIVER_UNIT.H_ENABLE_SIG\ : std_logic ;
3578 signal \VGA_DRIVER_UNIT.V_ENABLE_SIG\ : std_logic ;
3579 signal \VGA_CONTROL_UNIT.R\ : std_logic ;
3580 signal \VGA_CONTROL_UNIT.G\ : std_logic ;
3581 signal \VGA_CONTROL_UNIT.B\ : std_logic ;
3582 signal G_49 : std_logic ;
3583 signal CLK_PIN_C : std_logic ;
3584 signal RESET_PIN_C : std_logic ;
3585 signal CLK_PIN_INTERNAL : std_logic ;
3586 signal RESET_PIN_INTERNAL : std_logic ;
3587 signal N_1 : std_logic ;
3588 signal N_2 : std_logic ;
3589 signal N_60_0 : std_logic ;
3590 signal N_61_0 : std_logic ;
3591 signal N_62_0 : std_logic ;
3592 signal N_63_0 : std_logic ;
3593 signal N_64_0 : std_logic ;
3594 signal N_65_0 : std_logic ;
3595 signal N_66_0 : std_logic ;
3596 signal N_67_0 : std_logic ;
3597 signal N_68_0 : std_logic ;
3598 signal N_69_0 : std_logic ;
3599 signal N_70_0 : std_logic ;
3600 signal N_71_0 : std_logic ;
3601 signal N_72_0 : std_logic ;
3602 signal N_73_0 : std_logic ;
3603 signal N_74_0 : std_logic ;
3604 signal N_75_0 : std_logic ;
3605 signal N_76_0 : std_logic ;
3606 signal N_77_0 : std_logic ;
3607 signal N_78_0 : std_logic ;
3608 signal N_79_0 : std_logic ;
3609 signal N_80_0 : std_logic ;
3610 signal N_81_0 : std_logic ;
3611 signal N_82_0 : std_logic ;
3612 signal N_83_0 : std_logic ;
3613 signal N_84_0 : std_logic ;
3614 signal N_85_0 : std_logic ;
3615 signal N_86_0 : std_logic ;
3616 signal N_87_0 : std_logic ;
3617 signal N_88_0 : std_logic ;
3618 signal N_89_0 : std_logic ;
3619 signal N_90_0 : std_logic ;
3620 signal N_91_0 : std_logic ;
3621 signal N_92 : std_logic ;
3622 signal N_93 : std_logic ;
3623 signal N_94 : std_logic ;
3624 signal N_95 : std_logic ;
3625 signal N_96 : std_logic ;
3626 signal N_97 : std_logic ;
3627 signal N_98 : std_logic ;
3628 signal N_99 : std_logic ;
3629 signal N_100 : std_logic ;
3630 signal N_101 : std_logic ;
3631 signal N_102 : std_logic ;
3632 signal N_103 : std_logic ;
3633 signal N_104 : std_logic ;
3634 signal N_105 : std_logic ;
3635 signal N_106 : std_logic ;
3636 signal N_107 : std_logic ;
3637 signal N_108 : std_logic ;
3638 signal N_109 : std_logic ;
3639 signal N_110 : std_logic ;
3640 signal N_111 : std_logic ;
3641 signal N_112 : std_logic ;
3642 signal N_113 : std_logic ;
3643 signal N_114 : std_logic ;
3644 signal N_115 : std_logic ;
3645 signal N_116 : std_logic ;
3646 signal N_117 : std_logic ;
3647 signal N_118 : std_logic ;
3648 signal N_119 : std_logic ;
3649 signal N_120 : std_logic ;
3650 signal N_121 : std_logic ;
3651 signal N_122 : std_logic ;
3652 signal N_123 : std_logic ;
3653 signal N_124 : std_logic ;
3654 signal N_125 : std_logic ;
3655 signal N_126 : std_logic ;
3656 signal N_127 : std_logic ;
3657 signal N_128 : std_logic ;
3658 signal N_129 : std_logic ;
3659 signal N_130 : std_logic ;
3660 signal N_131 : std_logic ;
3661 signal N_132 : std_logic ;
3662 signal N_133 : std_logic ;
3663 signal N_134 : std_logic ;
3664 signal N_135 : std_logic ;
3665 signal N_136 : std_logic ;
3666 signal N_137 : std_logic ;
3667 signal N_138 : std_logic ;
3668 signal N_139 : std_logic ;
3669 signal N_140 : std_logic ;
3670 signal N_141 : std_logic ;
3671 signal N_142 : std_logic ;
3672 signal N_143 : std_logic ;
3673 signal N_144 : std_logic ;
3674 signal N_145 : std_logic ;
3675 signal N_146 : std_logic ;
3676 signal N_147 : std_logic ;
3677 signal N_148 : std_logic ;
3678 signal R0_PINZ : std_logic ;
3679 signal R1_PINZ : std_logic ;
3680 signal R2_PINZ : std_logic ;
3681 signal G0_PINZ : std_logic ;
3682 signal G1_PINZ : std_logic ;
3683 signal G2_PINZ : std_logic ;
3684 signal B0_PINZ : std_logic ;
3685 signal B1_PINZ : std_logic ;
3686 signal HSYNC_PINZ : std_logic ;
3687 signal VSYNC_PINZ : std_logic ;
3688 signal D_HSYNCZ : std_logic ;
3689 signal D_VSYNCZ : std_logic ;
3690 signal D_SET_COLUMN_COUNTERZ : std_logic ;
3691 signal D_SET_LINE_COUNTERZ : std_logic ;
3692 signal D_SET_HSYNC_COUNTERZ : std_logic ;
3693 signal D_SET_VSYNC_COUNTERZ : std_logic ;
3694 signal D_H_ENABLEZ : std_logic ;
3695 signal D_V_ENABLEZ : std_logic ;
3696 signal D_RZ : std_logic ;
3697 signal D_GZ : std_logic ;
3698 signal D_BZ : std_logic ;
3699 signal D_STATE_CLKZ : std_logic ;
3700 component vga_driver
3701 port(
3702   line_counter_sig_0 :  out std_logic;
3703   line_counter_sig_1 :  out std_logic;
3704   line_counter_sig_2 :  out std_logic;
3705   line_counter_sig_3 :  out std_logic;
3706   line_counter_sig_4 :  out std_logic;
3707   line_counter_sig_5 :  out std_logic;
3708   line_counter_sig_6 :  out std_logic;
3709   line_counter_sig_7 :  out std_logic;
3710   line_counter_sig_8 :  out std_logic;
3711   dly_counter_1 :  in std_logic;
3712   dly_counter_0 :  in std_logic;
3713   vsync_state_2 :  out std_logic;
3714   vsync_state_5 :  out std_logic;
3715   vsync_state_3 :  out std_logic;
3716   vsync_state_6 :  out std_logic;
3717   vsync_state_4 :  out std_logic;
3718   vsync_state_1 :  out std_logic;
3719   vsync_state_0 :  out std_logic;
3720   hsync_state_2 :  out std_logic;
3721   hsync_state_4 :  out std_logic;
3722   hsync_state_0 :  out std_logic;
3723   hsync_state_5 :  out std_logic;
3724   hsync_state_1 :  out std_logic;
3725   hsync_state_3 :  out std_logic;
3726   hsync_state_6 :  out std_logic;
3727   column_counter_sig_0 :  out std_logic;
3728   column_counter_sig_1 :  out std_logic;
3729   column_counter_sig_2 :  out std_logic;
3730   column_counter_sig_3 :  out std_logic;
3731   column_counter_sig_4 :  out std_logic;
3732   column_counter_sig_5 :  out std_logic;
3733   column_counter_sig_6 :  out std_logic;
3734   column_counter_sig_7 :  out std_logic;
3735   column_counter_sig_8 :  out std_logic;
3736   column_counter_sig_9 :  out std_logic;
3737   vsync_counter_9 :  out std_logic;
3738   vsync_counter_8 :  out std_logic;
3739   vsync_counter_7 :  out std_logic;
3740   vsync_counter_6 :  out std_logic;
3741   vsync_counter_5 :  out std_logic;
3742   vsync_counter_4 :  out std_logic;
3743   vsync_counter_3 :  out std_logic;
3744   vsync_counter_2 :  out std_logic;
3745   vsync_counter_1 :  out std_logic;
3746   vsync_counter_0 :  out std_logic;
3747   hsync_counter_9 :  out std_logic;
3748   hsync_counter_8 :  out std_logic;
3749   hsync_counter_7 :  out std_logic;
3750   hsync_counter_6 :  out std_logic;
3751   hsync_counter_5 :  out std_logic;
3752   hsync_counter_4 :  out std_logic;
3753   hsync_counter_3 :  out std_logic;
3754   hsync_counter_2 :  out std_logic;
3755   hsync_counter_1 :  out std_logic;
3756   hsync_counter_0 :  out std_logic;
3757   d_set_vsync_counter :  out std_logic;
3758   un10_column_counter_siglt6_1 :  out std_logic;
3759   un10_column_counter_siglt6_3 :  out std_logic;
3760   v_sync :  out std_logic;
3761   h_sync :  out std_logic;
3762   h_enable_sig :  out std_logic;
3763   v_enable_sig :  out std_logic;
3764   reset_pin_c :  in std_logic;
3765   un6_dly_counter_0_x :  out std_logic;
3766   d_set_hsync_counter :  out std_logic;
3767   clk_pin_c :  in std_logic  );
3768 end component;
3769 component vga_control
3770 port(
3771   column_counter_sig_1 :  in std_logic;
3772   column_counter_sig_7 :  in std_logic;
3773   column_counter_sig_2 :  in std_logic;
3774   column_counter_sig_0 :  in std_logic;
3775   column_counter_sig_4 :  in std_logic;
3776   column_counter_sig_3 :  in std_logic;
3777   column_counter_sig_5 :  in std_logic;
3778   column_counter_sig_6 :  in std_logic;
3779   h_enable_sig :  in std_logic;
3780   v_enable_sig :  in std_logic;
3781   un10_column_counter_siglt6_1 :  in std_logic;
3782   g :  out std_logic;
3783   un10_column_counter_siglt6_3 :  in std_logic;
3784   r :  out std_logic;
3785   un6_dly_counter_0_x :  in std_logic;
3786   clk_pin_c :  in std_logic;
3787   b :  out std_logic  );
3788 end component;
3789 begin
3790 VCC <= '1';
3791 GND <= '0';
3792 \DLY_COUNTER_1_\: stratix_lcell generic map (
3793     operation_mode => "normal",
3794     output_mode => "reg_only",
3795     synch_mode => "off",
3796      sum_lutc_input => "datac",
3797     lut_mask => "a8a8")
3798 port map (
3799 regout => DLY_COUNTER(1),
3800 clk => CLK_PIN_C,
3801 dataa => RESET_PIN_C,
3802 datab => DLY_COUNTER(0),
3803 datac => DLY_COUNTER(1),
3804         devpor => devpor,
3805         devclrn => devclrn,
3806         datad => VCC,
3807         aclr => GND,
3808         sclr => GND,
3809         sload => GND,
3810         ena => VCC,
3811         cin => GND,
3812         inverta => GND,
3813         aload => GND);
3814 \DLY_COUNTER_0_\: stratix_lcell generic map (
3815     operation_mode => "normal",
3816     output_mode => "reg_only",
3817     synch_mode => "off",
3818      sum_lutc_input => "datac",
3819     lut_mask => "a2a2")
3820 port map (
3821 regout => DLY_COUNTER(0),
3822 clk => CLK_PIN_C,
3823 dataa => RESET_PIN_C,
3824 datab => DLY_COUNTER(0),
3825 datac => DLY_COUNTER(1),
3826         devpor => devpor,
3827         devclrn => devclrn,
3828         datad => VCC,
3829         aclr => GND,
3830         sclr => GND,
3831         sload => GND,
3832         ena => VCC,
3833         cin => GND,
3834         inverta => GND,
3835         aload => GND);
3836 RESET_PIN_IN: stratix_io generic map (
3837     operation_mode => "input"
3838     )
3839 port map (
3840 padio => N_2,
3841 combout => RESET_PIN_C,
3842 oe => GND,
3843         devpor => devpor,
3844         devclrn => devclrn,
3845         devoe => devoe,
3846         outclkena => VCC,
3847         inclkena => VCC,
3848         areset => GND,
3849         sreset => GND);
3850 CLK_PIN_IN: stratix_io generic map (
3851     operation_mode => "input"
3852     )
3853 port map (
3854 padio => N_1,
3855 combout => CLK_PIN_C,
3856 oe => GND,
3857         devpor => devpor,
3858         devclrn => devclrn,
3859         devoe => devoe,
3860         outclkena => VCC,
3861         inclkena => VCC,
3862         areset => GND,
3863         sreset => GND);
3864 D_STATE_CLK_OUT: stratix_io generic map (
3865     operation_mode => "output"
3866     )
3867 port map (
3868 padio => D_STATE_CLKZ,
3869 datain => G_49,
3870 oe => VCC,
3871         devpor => devpor,
3872         devclrn => devclrn,
3873         devoe => devoe,
3874         outclkena => VCC,
3875         inclkena => VCC,
3876         areset => GND,
3877         sreset => GND);
3878 \D_VSYNC_STATE_OUT_0_\: stratix_io generic map (
3879     operation_mode => "output"
3880     )
3881 port map (
3882 padio => D_VSYNC_STATEZ(0),
3883 datain => \VGA_DRIVER_UNIT.VSYNC_STATE\(0),
3884 oe => VCC,
3885         devpor => devpor,
3886         devclrn => devclrn,
3887         devoe => devoe,
3888         outclkena => VCC,
3889         inclkena => VCC,
3890         areset => GND,
3891         sreset => GND);
3892 \D_VSYNC_STATE_OUT_1_\: stratix_io generic map (
3893     operation_mode => "output"
3894     )
3895 port map (
3896 padio => D_VSYNC_STATEZ(1),
3897 datain => \VGA_DRIVER_UNIT.VSYNC_STATE\(1),
3898 oe => VCC,
3899         devpor => devpor,
3900         devclrn => devclrn,
3901         devoe => devoe,
3902         outclkena => VCC,
3903         inclkena => VCC,
3904         areset => GND,
3905         sreset => GND);
3906 \D_VSYNC_STATE_OUT_2_\: stratix_io generic map (
3907     operation_mode => "output"
3908     )
3909 port map (
3910 padio => D_VSYNC_STATEZ(2),
3911 datain => \VGA_DRIVER_UNIT.VSYNC_STATE\(2),
3912 oe => VCC,
3913         devpor => devpor,
3914         devclrn => devclrn,
3915         devoe => devoe,
3916         outclkena => VCC,
3917         inclkena => VCC,
3918         areset => GND,
3919         sreset => GND);
3920 \D_VSYNC_STATE_OUT_3_\: stratix_io generic map (
3921     operation_mode => "output"
3922     )
3923 port map (
3924 padio => D_VSYNC_STATEZ(3),
3925 datain => \VGA_DRIVER_UNIT.VSYNC_STATE\(3),
3926 oe => VCC,
3927         devpor => devpor,
3928         devclrn => devclrn,
3929         devoe => devoe,
3930         outclkena => VCC,
3931         inclkena => VCC,
3932         areset => GND,
3933         sreset => GND);
3934 \D_VSYNC_STATE_OUT_4_\: stratix_io generic map (
3935     operation_mode => "output"
3936     )
3937 port map (
3938 padio => D_VSYNC_STATEZ(4),
3939 datain => \VGA_DRIVER_UNIT.VSYNC_STATE\(4),
3940 oe => VCC,
3941         devpor => devpor,
3942         devclrn => devclrn,
3943         devoe => devoe,
3944         outclkena => VCC,
3945         inclkena => VCC,
3946         areset => GND,
3947         sreset => GND);
3948 \D_VSYNC_STATE_OUT_5_\: stratix_io generic map (
3949     operation_mode => "output"
3950     )
3951 port map (
3952 padio => D_VSYNC_STATEZ(5),
3953 datain => \VGA_DRIVER_UNIT.VSYNC_STATE\(5),
3954 oe => VCC,
3955         devpor => devpor,
3956         devclrn => devclrn,
3957         devoe => devoe,
3958         outclkena => VCC,
3959         inclkena => VCC,
3960         areset => GND,
3961         sreset => GND);
3962 \D_VSYNC_STATE_OUT_6_\: stratix_io generic map (
3963     operation_mode => "output"
3964     )
3965 port map (
3966 padio => D_VSYNC_STATEZ(6),
3967 datain => \VGA_DRIVER_UNIT.VSYNC_STATE\(6),
3968 oe => VCC,
3969         devpor => devpor,
3970         devclrn => devclrn,
3971         devoe => devoe,
3972         outclkena => VCC,
3973         inclkena => VCC,
3974         areset => GND,
3975         sreset => GND);
3976 \D_HSYNC_STATE_OUT_0_\: stratix_io generic map (
3977     operation_mode => "output"
3978     )
3979 port map (
3980 padio => D_HSYNC_STATEZ(0),
3981 datain => \VGA_DRIVER_UNIT.HSYNC_STATE\(0),
3982 oe => VCC,
3983         devpor => devpor,
3984         devclrn => devclrn,
3985         devoe => devoe,
3986         outclkena => VCC,
3987         inclkena => VCC,
3988         areset => GND,
3989         sreset => GND);
3990 \D_HSYNC_STATE_OUT_1_\: stratix_io generic map (
3991     operation_mode => "output"
3992     )
3993 port map (
3994 padio => D_HSYNC_STATEZ(1),
3995 datain => \VGA_DRIVER_UNIT.HSYNC_STATE\(1),
3996 oe => VCC,
3997         devpor => devpor,
3998         devclrn => devclrn,
3999         devoe => devoe,
4000         outclkena => VCC,
4001         inclkena => VCC,
4002         areset => GND,
4003         sreset => GND);
4004 \D_HSYNC_STATE_OUT_2_\: stratix_io generic map (
4005     operation_mode => "output"
4006     )
4007 port map (
4008 padio => D_HSYNC_STATEZ(2),
4009 datain => \VGA_DRIVER_UNIT.HSYNC_STATE\(2),
4010 oe => VCC,
4011         devpor => devpor,
4012         devclrn => devclrn,
4013         devoe => devoe,
4014         outclkena => VCC,
4015         inclkena => VCC,
4016         areset => GND,
4017         sreset => GND);
4018 \D_HSYNC_STATE_OUT_3_\: stratix_io generic map (
4019     operation_mode => "output"
4020     )
4021 port map (
4022 padio => D_HSYNC_STATEZ(3),
4023 datain => \VGA_DRIVER_UNIT.HSYNC_STATE\(3),
4024 oe => VCC,
4025         devpor => devpor,
4026         devclrn => devclrn,
4027         devoe => devoe,
4028         outclkena => VCC,
4029         inclkena => VCC,
4030         areset => GND,
4031         sreset => GND);
4032 \D_HSYNC_STATE_OUT_4_\: stratix_io generic map (
4033     operation_mode => "output"
4034     )
4035 port map (
4036 padio => D_HSYNC_STATEZ(4),
4037 datain => \VGA_DRIVER_UNIT.HSYNC_STATE\(4),
4038 oe => VCC,
4039         devpor => devpor,
4040         devclrn => devclrn,
4041         devoe => devoe,
4042         outclkena => VCC,
4043         inclkena => VCC,
4044         areset => GND,
4045         sreset => GND);
4046 \D_HSYNC_STATE_OUT_5_\: stratix_io generic map (
4047     operation_mode => "output"
4048     )
4049 port map (
4050 padio => D_HSYNC_STATEZ(5),
4051 datain => \VGA_DRIVER_UNIT.HSYNC_STATE\(5),
4052 oe => VCC,
4053         devpor => devpor,
4054         devclrn => devclrn,
4055         devoe => devoe,
4056         outclkena => VCC,
4057         inclkena => VCC,
4058         areset => GND,
4059         sreset => GND);
4060 \D_HSYNC_STATE_OUT_6_\: stratix_io generic map (
4061     operation_mode => "output"
4062     )
4063 port map (
4064 padio => D_HSYNC_STATEZ(6),
4065 datain => \VGA_DRIVER_UNIT.HSYNC_STATE\(6),
4066 oe => VCC,
4067         devpor => devpor,
4068         devclrn => devclrn,
4069         devoe => devoe,
4070         outclkena => VCC,
4071         inclkena => VCC,
4072         areset => GND,
4073         sreset => GND);
4074 D_B_OUT: stratix_io generic map (
4075     operation_mode => "output"
4076     )
4077 port map (
4078 padio => D_BZ,
4079 datain => \VGA_CONTROL_UNIT.B\,
4080 oe => VCC,
4081         devpor => devpor,
4082         devclrn => devclrn,
4083         devoe => devoe,
4084         outclkena => VCC,
4085         inclkena => VCC,
4086         areset => GND,
4087         sreset => GND);
4088 D_G_OUT: stratix_io generic map (
4089     operation_mode => "output"
4090     )
4091 port map (
4092 padio => D_GZ,
4093 datain => \VGA_CONTROL_UNIT.G\,
4094 oe => VCC,
4095         devpor => devpor,
4096         devclrn => devclrn,
4097         devoe => devoe,
4098         outclkena => VCC,
4099         inclkena => VCC,
4100         areset => GND,
4101         sreset => GND);
4102 D_R_OUT: stratix_io generic map (
4103     operation_mode => "output"
4104     )
4105 port map (
4106 padio => D_RZ,
4107 datain => \VGA_CONTROL_UNIT.R\,
4108 oe => VCC,
4109         devpor => devpor,
4110         devclrn => devclrn,
4111         devoe => devoe,
4112         outclkena => VCC,
4113         inclkena => VCC,
4114         areset => GND,
4115         sreset => GND);
4116 D_V_ENABLE_OUT: stratix_io generic map (
4117     operation_mode => "output"
4118     )
4119 port map (
4120 padio => D_V_ENABLEZ,
4121 datain => \VGA_DRIVER_UNIT.V_ENABLE_SIG\,
4122 oe => VCC,
4123         devpor => devpor,
4124         devclrn => devclrn,
4125         devoe => devoe,
4126         outclkena => VCC,
4127         inclkena => VCC,
4128         areset => GND,
4129         sreset => GND);
4130 D_H_ENABLE_OUT: stratix_io generic map (
4131     operation_mode => "output"
4132     )
4133 port map (
4134 padio => D_H_ENABLEZ,
4135 datain => \VGA_DRIVER_UNIT.H_ENABLE_SIG\,
4136 oe => VCC,
4137         devpor => devpor,
4138         devclrn => devclrn,
4139         devoe => devoe,
4140         outclkena => VCC,
4141         inclkena => VCC,
4142         areset => GND,
4143         sreset => GND);
4144 D_SET_VSYNC_COUNTER_OUT: stratix_io generic map (
4145     operation_mode => "output"
4146     )
4147 port map (
4148 padio => D_SET_VSYNC_COUNTERZ,
4149 datain => \VGA_DRIVER_UNIT.D_SET_VSYNC_COUNTER\,
4150 oe => VCC,
4151         devpor => devpor,
4152         devclrn => devclrn,
4153         devoe => devoe,
4154         outclkena => VCC,
4155         inclkena => VCC,
4156         areset => GND,
4157         sreset => GND);
4158 D_SET_HSYNC_COUNTER_OUT: stratix_io generic map (
4159     operation_mode => "output"
4160     )
4161 port map (
4162 padio => D_SET_HSYNC_COUNTERZ,
4163 datain => \VGA_DRIVER_UNIT.D_SET_HSYNC_COUNTER\,
4164 oe => VCC,
4165         devpor => devpor,
4166         devclrn => devclrn,
4167         devoe => devoe,
4168         outclkena => VCC,
4169         inclkena => VCC,
4170         areset => GND,
4171         sreset => GND);
4172 \D_VSYNC_COUNTER_OUT_9_\: stratix_io generic map (
4173     operation_mode => "output"
4174     )
4175 port map (
4176 padio => D_VSYNC_COUNTERZ(9),
4177 datain => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(9),
4178 oe => VCC,
4179         devpor => devpor,
4180         devclrn => devclrn,
4181         devoe => devoe,
4182         outclkena => VCC,
4183         inclkena => VCC,
4184         areset => GND,
4185         sreset => GND);
4186 \D_VSYNC_COUNTER_OUT_8_\: stratix_io generic map (
4187     operation_mode => "output"
4188     )
4189 port map (
4190 padio => D_VSYNC_COUNTERZ(8),
4191 datain => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(8),
4192 oe => VCC,
4193         devpor => devpor,
4194         devclrn => devclrn,
4195         devoe => devoe,
4196         outclkena => VCC,
4197         inclkena => VCC,
4198         areset => GND,
4199         sreset => GND);
4200 \D_VSYNC_COUNTER_OUT_7_\: stratix_io generic map (
4201     operation_mode => "output"
4202     )
4203 port map (
4204 padio => D_VSYNC_COUNTERZ(7),
4205 datain => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(7),
4206 oe => VCC,
4207         devpor => devpor,
4208         devclrn => devclrn,
4209         devoe => devoe,
4210         outclkena => VCC,
4211         inclkena => VCC,
4212         areset => GND,
4213         sreset => GND);
4214 \D_VSYNC_COUNTER_OUT_6_\: stratix_io generic map (
4215     operation_mode => "output"
4216     )
4217 port map (
4218 padio => D_VSYNC_COUNTERZ(6),
4219 datain => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(6),
4220 oe => VCC,
4221         devpor => devpor,
4222         devclrn => devclrn,
4223         devoe => devoe,
4224         outclkena => VCC,
4225         inclkena => VCC,
4226         areset => GND,
4227         sreset => GND);
4228 \D_VSYNC_COUNTER_OUT_5_\: stratix_io generic map (
4229     operation_mode => "output"
4230     )
4231 port map (
4232 padio => D_VSYNC_COUNTERZ(5),
4233 datain => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(5),
4234 oe => VCC,
4235         devpor => devpor,
4236         devclrn => devclrn,
4237         devoe => devoe,
4238         outclkena => VCC,
4239         inclkena => VCC,
4240         areset => GND,
4241         sreset => GND);
4242 \D_VSYNC_COUNTER_OUT_4_\: stratix_io generic map (
4243     operation_mode => "output"
4244     )
4245 port map (
4246 padio => D_VSYNC_COUNTERZ(4),
4247 datain => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(4),
4248 oe => VCC,
4249         devpor => devpor,
4250         devclrn => devclrn,
4251         devoe => devoe,
4252         outclkena => VCC,
4253         inclkena => VCC,
4254         areset => GND,
4255         sreset => GND);
4256 \D_VSYNC_COUNTER_OUT_3_\: stratix_io generic map (
4257     operation_mode => "output"
4258     )
4259 port map (
4260 padio => D_VSYNC_COUNTERZ(3),
4261 datain => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(3),
4262 oe => VCC,
4263         devpor => devpor,
4264         devclrn => devclrn,
4265         devoe => devoe,
4266         outclkena => VCC,
4267         inclkena => VCC,
4268         areset => GND,
4269         sreset => GND);
4270 \D_VSYNC_COUNTER_OUT_2_\: stratix_io generic map (
4271     operation_mode => "output"
4272     )
4273 port map (
4274 padio => D_VSYNC_COUNTERZ(2),
4275 datain => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(2),
4276 oe => VCC,
4277         devpor => devpor,
4278         devclrn => devclrn,
4279         devoe => devoe,
4280         outclkena => VCC,
4281         inclkena => VCC,
4282         areset => GND,
4283         sreset => GND);
4284 \D_VSYNC_COUNTER_OUT_1_\: stratix_io generic map (
4285     operation_mode => "output"
4286     )
4287 port map (
4288 padio => D_VSYNC_COUNTERZ(1),
4289 datain => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(1),
4290 oe => VCC,
4291         devpor => devpor,
4292         devclrn => devclrn,
4293         devoe => devoe,
4294         outclkena => VCC,
4295         inclkena => VCC,
4296         areset => GND,
4297         sreset => GND);
4298 \D_VSYNC_COUNTER_OUT_0_\: stratix_io generic map (
4299     operation_mode => "output"
4300     )
4301 port map (
4302 padio => D_VSYNC_COUNTERZ(0),
4303 datain => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(0),
4304 oe => VCC,
4305         devpor => devpor,
4306         devclrn => devclrn,
4307         devoe => devoe,
4308         outclkena => VCC,
4309         inclkena => VCC,
4310         areset => GND,
4311         sreset => GND);
4312 \D_HSYNC_COUNTER_OUT_9_\: stratix_io generic map (
4313     operation_mode => "output"
4314     )
4315 port map (
4316 padio => D_HSYNC_COUNTERZ(9),
4317 datain => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(9),
4318 oe => VCC,
4319         devpor => devpor,
4320         devclrn => devclrn,
4321         devoe => devoe,
4322         outclkena => VCC,
4323         inclkena => VCC,
4324         areset => GND,
4325         sreset => GND);
4326 \D_HSYNC_COUNTER_OUT_8_\: stratix_io generic map (
4327     operation_mode => "output"
4328     )
4329 port map (
4330 padio => D_HSYNC_COUNTERZ(8),
4331 datain => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(8),
4332 oe => VCC,
4333         devpor => devpor,
4334         devclrn => devclrn,
4335         devoe => devoe,
4336         outclkena => VCC,
4337         inclkena => VCC,
4338         areset => GND,
4339         sreset => GND);
4340 \D_HSYNC_COUNTER_OUT_7_\: stratix_io generic map (
4341     operation_mode => "output"
4342     )
4343 port map (
4344 padio => D_HSYNC_COUNTERZ(7),
4345 datain => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(7),
4346 oe => VCC,
4347         devpor => devpor,
4348         devclrn => devclrn,
4349         devoe => devoe,
4350         outclkena => VCC,
4351         inclkena => VCC,
4352         areset => GND,
4353         sreset => GND);
4354 \D_HSYNC_COUNTER_OUT_6_\: stratix_io generic map (
4355     operation_mode => "output"
4356     )
4357 port map (
4358 padio => D_HSYNC_COUNTERZ(6),
4359 datain => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(6),
4360 oe => VCC,
4361         devpor => devpor,
4362         devclrn => devclrn,
4363         devoe => devoe,
4364         outclkena => VCC,
4365         inclkena => VCC,
4366         areset => GND,
4367         sreset => GND);
4368 \D_HSYNC_COUNTER_OUT_5_\: stratix_io generic map (
4369     operation_mode => "output"
4370     )
4371 port map (
4372 padio => D_HSYNC_COUNTERZ(5),
4373 datain => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(5),
4374 oe => VCC,
4375         devpor => devpor,
4376         devclrn => devclrn,
4377         devoe => devoe,
4378         outclkena => VCC,
4379         inclkena => VCC,
4380         areset => GND,
4381         sreset => GND);
4382 \D_HSYNC_COUNTER_OUT_4_\: stratix_io generic map (
4383     operation_mode => "output"
4384     )
4385 port map (
4386 padio => D_HSYNC_COUNTERZ(4),
4387 datain => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(4),
4388 oe => VCC,
4389         devpor => devpor,
4390         devclrn => devclrn,
4391         devoe => devoe,
4392         outclkena => VCC,
4393         inclkena => VCC,
4394         areset => GND,
4395         sreset => GND);
4396 \D_HSYNC_COUNTER_OUT_3_\: stratix_io generic map (
4397     operation_mode => "output"
4398     )
4399 port map (
4400 padio => D_HSYNC_COUNTERZ(3),
4401 datain => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(3),
4402 oe => VCC,
4403         devpor => devpor,
4404         devclrn => devclrn,
4405         devoe => devoe,
4406         outclkena => VCC,
4407         inclkena => VCC,
4408         areset => GND,
4409         sreset => GND);
4410 \D_HSYNC_COUNTER_OUT_2_\: stratix_io generic map (
4411     operation_mode => "output"
4412     )
4413 port map (
4414 padio => D_HSYNC_COUNTERZ(2),
4415 datain => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(2),
4416 oe => VCC,
4417         devpor => devpor,
4418         devclrn => devclrn,
4419         devoe => devoe,
4420         outclkena => VCC,
4421         inclkena => VCC,
4422         areset => GND,
4423         sreset => GND);
4424 \D_HSYNC_COUNTER_OUT_1_\: stratix_io generic map (
4425     operation_mode => "output"
4426     )
4427 port map (
4428 padio => D_HSYNC_COUNTERZ(1),
4429 datain => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(1),
4430 oe => VCC,
4431         devpor => devpor,
4432         devclrn => devclrn,
4433         devoe => devoe,
4434         outclkena => VCC,
4435         inclkena => VCC,
4436         areset => GND,
4437         sreset => GND);
4438 \D_HSYNC_COUNTER_OUT_0_\: stratix_io generic map (
4439     operation_mode => "output"
4440     )
4441 port map (
4442 padio => D_HSYNC_COUNTERZ(0),
4443 datain => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(0),
4444 oe => VCC,
4445         devpor => devpor,
4446         devclrn => devclrn,
4447         devoe => devoe,
4448         outclkena => VCC,
4449         inclkena => VCC,
4450         areset => GND,
4451         sreset => GND);
4452 D_SET_LINE_COUNTER_OUT: stratix_io generic map (
4453     operation_mode => "output"
4454     )
4455 port map (
4456 padio => D_SET_LINE_COUNTERZ,
4457 datain => \VGA_DRIVER_UNIT.VSYNC_STATE\(1),
4458 oe => VCC,
4459         devpor => devpor,
4460         devclrn => devclrn,
4461         devoe => devoe,
4462         outclkena => VCC,
4463         inclkena => VCC,
4464         areset => GND,
4465         sreset => GND);
4466 D_SET_COLUMN_COUNTER_OUT: stratix_io generic map (
4467     operation_mode => "output"
4468     )
4469 port map (
4470 padio => D_SET_COLUMN_COUNTERZ,
4471 datain => \VGA_DRIVER_UNIT.HSYNC_STATE\(1),
4472 oe => VCC,
4473         devpor => devpor,
4474         devclrn => devclrn,
4475         devoe => devoe,
4476         outclkena => VCC,
4477         inclkena => VCC,
4478         areset => GND,
4479         sreset => GND);
4480 \D_LINE_COUNTER_OUT_8_\: stratix_io generic map (
4481     operation_mode => "output"
4482     )
4483 port map (
4484 padio => D_LINE_COUNTERZ(8),
4485 datain => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(8),
4486 oe => VCC,
4487         devpor => devpor,
4488         devclrn => devclrn,
4489         devoe => devoe,
4490         outclkena => VCC,
4491         inclkena => VCC,
4492         areset => GND,
4493         sreset => GND);
4494 \D_LINE_COUNTER_OUT_7_\: stratix_io generic map (
4495     operation_mode => "output"
4496     )
4497 port map (
4498 padio => D_LINE_COUNTERZ(7),
4499 datain => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(7),
4500 oe => VCC,
4501         devpor => devpor,
4502         devclrn => devclrn,
4503         devoe => devoe,
4504         outclkena => VCC,
4505         inclkena => VCC,
4506         areset => GND,
4507         sreset => GND);
4508 \D_LINE_COUNTER_OUT_6_\: stratix_io generic map (
4509     operation_mode => "output"
4510     )
4511 port map (
4512 padio => D_LINE_COUNTERZ(6),
4513 datain => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(6),
4514 oe => VCC,
4515         devpor => devpor,
4516         devclrn => devclrn,
4517         devoe => devoe,
4518         outclkena => VCC,
4519         inclkena => VCC,
4520         areset => GND,
4521         sreset => GND);
4522 \D_LINE_COUNTER_OUT_5_\: stratix_io generic map (
4523     operation_mode => "output"
4524     )
4525 port map (
4526 padio => D_LINE_COUNTERZ(5),
4527 datain => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(5),
4528 oe => VCC,
4529         devpor => devpor,
4530         devclrn => devclrn,
4531         devoe => devoe,
4532         outclkena => VCC,
4533         inclkena => VCC,
4534         areset => GND,
4535         sreset => GND);
4536 \D_LINE_COUNTER_OUT_4_\: stratix_io generic map (
4537     operation_mode => "output"
4538     )
4539 port map (
4540 padio => D_LINE_COUNTERZ(4),
4541 datain => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(4),
4542 oe => VCC,
4543         devpor => devpor,
4544         devclrn => devclrn,
4545         devoe => devoe,
4546         outclkena => VCC,
4547         inclkena => VCC,
4548         areset => GND,
4549         sreset => GND);
4550 \D_LINE_COUNTER_OUT_3_\: stratix_io generic map (
4551     operation_mode => "output"
4552     )
4553 port map (
4554 padio => D_LINE_COUNTERZ(3),
4555 datain => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(3),
4556 oe => VCC,
4557         devpor => devpor,
4558         devclrn => devclrn,
4559         devoe => devoe,
4560         outclkena => VCC,
4561         inclkena => VCC,
4562         areset => GND,
4563         sreset => GND);
4564 \D_LINE_COUNTER_OUT_2_\: stratix_io generic map (
4565     operation_mode => "output"
4566     )
4567 port map (
4568 padio => D_LINE_COUNTERZ(2),
4569 datain => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(2),
4570 oe => VCC,
4571         devpor => devpor,
4572         devclrn => devclrn,
4573         devoe => devoe,
4574         outclkena => VCC,
4575         inclkena => VCC,
4576         areset => GND,
4577         sreset => GND);
4578 \D_LINE_COUNTER_OUT_1_\: stratix_io generic map (
4579     operation_mode => "output"
4580     )
4581 port map (
4582 padio => D_LINE_COUNTERZ(1),
4583 datain => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(1),
4584 oe => VCC,
4585         devpor => devpor,
4586         devclrn => devclrn,
4587         devoe => devoe,
4588         outclkena => VCC,
4589         inclkena => VCC,
4590         areset => GND,
4591         sreset => GND);
4592 \D_LINE_COUNTER_OUT_0_\: stratix_io generic map (
4593     operation_mode => "output"
4594     )
4595 port map (
4596 padio => D_LINE_COUNTERZ(0),
4597 datain => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(0),
4598 oe => VCC,
4599         devpor => devpor,
4600         devclrn => devclrn,
4601         devoe => devoe,
4602         outclkena => VCC,
4603         inclkena => VCC,
4604         areset => GND,
4605         sreset => GND);
4606 \D_COLUMN_COUNTER_OUT_9_\: stratix_io generic map (
4607     operation_mode => "output"
4608     )
4609 port map (
4610 padio => D_COLUMN_COUNTERZ(9),
4611 datain => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(9),
4612 oe => VCC,
4613         devpor => devpor,
4614         devclrn => devclrn,
4615         devoe => devoe,
4616         outclkena => VCC,
4617         inclkena => VCC,
4618         areset => GND,
4619         sreset => GND);
4620 \D_COLUMN_COUNTER_OUT_8_\: stratix_io generic map (
4621     operation_mode => "output"
4622     )
4623 port map (
4624 padio => D_COLUMN_COUNTERZ(8),
4625 datain => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(8),
4626 oe => VCC,
4627         devpor => devpor,
4628         devclrn => devclrn,
4629         devoe => devoe,
4630         outclkena => VCC,
4631         inclkena => VCC,
4632         areset => GND,
4633         sreset => GND);
4634 \D_COLUMN_COUNTER_OUT_7_\: stratix_io generic map (
4635     operation_mode => "output"
4636     )
4637 port map (
4638 padio => D_COLUMN_COUNTERZ(7),
4639 datain => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(7),
4640 oe => VCC,
4641         devpor => devpor,
4642         devclrn => devclrn,
4643         devoe => devoe,
4644         outclkena => VCC,
4645         inclkena => VCC,
4646         areset => GND,
4647         sreset => GND);
4648 \D_COLUMN_COUNTER_OUT_6_\: stratix_io generic map (
4649     operation_mode => "output"
4650     )
4651 port map (
4652 padio => D_COLUMN_COUNTERZ(6),
4653 datain => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(6),
4654 oe => VCC,
4655         devpor => devpor,
4656         devclrn => devclrn,
4657         devoe => devoe,
4658         outclkena => VCC,
4659         inclkena => VCC,
4660         areset => GND,
4661         sreset => GND);
4662 \D_COLUMN_COUNTER_OUT_5_\: stratix_io generic map (
4663     operation_mode => "output"
4664     )
4665 port map (
4666 padio => D_COLUMN_COUNTERZ(5),
4667 datain => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(5),
4668 oe => VCC,
4669         devpor => devpor,
4670         devclrn => devclrn,
4671         devoe => devoe,
4672         outclkena => VCC,
4673         inclkena => VCC,
4674         areset => GND,
4675         sreset => GND);
4676 \D_COLUMN_COUNTER_OUT_4_\: stratix_io generic map (
4677     operation_mode => "output"
4678     )
4679 port map (
4680 padio => D_COLUMN_COUNTERZ(4),
4681 datain => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(4),
4682 oe => VCC,
4683         devpor => devpor,
4684         devclrn => devclrn,
4685         devoe => devoe,
4686         outclkena => VCC,
4687         inclkena => VCC,
4688         areset => GND,
4689         sreset => GND);
4690 \D_COLUMN_COUNTER_OUT_3_\: stratix_io generic map (
4691     operation_mode => "output"
4692     )
4693 port map (
4694 padio => D_COLUMN_COUNTERZ(3),
4695 datain => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(3),
4696 oe => VCC,
4697         devpor => devpor,
4698         devclrn => devclrn,
4699         devoe => devoe,
4700         outclkena => VCC,
4701         inclkena => VCC,
4702         areset => GND,
4703         sreset => GND);
4704 \D_COLUMN_COUNTER_OUT_2_\: stratix_io generic map (
4705     operation_mode => "output"
4706     )
4707 port map (
4708 padio => D_COLUMN_COUNTERZ(2),
4709 datain => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(2),
4710 oe => VCC,
4711         devpor => devpor,
4712         devclrn => devclrn,
4713         devoe => devoe,
4714         outclkena => VCC,
4715         inclkena => VCC,
4716         areset => GND,
4717         sreset => GND);
4718 \D_COLUMN_COUNTER_OUT_1_\: stratix_io generic map (
4719     operation_mode => "output"
4720     )
4721 port map (
4722 padio => D_COLUMN_COUNTERZ(1),
4723 datain => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(1),
4724 oe => VCC,
4725         devpor => devpor,
4726         devclrn => devclrn,
4727         devoe => devoe,
4728         outclkena => VCC,
4729         inclkena => VCC,
4730         areset => GND,
4731         sreset => GND);
4732 \D_COLUMN_COUNTER_OUT_0_\: stratix_io generic map (
4733     operation_mode => "output"
4734     )
4735 port map (
4736 padio => D_COLUMN_COUNTERZ(0),
4737 datain => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(0),
4738 oe => VCC,
4739         devpor => devpor,
4740         devclrn => devclrn,
4741         devoe => devoe,
4742         outclkena => VCC,
4743         inclkena => VCC,
4744         areset => GND,
4745         sreset => GND);
4746 D_VSYNC_OUT: stratix_io generic map (
4747     operation_mode => "output"
4748     )
4749 port map (
4750 padio => D_VSYNCZ,
4751 datain => \VGA_DRIVER_UNIT.V_SYNC\,
4752 oe => VCC,
4753         devpor => devpor,
4754         devclrn => devclrn,
4755         devoe => devoe,
4756         outclkena => VCC,
4757         inclkena => VCC,
4758         areset => GND,
4759         sreset => GND);
4760 D_HSYNC_OUT: stratix_io generic map (
4761     operation_mode => "output"
4762     )
4763 port map (
4764 padio => D_HSYNCZ,
4765 datain => \VGA_DRIVER_UNIT.H_SYNC\,
4766 oe => VCC,
4767         devpor => devpor,
4768         devclrn => devclrn,
4769         devoe => devoe,
4770         outclkena => VCC,
4771         inclkena => VCC,
4772         areset => GND,
4773         sreset => GND);
4774 \SEVEN_SEG_PIN_TRI_13_\: stratix_io generic map (
4775     operation_mode => "output"
4776     )
4777 port map (
4778 padio => SEVEN_SEG_PINZ(13),
4779 datain => VCC,
4780 oe => VCC,
4781         devpor => devpor,
4782         devclrn => devclrn,
4783         devoe => devoe,
4784         outclkena => VCC,
4785         inclkena => VCC,
4786         areset => GND,
4787         sreset => GND);
4788 \SEVEN_SEG_PIN_OUT_12_\: stratix_io generic map (
4789     operation_mode => "output"
4790     )
4791 port map (
4792 padio => SEVEN_SEG_PINZ(12),
4793 datain => \DELAY_RESET_NEXT.UN6_DLY_COUNTER_0_X\,
4794 oe => VCC,
4795         devpor => devpor,
4796         devclrn => devclrn,
4797         devoe => devoe,
4798         outclkena => VCC,
4799         inclkena => VCC,
4800         areset => GND,
4801         sreset => GND);
4802 \SEVEN_SEG_PIN_OUT_11_\: stratix_io generic map (
4803     operation_mode => "output"
4804     )
4805 port map (
4806 padio => SEVEN_SEG_PINZ(11),
4807 datain => \DELAY_RESET_NEXT.UN6_DLY_COUNTER_0_X\,
4808 oe => VCC,
4809         devpor => devpor,
4810         devclrn => devclrn,
4811         devoe => devoe,
4812         outclkena => VCC,
4813         inclkena => VCC,
4814         areset => GND,
4815         sreset => GND);
4816 \SEVEN_SEG_PIN_OUT_10_\: stratix_io generic map (
4817     operation_mode => "output"
4818     )
4819 port map (
4820 padio => SEVEN_SEG_PINZ(10),
4821 datain => \DELAY_RESET_NEXT.UN6_DLY_COUNTER_0_X\,
4822 oe => VCC,
4823         devpor => devpor,
4824         devclrn => devclrn,
4825         devoe => devoe,
4826         outclkena => VCC,
4827         inclkena => VCC,
4828         areset => GND,
4829         sreset => GND);
4830 \SEVEN_SEG_PIN_OUT_9_\: stratix_io generic map (
4831     operation_mode => "output"
4832     )
4833 port map (
4834 padio => SEVEN_SEG_PINZ(9),
4835 datain => \DELAY_RESET_NEXT.UN6_DLY_COUNTER_0_X\,
4836 oe => VCC,
4837         devpor => devpor,
4838         devclrn => devclrn,
4839         devoe => devoe,
4840         outclkena => VCC,
4841         inclkena => VCC,
4842         areset => GND,
4843         sreset => GND);
4844 \SEVEN_SEG_PIN_OUT_8_\: stratix_io generic map (
4845     operation_mode => "output"
4846     )
4847 port map (
4848 padio => SEVEN_SEG_PINZ(8),
4849 datain => \DELAY_RESET_NEXT.UN6_DLY_COUNTER_0_X\,
4850 oe => VCC,
4851         devpor => devpor,
4852         devclrn => devclrn,
4853         devoe => devoe,
4854         outclkena => VCC,
4855         inclkena => VCC,
4856         areset => GND,
4857         sreset => GND);
4858 \SEVEN_SEG_PIN_OUT_7_\: stratix_io generic map (
4859     operation_mode => "output"
4860     )
4861 port map (
4862 padio => SEVEN_SEG_PINZ(7),
4863 datain => \DELAY_RESET_NEXT.UN6_DLY_COUNTER_0_X\,
4864 oe => VCC,
4865         devpor => devpor,
4866         devclrn => devclrn,
4867         devoe => devoe,
4868         outclkena => VCC,
4869         inclkena => VCC,
4870         areset => GND,
4871         sreset => GND);
4872 \SEVEN_SEG_PIN_TRI_6_\: stratix_io generic map (
4873     operation_mode => "output"
4874     )
4875 port map (
4876 padio => SEVEN_SEG_PINZ(6),
4877 datain => VCC,
4878 oe => VCC,
4879         devpor => devpor,
4880         devclrn => devclrn,
4881         devoe => devoe,
4882         outclkena => VCC,
4883         inclkena => VCC,
4884         areset => GND,
4885         sreset => GND);
4886 \SEVEN_SEG_PIN_TRI_5_\: stratix_io generic map (
4887     operation_mode => "output"
4888     )
4889 port map (
4890 padio => SEVEN_SEG_PINZ(5),
4891 datain => VCC,
4892 oe => VCC,
4893         devpor => devpor,
4894         devclrn => devclrn,
4895         devoe => devoe,
4896         outclkena => VCC,
4897         inclkena => VCC,
4898         areset => GND,
4899         sreset => GND);
4900 \SEVEN_SEG_PIN_TRI_4_\: stratix_io generic map (
4901     operation_mode => "output"
4902     )
4903 port map (
4904 padio => SEVEN_SEG_PINZ(4),
4905 datain => VCC,
4906 oe => VCC,
4907         devpor => devpor,
4908         devclrn => devclrn,
4909         devoe => devoe,
4910         outclkena => VCC,
4911         inclkena => VCC,
4912         areset => GND,
4913         sreset => GND);
4914 \SEVEN_SEG_PIN_TRI_3_\: stratix_io generic map (
4915     operation_mode => "output"
4916     )
4917 port map (
4918 padio => SEVEN_SEG_PINZ(3),
4919 datain => VCC,
4920 oe => VCC,
4921         devpor => devpor,
4922         devclrn => devclrn,
4923         devoe => devoe,
4924         outclkena => VCC,
4925         inclkena => VCC,
4926         areset => GND,
4927         sreset => GND);
4928 \SEVEN_SEG_PIN_OUT_2_\: stratix_io generic map (
4929     operation_mode => "output"
4930     )
4931 port map (
4932 padio => SEVEN_SEG_PINZ(2),
4933 datain => \DELAY_RESET_NEXT.UN6_DLY_COUNTER_0_X\,
4934 oe => VCC,
4935         devpor => devpor,
4936         devclrn => devclrn,
4937         devoe => devoe,
4938         outclkena => VCC,
4939         inclkena => VCC,
4940         areset => GND,
4941         sreset => GND);
4942 \SEVEN_SEG_PIN_OUT_1_\: stratix_io generic map (
4943     operation_mode => "output"
4944     )
4945 port map (
4946 padio => SEVEN_SEG_PINZ(1),
4947 datain => \DELAY_RESET_NEXT.UN6_DLY_COUNTER_0_X\,
4948 oe => VCC,
4949         devpor => devpor,
4950         devclrn => devclrn,
4951         devoe => devoe,
4952         outclkena => VCC,
4953         inclkena => VCC,
4954         areset => GND,
4955         sreset => GND);
4956 \SEVEN_SEG_PIN_TRI_0_\: stratix_io generic map (
4957     operation_mode => "output"
4958     )
4959 port map (
4960 padio => SEVEN_SEG_PINZ(0),
4961 datain => VCC,
4962 oe => VCC,
4963         devpor => devpor,
4964         devclrn => devclrn,
4965         devoe => devoe,
4966         outclkena => VCC,
4967         inclkena => VCC,
4968         areset => GND,
4969         sreset => GND);
4970 VSYNC_PIN_OUT: stratix_io generic map (
4971     operation_mode => "output"
4972     )
4973 port map (
4974 padio => VSYNC_PINZ,
4975 datain => \VGA_DRIVER_UNIT.V_SYNC\,
4976 oe => VCC,
4977         devpor => devpor,
4978         devclrn => devclrn,
4979         devoe => devoe,
4980         outclkena => VCC,
4981         inclkena => VCC,
4982         areset => GND,
4983         sreset => GND);
4984 HSYNC_PIN_OUT: stratix_io generic map (
4985     operation_mode => "output"
4986     )
4987 port map (
4988 padio => HSYNC_PINZ,
4989 datain => \VGA_DRIVER_UNIT.H_SYNC\,
4990 oe => VCC,
4991         devpor => devpor,
4992         devclrn => devclrn,
4993         devoe => devoe,
4994         outclkena => VCC,
4995         inclkena => VCC,
4996         areset => GND,
4997         sreset => GND);
4998 B1_PIN_OUT: stratix_io generic map (
4999     operation_mode => "output"
5000     )
5001 port map (
5002 padio => B1_PINZ,
5003 datain => \VGA_CONTROL_UNIT.B\,
5004 oe => VCC,
5005         devpor => devpor,
5006         devclrn => devclrn,
5007         devoe => devoe,
5008         outclkena => VCC,
5009         inclkena => VCC,
5010         areset => GND,
5011         sreset => GND);
5012 B0_PIN_OUT: stratix_io generic map (
5013     operation_mode => "output"
5014     )
5015 port map (
5016 padio => B0_PINZ,
5017 datain => \VGA_CONTROL_UNIT.B\,
5018 oe => VCC,
5019         devpor => devpor,
5020         devclrn => devclrn,
5021         devoe => devoe,
5022         outclkena => VCC,
5023         inclkena => VCC,
5024         areset => GND,
5025         sreset => GND);
5026 G2_PIN_OUT: stratix_io generic map (
5027     operation_mode => "output"
5028     )
5029 port map (
5030 padio => G2_PINZ,
5031 datain => \VGA_CONTROL_UNIT.G\,
5032 oe => VCC,
5033         devpor => devpor,
5034         devclrn => devclrn,
5035         devoe => devoe,
5036         outclkena => VCC,
5037         inclkena => VCC,
5038         areset => GND,
5039         sreset => GND);
5040 G1_PIN_OUT: stratix_io generic map (
5041     operation_mode => "output"
5042     )
5043 port map (
5044 padio => G1_PINZ,
5045 datain => \VGA_CONTROL_UNIT.G\,
5046 oe => VCC,
5047         devpor => devpor,
5048         devclrn => devclrn,
5049         devoe => devoe,
5050         outclkena => VCC,
5051         inclkena => VCC,
5052         areset => GND,
5053         sreset => GND);
5054 G0_PIN_OUT: stratix_io generic map (
5055     operation_mode => "output"
5056     )
5057 port map (
5058 padio => G0_PINZ,
5059 datain => \VGA_CONTROL_UNIT.G\,
5060 oe => VCC,
5061         devpor => devpor,
5062         devclrn => devclrn,
5063         devoe => devoe,
5064         outclkena => VCC,
5065         inclkena => VCC,
5066         areset => GND,
5067         sreset => GND);
5068 R2_PIN_OUT: stratix_io generic map (
5069     operation_mode => "output"
5070     )
5071 port map (
5072 padio => R2_PINZ,
5073 datain => \VGA_CONTROL_UNIT.R\,
5074 oe => VCC,
5075         devpor => devpor,
5076         devclrn => devclrn,
5077         devoe => devoe,
5078         outclkena => VCC,
5079         inclkena => VCC,
5080         areset => GND,
5081         sreset => GND);
5082 R1_PIN_OUT: stratix_io generic map (
5083     operation_mode => "output"
5084     )
5085 port map (
5086 padio => R1_PINZ,
5087 datain => \VGA_CONTROL_UNIT.R\,
5088 oe => VCC,
5089         devpor => devpor,
5090         devclrn => devclrn,
5091         devoe => devoe,
5092         outclkena => VCC,
5093         inclkena => VCC,
5094         areset => GND,
5095         sreset => GND);
5096 R0_PIN_OUT: stratix_io generic map (
5097     operation_mode => "output"
5098     )
5099 port map (
5100 padio => R0_PINZ,
5101 datain => \VGA_CONTROL_UNIT.R\,
5102 oe => VCC,
5103         devpor => devpor,
5104         devclrn => devclrn,
5105         devoe => devoe,
5106         outclkena => VCC,
5107         inclkena => VCC,
5108         areset => GND,
5109         sreset => GND);
5110 G_49 <= CLK_PIN_C;
5111 VGA_DRIVER_UNIT: vga_driver port map (
5112 line_counter_sig_0 => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(0),
5113 line_counter_sig_1 => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(1),
5114 line_counter_sig_2 => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(2),
5115 line_counter_sig_3 => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(3),
5116 line_counter_sig_4 => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(4),
5117 line_counter_sig_5 => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(5),
5118 line_counter_sig_6 => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(6),
5119 line_counter_sig_7 => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(7),
5120 line_counter_sig_8 => \VGA_DRIVER_UNIT.LINE_COUNTER_SIG\(8),
5121 dly_counter_1 => DLY_COUNTER(1),
5122 dly_counter_0 => DLY_COUNTER(0),
5123 vsync_state_2 => \VGA_DRIVER_UNIT.VSYNC_STATE\(2),
5124 vsync_state_5 => \VGA_DRIVER_UNIT.VSYNC_STATE\(5),
5125 vsync_state_3 => \VGA_DRIVER_UNIT.VSYNC_STATE\(3),
5126 vsync_state_6 => \VGA_DRIVER_UNIT.VSYNC_STATE\(6),
5127 vsync_state_4 => \VGA_DRIVER_UNIT.VSYNC_STATE\(4),
5128 vsync_state_1 => \VGA_DRIVER_UNIT.VSYNC_STATE\(1),
5129 vsync_state_0 => \VGA_DRIVER_UNIT.VSYNC_STATE\(0),
5130 hsync_state_2 => \VGA_DRIVER_UNIT.HSYNC_STATE\(2),
5131 hsync_state_4 => \VGA_DRIVER_UNIT.HSYNC_STATE\(4),
5132 hsync_state_0 => \VGA_DRIVER_UNIT.HSYNC_STATE\(0),
5133 hsync_state_5 => \VGA_DRIVER_UNIT.HSYNC_STATE\(5),
5134 hsync_state_1 => \VGA_DRIVER_UNIT.HSYNC_STATE\(1),
5135 hsync_state_3 => \VGA_DRIVER_UNIT.HSYNC_STATE\(3),
5136 hsync_state_6 => \VGA_DRIVER_UNIT.HSYNC_STATE\(6),
5137 column_counter_sig_0 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(0),
5138 column_counter_sig_1 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(1),
5139 column_counter_sig_2 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(2),
5140 column_counter_sig_3 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(3),
5141 column_counter_sig_4 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(4),
5142 column_counter_sig_5 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(5),
5143 column_counter_sig_6 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(6),
5144 column_counter_sig_7 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(7),
5145 column_counter_sig_8 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(8),
5146 column_counter_sig_9 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(9),
5147 vsync_counter_9 => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(9),
5148 vsync_counter_8 => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(8),
5149 vsync_counter_7 => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(7),
5150 vsync_counter_6 => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(6),
5151 vsync_counter_5 => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(5),
5152 vsync_counter_4 => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(4),
5153 vsync_counter_3 => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(3),
5154 vsync_counter_2 => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(2),
5155 vsync_counter_1 => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(1),
5156 vsync_counter_0 => \VGA_DRIVER_UNIT.VSYNC_COUNTER\(0),
5157 hsync_counter_9 => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(9),
5158 hsync_counter_8 => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(8),
5159 hsync_counter_7 => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(7),
5160 hsync_counter_6 => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(6),
5161 hsync_counter_5 => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(5),
5162 hsync_counter_4 => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(4),
5163 hsync_counter_3 => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(3),
5164 hsync_counter_2 => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(2),
5165 hsync_counter_1 => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(1),
5166 hsync_counter_0 => \VGA_DRIVER_UNIT.HSYNC_COUNTER\(0),
5167 d_set_vsync_counter => \VGA_DRIVER_UNIT.D_SET_VSYNC_COUNTER\,
5168 un10_column_counter_siglt6_1 => \VGA_DRIVER_UNIT.COLUMN_COUNT_NEXT.UN10_COLUMN_COUNTER_SIGLT6_1\,
5169 un10_column_counter_siglt6_3 => \VGA_DRIVER_UNIT.COLUMN_COUNT_NEXT.UN10_COLUMN_COUNTER_SIGLT6_3\,
5170 v_sync => \VGA_DRIVER_UNIT.V_SYNC\,
5171 h_sync => \VGA_DRIVER_UNIT.H_SYNC\,
5172 h_enable_sig => \VGA_DRIVER_UNIT.H_ENABLE_SIG\,
5173 v_enable_sig => \VGA_DRIVER_UNIT.V_ENABLE_SIG\,
5174 reset_pin_c => RESET_PIN_C,
5175 un6_dly_counter_0_x => \DELAY_RESET_NEXT.UN6_DLY_COUNTER_0_X\,
5176 d_set_hsync_counter => \VGA_DRIVER_UNIT.D_SET_HSYNC_COUNTER\,
5177 clk_pin_c => CLK_PIN_C);
5178 VGA_CONTROL_UNIT: vga_control port map (
5179 column_counter_sig_1 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(3),
5180 column_counter_sig_7 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(9),
5181 column_counter_sig_2 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(4),
5182 column_counter_sig_0 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(2),
5183 column_counter_sig_4 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(6),
5184 column_counter_sig_3 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(5),
5185 column_counter_sig_5 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(7),
5186 column_counter_sig_6 => \VGA_DRIVER_UNIT.COLUMN_COUNTER_SIG\(8),
5187 h_enable_sig => \VGA_DRIVER_UNIT.H_ENABLE_SIG\,
5188 v_enable_sig => \VGA_DRIVER_UNIT.V_ENABLE_SIG\,
5189 un10_column_counter_siglt6_1 => \VGA_DRIVER_UNIT.COLUMN_COUNT_NEXT.UN10_COLUMN_COUNTER_SIGLT6_1\,
5190 g => \VGA_CONTROL_UNIT.G\,
5191 un10_column_counter_siglt6_3 => \VGA_DRIVER_UNIT.COLUMN_COUNT_NEXT.UN10_COLUMN_COUNTER_SIGLT6_3\,
5192 r => \VGA_CONTROL_UNIT.R\,
5193 un6_dly_counter_0_x => \DELAY_RESET_NEXT.UN6_DLY_COUNTER_0_X\,
5194 clk_pin_c => CLK_PIN_C,
5195 b => \VGA_CONTROL_UNIT.B\);
5196 N_1 <= CLK_PIN_INTERNAL;
5197 N_2 <= RESET_PIN_INTERNAL;
5198 N_60_0 <= R0_PINZ;
5199 N_61_0 <= R1_PINZ;
5200 N_62_0 <= R2_PINZ;
5201 N_63_0 <= G0_PINZ;
5202 N_64_0 <= G1_PINZ;
5203 N_65_0 <= G2_PINZ;
5204 N_66_0 <= B0_PINZ;
5205 N_67_0 <= B1_PINZ;
5206 N_68_0 <= HSYNC_PINZ;
5207 N_69_0 <= VSYNC_PINZ;
5208 N_70_0 <= SEVEN_SEG_PINZ(0);
5209 N_71_0 <= SEVEN_SEG_PINZ(1);
5210 N_72_0 <= SEVEN_SEG_PINZ(2);
5211 N_73_0 <= SEVEN_SEG_PINZ(3);
5212 N_74_0 <= SEVEN_SEG_PINZ(4);
5213 N_75_0 <= SEVEN_SEG_PINZ(5);
5214 N_76_0 <= SEVEN_SEG_PINZ(6);
5215 N_77_0 <= SEVEN_SEG_PINZ(7);
5216 N_78_0 <= SEVEN_SEG_PINZ(8);
5217 N_79_0 <= SEVEN_SEG_PINZ(9);
5218 N_80_0 <= SEVEN_SEG_PINZ(10);
5219 N_81_0 <= SEVEN_SEG_PINZ(11);
5220 N_82_0 <= SEVEN_SEG_PINZ(12);
5221 N_83_0 <= SEVEN_SEG_PINZ(13);
5222 N_84_0 <= D_HSYNCZ;
5223 N_85_0 <= D_VSYNCZ;
5224 N_86_0 <= D_COLUMN_COUNTERZ(0);
5225 N_87_0 <= D_COLUMN_COUNTERZ(1);
5226 N_88_0 <= D_COLUMN_COUNTERZ(2);
5227 N_89_0 <= D_COLUMN_COUNTERZ(3);
5228 N_90_0 <= D_COLUMN_COUNTERZ(4);
5229 N_91_0 <= D_COLUMN_COUNTERZ(5);
5230 N_92 <= D_COLUMN_COUNTERZ(6);
5231 N_93 <= D_COLUMN_COUNTERZ(7);
5232 N_94 <= D_COLUMN_COUNTERZ(8);
5233 N_95 <= D_COLUMN_COUNTERZ(9);
5234 N_96 <= D_LINE_COUNTERZ(0);
5235 N_97 <= D_LINE_COUNTERZ(1);
5236 N_98 <= D_LINE_COUNTERZ(2);
5237 N_99 <= D_LINE_COUNTERZ(3);
5238 N_100 <= D_LINE_COUNTERZ(4);
5239 N_101 <= D_LINE_COUNTERZ(5);
5240 N_102 <= D_LINE_COUNTERZ(6);
5241 N_103 <= D_LINE_COUNTERZ(7);
5242 N_104 <= D_LINE_COUNTERZ(8);
5243 N_105 <= D_SET_COLUMN_COUNTERZ;
5244 N_106 <= D_SET_LINE_COUNTERZ;
5245 N_107 <= D_HSYNC_COUNTERZ(0);
5246 N_108 <= D_HSYNC_COUNTERZ(1);
5247 N_109 <= D_HSYNC_COUNTERZ(2);
5248 N_110 <= D_HSYNC_COUNTERZ(3);
5249 N_111 <= D_HSYNC_COUNTERZ(4);
5250 N_112 <= D_HSYNC_COUNTERZ(5);
5251 N_113 <= D_HSYNC_COUNTERZ(6);
5252 N_114 <= D_HSYNC_COUNTERZ(7);
5253 N_115 <= D_HSYNC_COUNTERZ(8);
5254 N_116 <= D_HSYNC_COUNTERZ(9);
5255 N_117 <= D_VSYNC_COUNTERZ(0);
5256 N_118 <= D_VSYNC_COUNTERZ(1);
5257 N_119 <= D_VSYNC_COUNTERZ(2);
5258 N_120 <= D_VSYNC_COUNTERZ(3);
5259 N_121 <= D_VSYNC_COUNTERZ(4);
5260 N_122 <= D_VSYNC_COUNTERZ(5);
5261 N_123 <= D_VSYNC_COUNTERZ(6);
5262 N_124 <= D_VSYNC_COUNTERZ(7);
5263 N_125 <= D_VSYNC_COUNTERZ(8);
5264 N_126 <= D_VSYNC_COUNTERZ(9);
5265 N_127 <= D_SET_HSYNC_COUNTERZ;
5266 N_128 <= D_SET_VSYNC_COUNTERZ;
5267 N_129 <= D_H_ENABLEZ;
5268 N_130 <= D_V_ENABLEZ;
5269 N_131 <= D_RZ;
5270 N_132 <= D_GZ;
5271 N_133 <= D_BZ;
5272 N_134 <= D_HSYNC_STATEZ(6);
5273 N_135 <= D_HSYNC_STATEZ(5);
5274 N_136 <= D_HSYNC_STATEZ(4);
5275 N_137 <= D_HSYNC_STATEZ(3);
5276 N_138 <= D_HSYNC_STATEZ(2);
5277 N_139 <= D_HSYNC_STATEZ(1);
5278 N_140 <= D_HSYNC_STATEZ(0);
5279 N_141 <= D_VSYNC_STATEZ(6);
5280 N_142 <= D_VSYNC_STATEZ(5);
5281 N_143 <= D_VSYNC_STATEZ(4);
5282 N_144 <= D_VSYNC_STATEZ(3);
5283 N_145 <= D_VSYNC_STATEZ(2);
5284 N_146 <= D_VSYNC_STATEZ(1);
5285 N_147 <= D_VSYNC_STATEZ(0);
5286 N_148 <= D_STATE_CLKZ;
5287 r0_pin <= N_60_0;
5288 r1_pin <= N_61_0;
5289 r2_pin <= N_62_0;
5290 g0_pin <= N_63_0;
5291 g1_pin <= N_64_0;
5292 g2_pin <= N_65_0;
5293 b0_pin <= N_66_0;
5294 b1_pin <= N_67_0;
5295 hsync_pin <= N_68_0;
5296 vsync_pin <= N_69_0;
5297 seven_seg_pin(0) <= N_70_0;
5298 seven_seg_pin(1) <= N_71_0;
5299 seven_seg_pin(2) <= N_72_0;
5300 seven_seg_pin(3) <= N_73_0;
5301 seven_seg_pin(4) <= N_74_0;
5302 seven_seg_pin(5) <= N_75_0;
5303 seven_seg_pin(6) <= N_76_0;
5304 seven_seg_pin(7) <= N_77_0;
5305 seven_seg_pin(8) <= N_78_0;
5306 seven_seg_pin(9) <= N_79_0;
5307 seven_seg_pin(10) <= N_80_0;
5308 seven_seg_pin(11) <= N_81_0;
5309 seven_seg_pin(12) <= N_82_0;
5310 seven_seg_pin(13) <= N_83_0;
5311 d_hsync <= N_84_0;
5312 d_vsync <= N_85_0;
5313 d_column_counter(0) <= N_86_0;
5314 d_column_counter(1) <= N_87_0;
5315 d_column_counter(2) <= N_88_0;
5316 d_column_counter(3) <= N_89_0;
5317 d_column_counter(4) <= N_90_0;
5318 d_column_counter(5) <= N_91_0;
5319 d_column_counter(6) <= N_92;
5320 d_column_counter(7) <= N_93;
5321 d_column_counter(8) <= N_94;
5322 d_column_counter(9) <= N_95;
5323 d_line_counter(0) <= N_96;
5324 d_line_counter(1) <= N_97;
5325 d_line_counter(2) <= N_98;
5326 d_line_counter(3) <= N_99;
5327 d_line_counter(4) <= N_100;
5328 d_line_counter(5) <= N_101;
5329 d_line_counter(6) <= N_102;
5330 d_line_counter(7) <= N_103;
5331 d_line_counter(8) <= N_104;
5332 d_set_column_counter <= N_105;
5333 d_set_line_counter <= N_106;
5334 d_hsync_counter(0) <= N_107;
5335 d_hsync_counter(1) <= N_108;
5336 d_hsync_counter(2) <= N_109;
5337 d_hsync_counter(3) <= N_110;
5338 d_hsync_counter(4) <= N_111;
5339 d_hsync_counter(5) <= N_112;
5340 d_hsync_counter(6) <= N_113;
5341 d_hsync_counter(7) <= N_114;
5342 d_hsync_counter(8) <= N_115;
5343 d_hsync_counter(9) <= N_116;
5344 d_vsync_counter(0) <= N_117;
5345 d_vsync_counter(1) <= N_118;
5346 d_vsync_counter(2) <= N_119;
5347 d_vsync_counter(3) <= N_120;
5348 d_vsync_counter(4) <= N_121;
5349 d_vsync_counter(5) <= N_122;
5350 d_vsync_counter(6) <= N_123;
5351 d_vsync_counter(7) <= N_124;
5352 d_vsync_counter(8) <= N_125;
5353 d_vsync_counter(9) <= N_126;
5354 d_set_hsync_counter <= N_127;
5355 d_set_vsync_counter <= N_128;
5356 d_h_enable <= N_129;
5357 d_v_enable <= N_130;
5358 d_r <= N_131;
5359 d_g <= N_132;
5360 d_b <= N_133;
5361 d_hsync_state(6) <= N_134;
5362 d_hsync_state(5) <= N_135;
5363 d_hsync_state(4) <= N_136;
5364 d_hsync_state(3) <= N_137;
5365 d_hsync_state(2) <= N_138;
5366 d_hsync_state(1) <= N_139;
5367 d_hsync_state(0) <= N_140;
5368 d_vsync_state(6) <= N_141;
5369 d_vsync_state(5) <= N_142;
5370 d_vsync_state(4) <= N_143;
5371 d_vsync_state(3) <= N_144;
5372 d_vsync_state(2) <= N_145;
5373 d_vsync_state(1) <= N_146;
5374 d_vsync_state(0) <= N_147;
5375 d_state_clk <= N_148;
5376 CLK_PIN_INTERNAL <= clk_pin;
5377 RESET_PIN_INTERNAL <= reset_pin;
5378 end beh;
5379